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a4b12990 MB |
1 | /* |
2 | * Intel SST Haswell/Broadwell IPC Support | |
3 | * | |
4 | * Copyright (C) 2013, Intel Corporation. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License version | |
8 | * 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/types.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/wait.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/workqueue.h> | |
24 | #include <linux/export.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
a4b12990 MB |
28 | #include <linux/platform_device.h> |
29 | #include <linux/kthread.h> | |
30 | #include <linux/firmware.h> | |
31 | #include <linux/dma-mapping.h> | |
32 | #include <linux/debugfs.h> | |
aed3c7b7 | 33 | #include <linux/pm_runtime.h> |
1b006996 | 34 | #include <sound/asound.h> |
a4b12990 MB |
35 | |
36 | #include "sst-haswell-ipc.h" | |
37 | #include "sst-dsp.h" | |
38 | #include "sst-dsp-priv.h" | |
39 | ||
40 | /* Global Message - Generic */ | |
41 | #define IPC_GLB_TYPE_SHIFT 24 | |
42 | #define IPC_GLB_TYPE_MASK (0x1f << IPC_GLB_TYPE_SHIFT) | |
43 | #define IPC_GLB_TYPE(x) (x << IPC_GLB_TYPE_SHIFT) | |
44 | ||
45 | /* Global Message - Reply */ | |
46 | #define IPC_GLB_REPLY_SHIFT 0 | |
47 | #define IPC_GLB_REPLY_MASK (0x1f << IPC_GLB_REPLY_SHIFT) | |
48 | #define IPC_GLB_REPLY_TYPE(x) (x << IPC_GLB_REPLY_TYPE_SHIFT) | |
49 | ||
50 | /* Stream Message - Generic */ | |
51 | #define IPC_STR_TYPE_SHIFT 20 | |
52 | #define IPC_STR_TYPE_MASK (0xf << IPC_STR_TYPE_SHIFT) | |
53 | #define IPC_STR_TYPE(x) (x << IPC_STR_TYPE_SHIFT) | |
54 | #define IPC_STR_ID_SHIFT 16 | |
55 | #define IPC_STR_ID_MASK (0xf << IPC_STR_ID_SHIFT) | |
56 | #define IPC_STR_ID(x) (x << IPC_STR_ID_SHIFT) | |
57 | ||
58 | /* Stream Message - Reply */ | |
59 | #define IPC_STR_REPLY_SHIFT 0 | |
60 | #define IPC_STR_REPLY_MASK (0x1f << IPC_STR_REPLY_SHIFT) | |
61 | ||
62 | /* Stream Stage Message - Generic */ | |
63 | #define IPC_STG_TYPE_SHIFT 12 | |
64 | #define IPC_STG_TYPE_MASK (0xf << IPC_STG_TYPE_SHIFT) | |
65 | #define IPC_STG_TYPE(x) (x << IPC_STG_TYPE_SHIFT) | |
66 | #define IPC_STG_ID_SHIFT 10 | |
67 | #define IPC_STG_ID_MASK (0x3 << IPC_STG_ID_SHIFT) | |
68 | #define IPC_STG_ID(x) (x << IPC_STG_ID_SHIFT) | |
69 | ||
70 | /* Stream Stage Message - Reply */ | |
71 | #define IPC_STG_REPLY_SHIFT 0 | |
72 | #define IPC_STG_REPLY_MASK (0x1f << IPC_STG_REPLY_SHIFT) | |
73 | ||
74 | /* Debug Log Message - Generic */ | |
75 | #define IPC_LOG_OP_SHIFT 20 | |
76 | #define IPC_LOG_OP_MASK (0xf << IPC_LOG_OP_SHIFT) | |
77 | #define IPC_LOG_OP_TYPE(x) (x << IPC_LOG_OP_SHIFT) | |
78 | #define IPC_LOG_ID_SHIFT 16 | |
79 | #define IPC_LOG_ID_MASK (0xf << IPC_LOG_ID_SHIFT) | |
80 | #define IPC_LOG_ID(x) (x << IPC_LOG_ID_SHIFT) | |
81 | ||
e8e79ede LH |
82 | /* Module Message */ |
83 | #define IPC_MODULE_OPERATION_SHIFT 20 | |
84 | #define IPC_MODULE_OPERATION_MASK (0xf << IPC_MODULE_OPERATION_SHIFT) | |
85 | #define IPC_MODULE_OPERATION(x) (x << IPC_MODULE_OPERATION_SHIFT) | |
86 | ||
87 | #define IPC_MODULE_ID_SHIFT 16 | |
88 | #define IPC_MODULE_ID_MASK (0xf << IPC_MODULE_ID_SHIFT) | |
89 | #define IPC_MODULE_ID(x) (x << IPC_MODULE_ID_SHIFT) | |
90 | ||
a4b12990 MB |
91 | /* IPC message timeout (msecs) */ |
92 | #define IPC_TIMEOUT_MSECS 300 | |
93 | #define IPC_BOOT_MSECS 200 | |
94 | #define IPC_MSG_WAIT 0 | |
95 | #define IPC_MSG_NOWAIT 1 | |
96 | ||
97 | /* Firmware Ready Message */ | |
98 | #define IPC_FW_READY (0x1 << 29) | |
99 | #define IPC_STATUS_MASK (0x3 << 30) | |
100 | ||
101 | #define IPC_EMPTY_LIST_SIZE 8 | |
102 | #define IPC_MAX_STREAMS 4 | |
103 | ||
104 | /* Mailbox */ | |
105 | #define IPC_MAX_MAILBOX_BYTES 256 | |
106 | ||
a0a7c48f JY |
107 | #define INVALID_STREAM_HW_ID 0xffffffff |
108 | ||
a4b12990 MB |
109 | /* Global Message - Types and Replies */ |
110 | enum ipc_glb_type { | |
111 | IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */ | |
112 | IPC_GLB_PERFORMANCE_MONITOR = 1, /* Performance monitoring actions */ | |
113 | IPC_GLB_ALLOCATE_STREAM = 3, /* Request to allocate new stream */ | |
114 | IPC_GLB_FREE_STREAM = 4, /* Request to free stream */ | |
115 | IPC_GLB_GET_FW_CAPABILITIES = 5, /* Retrieves firmware capabilities */ | |
116 | IPC_GLB_STREAM_MESSAGE = 6, /* Message directed to stream or its stages */ | |
117 | /* Request to store firmware context during D0->D3 transition */ | |
118 | IPC_GLB_REQUEST_DUMP = 7, | |
119 | /* Request to restore firmware context during D3->D0 transition */ | |
120 | IPC_GLB_RESTORE_CONTEXT = 8, | |
121 | IPC_GLB_GET_DEVICE_FORMATS = 9, /* Set device format */ | |
122 | IPC_GLB_SET_DEVICE_FORMATS = 10, /* Get device format */ | |
123 | IPC_GLB_SHORT_REPLY = 11, | |
124 | IPC_GLB_ENTER_DX_STATE = 12, | |
125 | IPC_GLB_GET_MIXER_STREAM_INFO = 13, /* Request mixer stream params */ | |
126 | IPC_GLB_DEBUG_LOG_MESSAGE = 14, /* Message to or from the debug logger. */ | |
e8e79ede | 127 | IPC_GLB_MODULE_OPERATION = 15, /* Message to loadable fw module */ |
a4b12990 MB |
128 | IPC_GLB_REQUEST_TRANSFER = 16, /* < Request Transfer for host */ |
129 | IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17, /* Maximum message number */ | |
130 | }; | |
131 | ||
132 | enum ipc_glb_reply { | |
133 | IPC_GLB_REPLY_SUCCESS = 0, /* The operation was successful. */ | |
134 | IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1, /* Invalid parameter was passed. */ | |
135 | IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */ | |
136 | IPC_GLB_REPLY_OUT_OF_RESOURCES = 3, /* No resources to satisfy the request. */ | |
137 | IPC_GLB_REPLY_BUSY = 4, /* The system or resource is busy. */ | |
138 | IPC_GLB_REPLY_PENDING = 5, /* The action was scheduled for processing. */ | |
139 | IPC_GLB_REPLY_FAILURE = 6, /* Critical error happened. */ | |
140 | IPC_GLB_REPLY_INVALID_REQUEST = 7, /* Request can not be completed. */ | |
141 | IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8, /* Processing stage was uninitialized. */ | |
142 | IPC_GLB_REPLY_NOT_FOUND = 9, /* Required resource can not be found. */ | |
143 | IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10, /* Source was not started. */ | |
144 | }; | |
145 | ||
e8e79ede LH |
146 | enum ipc_module_operation { |
147 | IPC_MODULE_NOTIFICATION = 0, | |
148 | IPC_MODULE_ENABLE = 1, | |
149 | IPC_MODULE_DISABLE = 2, | |
150 | IPC_MODULE_GET_PARAMETER = 3, | |
151 | IPC_MODULE_SET_PARAMETER = 4, | |
152 | IPC_MODULE_GET_INFO = 5, | |
153 | IPC_MODULE_MAX_MESSAGE | |
154 | }; | |
155 | ||
a4b12990 MB |
156 | /* Stream Message - Types */ |
157 | enum ipc_str_operation { | |
158 | IPC_STR_RESET = 0, | |
159 | IPC_STR_PAUSE = 1, | |
160 | IPC_STR_RESUME = 2, | |
161 | IPC_STR_STAGE_MESSAGE = 3, | |
162 | IPC_STR_NOTIFICATION = 4, | |
163 | IPC_STR_MAX_MESSAGE | |
164 | }; | |
165 | ||
166 | /* Stream Stage Message Types */ | |
167 | enum ipc_stg_operation { | |
168 | IPC_STG_GET_VOLUME = 0, | |
169 | IPC_STG_SET_VOLUME, | |
170 | IPC_STG_SET_WRITE_POSITION, | |
171 | IPC_STG_SET_FX_ENABLE, | |
172 | IPC_STG_SET_FX_DISABLE, | |
173 | IPC_STG_SET_FX_GET_PARAM, | |
174 | IPC_STG_SET_FX_SET_PARAM, | |
175 | IPC_STG_SET_FX_GET_INFO, | |
176 | IPC_STG_MUTE_LOOPBACK, | |
177 | IPC_STG_MAX_MESSAGE | |
178 | }; | |
179 | ||
180 | /* Stream Stage Message Types For Notification*/ | |
181 | enum ipc_stg_operation_notify { | |
182 | IPC_POSITION_CHANGED = 0, | |
183 | IPC_STG_GLITCH, | |
184 | IPC_STG_MAX_NOTIFY | |
185 | }; | |
186 | ||
187 | enum ipc_glitch_type { | |
188 | IPC_GLITCH_UNDERRUN = 1, | |
189 | IPC_GLITCH_DECODER_ERROR, | |
190 | IPC_GLITCH_DOUBLED_WRITE_POS, | |
191 | IPC_GLITCH_MAX | |
192 | }; | |
193 | ||
194 | /* Debug Control */ | |
195 | enum ipc_debug_operation { | |
196 | IPC_DEBUG_ENABLE_LOG = 0, | |
197 | IPC_DEBUG_DISABLE_LOG = 1, | |
198 | IPC_DEBUG_REQUEST_LOG_DUMP = 2, | |
199 | IPC_DEBUG_NOTIFY_LOG_DUMP = 3, | |
200 | IPC_DEBUG_MAX_DEBUG_LOG | |
201 | }; | |
202 | ||
203 | /* Firmware Ready */ | |
204 | struct sst_hsw_ipc_fw_ready { | |
205 | u32 inbox_offset; | |
206 | u32 outbox_offset; | |
207 | u32 inbox_size; | |
208 | u32 outbox_size; | |
209 | u32 fw_info_size; | |
249adddb | 210 | u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)]; |
a4b12990 MB |
211 | } __attribute__((packed)); |
212 | ||
213 | struct ipc_message { | |
214 | struct list_head list; | |
215 | u32 header; | |
216 | ||
217 | /* direction wrt host CPU */ | |
218 | char tx_data[IPC_MAX_MAILBOX_BYTES]; | |
219 | size_t tx_size; | |
220 | char rx_data[IPC_MAX_MAILBOX_BYTES]; | |
221 | size_t rx_size; | |
222 | ||
223 | wait_queue_head_t waitq; | |
224 | bool pending; | |
225 | bool complete; | |
226 | bool wait; | |
227 | int errno; | |
228 | }; | |
229 | ||
230 | struct sst_hsw_stream; | |
231 | struct sst_hsw; | |
232 | ||
233 | /* Stream infomation */ | |
234 | struct sst_hsw_stream { | |
235 | /* configuration */ | |
236 | struct sst_hsw_ipc_stream_alloc_req request; | |
237 | struct sst_hsw_ipc_stream_alloc_reply reply; | |
238 | struct sst_hsw_ipc_stream_free_req free_req; | |
239 | ||
240 | /* Mixer info */ | |
241 | u32 mute_volume[SST_HSW_NO_CHANNELS]; | |
242 | u32 mute[SST_HSW_NO_CHANNELS]; | |
243 | ||
244 | /* runtime info */ | |
245 | struct sst_hsw *hsw; | |
246 | int host_id; | |
247 | bool commited; | |
248 | bool running; | |
249 | ||
250 | /* Notification work */ | |
251 | struct work_struct notify_work; | |
252 | u32 header; | |
253 | ||
254 | /* Position info from DSP */ | |
255 | struct sst_hsw_ipc_stream_set_position wpos; | |
256 | struct sst_hsw_ipc_stream_get_position rpos; | |
257 | struct sst_hsw_ipc_stream_glitch_position glitch; | |
258 | ||
259 | /* Volume info */ | |
260 | struct sst_hsw_ipc_volume_req vol_req; | |
261 | ||
262 | /* driver callback */ | |
263 | u32 (*notify_position)(struct sst_hsw_stream *stream, void *data); | |
264 | void *pdata; | |
265 | ||
1b006996 LY |
266 | /* record the fw read position when playback */ |
267 | snd_pcm_uframes_t old_position; | |
268 | bool play_silence; | |
a4b12990 MB |
269 | struct list_head node; |
270 | }; | |
271 | ||
272 | /* FW log ring information */ | |
273 | struct sst_hsw_log_stream { | |
274 | dma_addr_t dma_addr; | |
275 | unsigned char *dma_area; | |
276 | unsigned char *ring_descr; | |
277 | int pages; | |
278 | int size; | |
279 | ||
280 | /* Notification work */ | |
281 | struct work_struct notify_work; | |
282 | wait_queue_head_t readers_wait_q; | |
283 | struct mutex rw_mutex; | |
284 | ||
285 | u32 last_pos; | |
286 | u32 curr_pos; | |
287 | u32 reader_pos; | |
288 | ||
289 | /* fw log config */ | |
290 | u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS]; | |
291 | ||
292 | struct sst_hsw *hsw; | |
293 | }; | |
294 | ||
295 | /* SST Haswell IPC data */ | |
296 | struct sst_hsw { | |
297 | struct device *dev; | |
298 | struct sst_dsp *dsp; | |
299 | struct platform_device *pdev_pcm; | |
300 | ||
301 | /* FW config */ | |
302 | struct sst_hsw_ipc_fw_ready fw_ready; | |
303 | struct sst_hsw_ipc_fw_version version; | |
a4b12990 | 304 | bool fw_done; |
aed3c7b7 | 305 | struct sst_fw *sst_fw; |
a4b12990 MB |
306 | |
307 | /* stream */ | |
308 | struct list_head stream_list; | |
309 | ||
310 | /* global mixer */ | |
311 | struct sst_hsw_ipc_stream_info_reply mixer_info; | |
312 | enum sst_hsw_volume_curve curve_type; | |
313 | u32 curve_duration; | |
314 | u32 mute[SST_HSW_NO_CHANNELS]; | |
315 | u32 mute_volume[SST_HSW_NO_CHANNELS]; | |
316 | ||
317 | /* DX */ | |
318 | struct sst_hsw_ipc_dx_reply dx; | |
aed3c7b7 LG |
319 | void *dx_context; |
320 | dma_addr_t dx_context_paddr; | |
a4b12990 MB |
321 | |
322 | /* boot */ | |
323 | wait_queue_head_t boot_wait; | |
324 | bool boot_complete; | |
325 | bool shutdown; | |
326 | ||
327 | /* IPC messaging */ | |
328 | struct list_head tx_list; | |
329 | struct list_head rx_list; | |
330 | struct list_head empty_list; | |
331 | wait_queue_head_t wait_txq; | |
332 | struct task_struct *tx_thread; | |
333 | struct kthread_worker kworker; | |
334 | struct kthread_work kwork; | |
335 | bool pending; | |
336 | struct ipc_message *msg; | |
337 | ||
338 | /* FW log stream */ | |
339 | struct sst_hsw_log_stream log_stream; | |
76c07b82 LH |
340 | |
341 | /* flags bit field to track module state when resume from RTD3, | |
342 | * each bit represent state (enabled/disabled) of single module */ | |
343 | u32 enabled_modules_rtd3; | |
a4b12990 MB |
344 | }; |
345 | ||
346 | #define CREATE_TRACE_POINTS | |
347 | #include <trace/events/hswadsp.h> | |
348 | ||
349 | static inline u32 msg_get_global_type(u32 msg) | |
350 | { | |
351 | return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT; | |
352 | } | |
353 | ||
354 | static inline u32 msg_get_global_reply(u32 msg) | |
355 | { | |
356 | return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT; | |
357 | } | |
358 | ||
359 | static inline u32 msg_get_stream_type(u32 msg) | |
360 | { | |
361 | return (msg & IPC_STR_TYPE_MASK) >> IPC_STR_TYPE_SHIFT; | |
362 | } | |
363 | ||
364 | static inline u32 msg_get_stage_type(u32 msg) | |
365 | { | |
366 | return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT; | |
367 | } | |
368 | ||
a4b12990 MB |
369 | static inline u32 msg_get_stream_id(u32 msg) |
370 | { | |
371 | return (msg & IPC_STR_ID_MASK) >> IPC_STR_ID_SHIFT; | |
372 | } | |
373 | ||
374 | static inline u32 msg_get_notify_reason(u32 msg) | |
375 | { | |
376 | return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT; | |
377 | } | |
378 | ||
e8e79ede LH |
379 | static inline u32 msg_get_module_operation(u32 msg) |
380 | { | |
381 | return (msg & IPC_MODULE_OPERATION_MASK) >> IPC_MODULE_OPERATION_SHIFT; | |
382 | } | |
383 | ||
384 | static inline u32 msg_get_module_id(u32 msg) | |
385 | { | |
386 | return (msg & IPC_MODULE_ID_MASK) >> IPC_MODULE_ID_SHIFT; | |
387 | } | |
388 | ||
a4b12990 MB |
389 | u32 create_channel_map(enum sst_hsw_channel_config config) |
390 | { | |
391 | switch (config) { | |
392 | case SST_HSW_CHANNEL_CONFIG_MONO: | |
393 | return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER); | |
394 | case SST_HSW_CHANNEL_CONFIG_STEREO: | |
395 | return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT | |
396 | | (SST_HSW_CHANNEL_RIGHT << 4)); | |
397 | case SST_HSW_CHANNEL_CONFIG_2_POINT_1: | |
398 | return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT | |
399 | | (SST_HSW_CHANNEL_RIGHT << 4) | |
400 | | (SST_HSW_CHANNEL_LFE << 8 )); | |
401 | case SST_HSW_CHANNEL_CONFIG_3_POINT_0: | |
402 | return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT | |
403 | | (SST_HSW_CHANNEL_CENTER << 4) | |
404 | | (SST_HSW_CHANNEL_RIGHT << 8)); | |
405 | case SST_HSW_CHANNEL_CONFIG_3_POINT_1: | |
406 | return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT | |
407 | | (SST_HSW_CHANNEL_CENTER << 4) | |
408 | | (SST_HSW_CHANNEL_RIGHT << 8) | |
409 | | (SST_HSW_CHANNEL_LFE << 12)); | |
410 | case SST_HSW_CHANNEL_CONFIG_QUATRO: | |
411 | return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT | |
412 | | (SST_HSW_CHANNEL_RIGHT << 4) | |
413 | | (SST_HSW_CHANNEL_LEFT_SURROUND << 8) | |
414 | | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12)); | |
415 | case SST_HSW_CHANNEL_CONFIG_4_POINT_0: | |
416 | return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT | |
417 | | (SST_HSW_CHANNEL_CENTER << 4) | |
418 | | (SST_HSW_CHANNEL_RIGHT << 8) | |
419 | | (SST_HSW_CHANNEL_CENTER_SURROUND << 12)); | |
420 | case SST_HSW_CHANNEL_CONFIG_5_POINT_0: | |
421 | return (0xFFF00000 | SST_HSW_CHANNEL_LEFT | |
422 | | (SST_HSW_CHANNEL_CENTER << 4) | |
423 | | (SST_HSW_CHANNEL_RIGHT << 8) | |
424 | | (SST_HSW_CHANNEL_LEFT_SURROUND << 12) | |
425 | | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)); | |
426 | case SST_HSW_CHANNEL_CONFIG_5_POINT_1: | |
427 | return (0xFF000000 | SST_HSW_CHANNEL_CENTER | |
428 | | (SST_HSW_CHANNEL_LEFT << 4) | |
429 | | (SST_HSW_CHANNEL_RIGHT << 8) | |
430 | | (SST_HSW_CHANNEL_LEFT_SURROUND << 12) | |
431 | | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16) | |
432 | | (SST_HSW_CHANNEL_LFE << 20)); | |
433 | case SST_HSW_CHANNEL_CONFIG_DUAL_MONO: | |
434 | return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT | |
435 | | (SST_HSW_CHANNEL_LEFT << 4)); | |
436 | default: | |
437 | return 0xFFFFFFFF; | |
438 | } | |
439 | } | |
440 | ||
441 | static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw, | |
442 | int stream_id) | |
443 | { | |
444 | struct sst_hsw_stream *stream; | |
445 | ||
446 | list_for_each_entry(stream, &hsw->stream_list, node) { | |
447 | if (stream->reply.stream_hw_id == stream_id) | |
448 | return stream; | |
449 | } | |
450 | ||
451 | return NULL; | |
452 | } | |
453 | ||
454 | static void ipc_shim_dbg(struct sst_hsw *hsw, const char *text) | |
455 | { | |
456 | struct sst_dsp *sst = hsw->dsp; | |
457 | u32 isr, ipcd, imrx, ipcx; | |
458 | ||
459 | ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX); | |
460 | isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX); | |
461 | ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD); | |
462 | imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX); | |
463 | ||
464 | dev_err(hsw->dev, "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n", | |
465 | text, ipcx, isr, ipcd, imrx); | |
466 | } | |
467 | ||
468 | /* locks held by caller */ | |
469 | static struct ipc_message *msg_get_empty(struct sst_hsw *hsw) | |
470 | { | |
471 | struct ipc_message *msg = NULL; | |
472 | ||
473 | if (!list_empty(&hsw->empty_list)) { | |
474 | msg = list_first_entry(&hsw->empty_list, struct ipc_message, | |
475 | list); | |
476 | list_del(&msg->list); | |
477 | } | |
478 | ||
479 | return msg; | |
480 | } | |
481 | ||
482 | static void ipc_tx_msgs(struct kthread_work *work) | |
483 | { | |
484 | struct sst_hsw *hsw = | |
485 | container_of(work, struct sst_hsw, kwork); | |
486 | struct ipc_message *msg; | |
487 | unsigned long flags; | |
488 | u32 ipcx; | |
489 | ||
490 | spin_lock_irqsave(&hsw->dsp->spinlock, flags); | |
491 | ||
492 | if (list_empty(&hsw->tx_list) || hsw->pending) { | |
493 | spin_unlock_irqrestore(&hsw->dsp->spinlock, flags); | |
494 | return; | |
495 | } | |
496 | ||
94ce3345 PP |
497 | /* if the DSP is busy, we will TX messages after IRQ. |
498 | * also postpone if we are in the middle of procesing completion irq*/ | |
a4b12990 | 499 | ipcx = sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX); |
94ce3345 | 500 | if (ipcx & (SST_IPCX_BUSY | SST_IPCX_DONE)) { |
a4b12990 MB |
501 | spin_unlock_irqrestore(&hsw->dsp->spinlock, flags); |
502 | return; | |
503 | } | |
504 | ||
505 | msg = list_first_entry(&hsw->tx_list, struct ipc_message, list); | |
506 | ||
507 | list_move(&msg->list, &hsw->rx_list); | |
508 | ||
509 | /* send the message */ | |
510 | sst_dsp_outbox_write(hsw->dsp, msg->tx_data, msg->tx_size); | |
511 | sst_dsp_ipc_msg_tx(hsw->dsp, msg->header | SST_IPCX_BUSY); | |
512 | ||
513 | spin_unlock_irqrestore(&hsw->dsp->spinlock, flags); | |
514 | } | |
515 | ||
516 | /* locks held by caller */ | |
517 | static void tx_msg_reply_complete(struct sst_hsw *hsw, struct ipc_message *msg) | |
518 | { | |
519 | msg->complete = true; | |
520 | trace_ipc_reply("completed", msg->header); | |
521 | ||
522 | if (!msg->wait) | |
523 | list_add_tail(&msg->list, &hsw->empty_list); | |
524 | else | |
525 | wake_up(&msg->waitq); | |
526 | } | |
527 | ||
528 | static int tx_wait_done(struct sst_hsw *hsw, struct ipc_message *msg, | |
529 | void *rx_data) | |
530 | { | |
531 | unsigned long flags; | |
532 | int ret; | |
533 | ||
534 | /* wait for DSP completion (in all cases atm inc pending) */ | |
535 | ret = wait_event_timeout(msg->waitq, msg->complete, | |
536 | msecs_to_jiffies(IPC_TIMEOUT_MSECS)); | |
537 | ||
538 | spin_lock_irqsave(&hsw->dsp->spinlock, flags); | |
539 | if (ret == 0) { | |
540 | ipc_shim_dbg(hsw, "message timeout"); | |
541 | ||
542 | trace_ipc_error("error message timeout for", msg->header); | |
97cfc751 | 543 | list_del(&msg->list); |
a4b12990 MB |
544 | ret = -ETIMEDOUT; |
545 | } else { | |
546 | ||
547 | /* copy the data returned from DSP */ | |
548 | if (msg->rx_size) | |
549 | memcpy(rx_data, msg->rx_data, msg->rx_size); | |
550 | ret = msg->errno; | |
551 | } | |
552 | ||
553 | list_add_tail(&msg->list, &hsw->empty_list); | |
554 | spin_unlock_irqrestore(&hsw->dsp->spinlock, flags); | |
555 | return ret; | |
556 | } | |
557 | ||
558 | static int ipc_tx_message(struct sst_hsw *hsw, u32 header, void *tx_data, | |
559 | size_t tx_bytes, void *rx_data, size_t rx_bytes, int wait) | |
560 | { | |
561 | struct ipc_message *msg; | |
562 | unsigned long flags; | |
563 | ||
564 | spin_lock_irqsave(&hsw->dsp->spinlock, flags); | |
565 | ||
566 | msg = msg_get_empty(hsw); | |
567 | if (msg == NULL) { | |
568 | spin_unlock_irqrestore(&hsw->dsp->spinlock, flags); | |
569 | return -EBUSY; | |
570 | } | |
571 | ||
572 | if (tx_bytes) | |
573 | memcpy(msg->tx_data, tx_data, tx_bytes); | |
574 | ||
575 | msg->header = header; | |
576 | msg->tx_size = tx_bytes; | |
577 | msg->rx_size = rx_bytes; | |
578 | msg->wait = wait; | |
579 | msg->errno = 0; | |
580 | msg->pending = false; | |
581 | msg->complete = false; | |
582 | ||
583 | list_add_tail(&msg->list, &hsw->tx_list); | |
584 | spin_unlock_irqrestore(&hsw->dsp->spinlock, flags); | |
585 | ||
586 | queue_kthread_work(&hsw->kworker, &hsw->kwork); | |
587 | ||
588 | if (wait) | |
589 | return tx_wait_done(hsw, msg, rx_data); | |
590 | else | |
591 | return 0; | |
592 | } | |
593 | ||
594 | static inline int ipc_tx_message_wait(struct sst_hsw *hsw, u32 header, | |
595 | void *tx_data, size_t tx_bytes, void *rx_data, size_t rx_bytes) | |
596 | { | |
597 | return ipc_tx_message(hsw, header, tx_data, tx_bytes, rx_data, | |
598 | rx_bytes, 1); | |
599 | } | |
600 | ||
601 | static inline int ipc_tx_message_nowait(struct sst_hsw *hsw, u32 header, | |
602 | void *tx_data, size_t tx_bytes) | |
603 | { | |
604 | return ipc_tx_message(hsw, header, tx_data, tx_bytes, NULL, 0, 0); | |
605 | } | |
606 | ||
607 | static void hsw_fw_ready(struct sst_hsw *hsw, u32 header) | |
608 | { | |
609 | struct sst_hsw_ipc_fw_ready fw_ready; | |
610 | u32 offset; | |
249adddb JY |
611 | u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)]; |
612 | char *tmp[5], *pinfo; | |
613 | int i = 0; | |
a4b12990 MB |
614 | |
615 | offset = (header & 0x1FFFFFFF) << 3; | |
616 | ||
617 | dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n", | |
618 | header, offset); | |
619 | ||
620 | /* copy data from the DSP FW ready offset */ | |
621 | sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready)); | |
622 | ||
623 | sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset, | |
624 | fw_ready.inbox_size, fw_ready.outbox_offset, | |
625 | fw_ready.outbox_size); | |
626 | ||
627 | hsw->boot_complete = true; | |
628 | wake_up(&hsw->boot_wait); | |
629 | ||
630 | dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n", | |
631 | fw_ready.inbox_offset, fw_ready.inbox_size); | |
632 | dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n", | |
633 | fw_ready.outbox_offset, fw_ready.outbox_size); | |
249adddb JY |
634 | if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) { |
635 | fw_ready.fw_info[fw_ready.fw_info_size] = 0; | |
636 | dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info); | |
637 | ||
638 | /* log the FW version info got from the mailbox here. */ | |
639 | memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size); | |
640 | pinfo = &fw_info[0]; | |
641 | for (i = 0; i < sizeof(tmp) / sizeof(char *); i++) | |
642 | tmp[i] = strsep(&pinfo, " "); | |
643 | dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - " | |
644 | "version: %s.%s, build %s, source commit id: %s\n", | |
645 | tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]); | |
646 | } | |
a4b12990 MB |
647 | } |
648 | ||
649 | static void hsw_notification_work(struct work_struct *work) | |
650 | { | |
651 | struct sst_hsw_stream *stream = container_of(work, | |
652 | struct sst_hsw_stream, notify_work); | |
653 | struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch; | |
654 | struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos; | |
655 | struct sst_hsw *hsw = stream->hsw; | |
656 | u32 reason; | |
657 | ||
658 | reason = msg_get_notify_reason(stream->header); | |
659 | ||
660 | switch (reason) { | |
661 | case IPC_STG_GLITCH: | |
662 | trace_ipc_notification("DSP stream under/overrun", | |
663 | stream->reply.stream_hw_id); | |
664 | sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch)); | |
665 | ||
666 | dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n", | |
667 | glitch->glitch_type, glitch->present_pos, | |
668 | glitch->write_pos); | |
669 | break; | |
670 | ||
671 | case IPC_POSITION_CHANGED: | |
672 | trace_ipc_notification("DSP stream position changed for", | |
673 | stream->reply.stream_hw_id); | |
7897ab78 | 674 | sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos)); |
a4b12990 MB |
675 | |
676 | if (stream->notify_position) | |
677 | stream->notify_position(stream, stream->pdata); | |
678 | ||
679 | break; | |
680 | default: | |
681 | dev_err(hsw->dev, "error: unknown notification 0x%x\n", | |
682 | stream->header); | |
683 | break; | |
684 | } | |
685 | ||
686 | /* tell DSP that notification has been handled */ | |
09a34aa5 | 687 | sst_dsp_shim_update_bits(hsw->dsp, SST_IPCD, |
a4b12990 MB |
688 | SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE); |
689 | ||
690 | /* unmask busy interrupt */ | |
09a34aa5 | 691 | sst_dsp_shim_update_bits(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0); |
a4b12990 MB |
692 | } |
693 | ||
694 | static struct ipc_message *reply_find_msg(struct sst_hsw *hsw, u32 header) | |
695 | { | |
696 | struct ipc_message *msg; | |
697 | ||
698 | /* clear reply bits & status bits */ | |
699 | header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK); | |
700 | ||
701 | if (list_empty(&hsw->rx_list)) { | |
702 | dev_err(hsw->dev, "error: rx list empty but received 0x%x\n", | |
703 | header); | |
704 | return NULL; | |
705 | } | |
706 | ||
707 | list_for_each_entry(msg, &hsw->rx_list, list) { | |
708 | if (msg->header == header) | |
709 | return msg; | |
710 | } | |
711 | ||
712 | return NULL; | |
713 | } | |
714 | ||
715 | static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg) | |
716 | { | |
717 | struct sst_hsw_stream *stream; | |
718 | u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK); | |
719 | u32 stream_id = msg_get_stream_id(header); | |
720 | u32 stream_msg = msg_get_stream_type(header); | |
721 | ||
722 | stream = get_stream_by_id(hsw, stream_id); | |
723 | if (stream == NULL) | |
724 | return; | |
725 | ||
726 | switch (stream_msg) { | |
727 | case IPC_STR_STAGE_MESSAGE: | |
728 | case IPC_STR_NOTIFICATION: | |
81552612 | 729 | break; |
a4b12990 | 730 | case IPC_STR_RESET: |
81552612 | 731 | trace_ipc_notification("stream reset", stream->reply.stream_hw_id); |
a4b12990 MB |
732 | break; |
733 | case IPC_STR_PAUSE: | |
734 | stream->running = false; | |
735 | trace_ipc_notification("stream paused", | |
736 | stream->reply.stream_hw_id); | |
737 | break; | |
738 | case IPC_STR_RESUME: | |
739 | stream->running = true; | |
740 | trace_ipc_notification("stream running", | |
741 | stream->reply.stream_hw_id); | |
742 | break; | |
743 | } | |
744 | } | |
745 | ||
746 | static int hsw_process_reply(struct sst_hsw *hsw, u32 header) | |
747 | { | |
748 | struct ipc_message *msg; | |
749 | u32 reply = msg_get_global_reply(header); | |
750 | ||
751 | trace_ipc_reply("processing -->", header); | |
752 | ||
753 | msg = reply_find_msg(hsw, header); | |
754 | if (msg == NULL) { | |
755 | trace_ipc_error("error: can't find message header", header); | |
756 | return -EIO; | |
757 | } | |
758 | ||
759 | /* first process the header */ | |
760 | switch (reply) { | |
761 | case IPC_GLB_REPLY_PENDING: | |
762 | trace_ipc_pending_reply("received", header); | |
763 | msg->pending = true; | |
764 | hsw->pending = true; | |
765 | return 1; | |
766 | case IPC_GLB_REPLY_SUCCESS: | |
767 | if (msg->pending) { | |
768 | trace_ipc_pending_reply("completed", header); | |
769 | sst_dsp_inbox_read(hsw->dsp, msg->rx_data, | |
770 | msg->rx_size); | |
771 | hsw->pending = false; | |
772 | } else { | |
773 | /* copy data from the DSP */ | |
774 | sst_dsp_outbox_read(hsw->dsp, msg->rx_data, | |
775 | msg->rx_size); | |
776 | } | |
777 | break; | |
778 | /* these will be rare - but useful for debug */ | |
779 | case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE: | |
780 | trace_ipc_error("error: unknown message type", header); | |
781 | msg->errno = -EBADMSG; | |
782 | break; | |
783 | case IPC_GLB_REPLY_OUT_OF_RESOURCES: | |
784 | trace_ipc_error("error: out of resources", header); | |
785 | msg->errno = -ENOMEM; | |
786 | break; | |
787 | case IPC_GLB_REPLY_BUSY: | |
788 | trace_ipc_error("error: reply busy", header); | |
789 | msg->errno = -EBUSY; | |
790 | break; | |
791 | case IPC_GLB_REPLY_FAILURE: | |
792 | trace_ipc_error("error: reply failure", header); | |
793 | msg->errno = -EINVAL; | |
794 | break; | |
795 | case IPC_GLB_REPLY_STAGE_UNINITIALIZED: | |
796 | trace_ipc_error("error: stage uninitialized", header); | |
797 | msg->errno = -EINVAL; | |
798 | break; | |
799 | case IPC_GLB_REPLY_NOT_FOUND: | |
800 | trace_ipc_error("error: reply not found", header); | |
801 | msg->errno = -EINVAL; | |
802 | break; | |
803 | case IPC_GLB_REPLY_SOURCE_NOT_STARTED: | |
804 | trace_ipc_error("error: source not started", header); | |
805 | msg->errno = -EINVAL; | |
806 | break; | |
807 | case IPC_GLB_REPLY_INVALID_REQUEST: | |
808 | trace_ipc_error("error: invalid request", header); | |
809 | msg->errno = -EINVAL; | |
810 | break; | |
811 | case IPC_GLB_REPLY_ERROR_INVALID_PARAM: | |
812 | trace_ipc_error("error: invalid parameter", header); | |
813 | msg->errno = -EINVAL; | |
814 | break; | |
815 | default: | |
816 | trace_ipc_error("error: unknown reply", header); | |
817 | msg->errno = -EINVAL; | |
818 | break; | |
819 | } | |
820 | ||
821 | /* update any stream states */ | |
d6e08617 PP |
822 | if (msg_get_global_type(header) == IPC_GLB_STREAM_MESSAGE) |
823 | hsw_stream_update(hsw, msg); | |
a4b12990 MB |
824 | |
825 | /* wake up and return the error if we have waiters on this message ? */ | |
826 | list_del(&msg->list); | |
827 | tx_msg_reply_complete(hsw, msg); | |
828 | ||
829 | return 1; | |
830 | } | |
831 | ||
e8e79ede LH |
832 | static int hsw_module_message(struct sst_hsw *hsw, u32 header) |
833 | { | |
834 | u32 operation, module_id; | |
835 | int handled = 0; | |
836 | ||
837 | operation = msg_get_module_operation(header); | |
838 | module_id = msg_get_module_id(header); | |
839 | dev_dbg(hsw->dev, "received module message header: 0x%8.8x\n", | |
840 | header); | |
841 | dev_dbg(hsw->dev, "operation: 0x%8.8x module_id: 0x%8.8x\n", | |
842 | operation, module_id); | |
843 | ||
844 | switch (operation) { | |
845 | case IPC_MODULE_NOTIFICATION: | |
846 | dev_dbg(hsw->dev, "module notification received"); | |
847 | handled = 1; | |
848 | break; | |
849 | default: | |
850 | handled = hsw_process_reply(hsw, header); | |
851 | break; | |
852 | } | |
853 | ||
854 | return handled; | |
855 | } | |
856 | ||
a4b12990 MB |
857 | static int hsw_stream_message(struct sst_hsw *hsw, u32 header) |
858 | { | |
859 | u32 stream_msg, stream_id, stage_type; | |
860 | struct sst_hsw_stream *stream; | |
861 | int handled = 0; | |
862 | ||
863 | stream_msg = msg_get_stream_type(header); | |
864 | stream_id = msg_get_stream_id(header); | |
865 | stage_type = msg_get_stage_type(header); | |
866 | ||
867 | stream = get_stream_by_id(hsw, stream_id); | |
868 | if (stream == NULL) | |
869 | return handled; | |
870 | ||
871 | stream->header = header; | |
872 | ||
873 | switch (stream_msg) { | |
874 | case IPC_STR_STAGE_MESSAGE: | |
875 | dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n", | |
876 | header); | |
877 | break; | |
878 | case IPC_STR_NOTIFICATION: | |
879 | schedule_work(&stream->notify_work); | |
880 | break; | |
881 | default: | |
882 | /* handle pending message complete request */ | |
883 | handled = hsw_process_reply(hsw, header); | |
884 | break; | |
885 | } | |
886 | ||
887 | return handled; | |
888 | } | |
889 | ||
890 | static int hsw_log_message(struct sst_hsw *hsw, u32 header) | |
891 | { | |
892 | u32 operation = (header & IPC_LOG_OP_MASK) >> IPC_LOG_OP_SHIFT; | |
893 | struct sst_hsw_log_stream *stream = &hsw->log_stream; | |
894 | int ret = 1; | |
895 | ||
896 | if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) { | |
897 | dev_err(hsw->dev, | |
898 | "error: log msg not implemented 0x%8.8x\n", header); | |
899 | return 0; | |
900 | } | |
901 | ||
902 | mutex_lock(&stream->rw_mutex); | |
903 | stream->last_pos = stream->curr_pos; | |
904 | sst_dsp_inbox_read( | |
905 | hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos)); | |
906 | mutex_unlock(&stream->rw_mutex); | |
907 | ||
908 | schedule_work(&stream->notify_work); | |
909 | ||
910 | return ret; | |
911 | } | |
912 | ||
913 | static int hsw_process_notification(struct sst_hsw *hsw) | |
914 | { | |
915 | struct sst_dsp *sst = hsw->dsp; | |
916 | u32 type, header; | |
917 | int handled = 1; | |
918 | ||
919 | header = sst_dsp_shim_read_unlocked(sst, SST_IPCD); | |
920 | type = msg_get_global_type(header); | |
921 | ||
922 | trace_ipc_request("processing -->", header); | |
923 | ||
924 | /* FW Ready is a special case */ | |
925 | if (!hsw->boot_complete && header & IPC_FW_READY) { | |
926 | hsw_fw_ready(hsw, header); | |
927 | return handled; | |
928 | } | |
929 | ||
930 | switch (type) { | |
931 | case IPC_GLB_GET_FW_VERSION: | |
932 | case IPC_GLB_ALLOCATE_STREAM: | |
933 | case IPC_GLB_FREE_STREAM: | |
934 | case IPC_GLB_GET_FW_CAPABILITIES: | |
935 | case IPC_GLB_REQUEST_DUMP: | |
936 | case IPC_GLB_GET_DEVICE_FORMATS: | |
937 | case IPC_GLB_SET_DEVICE_FORMATS: | |
938 | case IPC_GLB_ENTER_DX_STATE: | |
939 | case IPC_GLB_GET_MIXER_STREAM_INFO: | |
940 | case IPC_GLB_MAX_IPC_MESSAGE_TYPE: | |
941 | case IPC_GLB_RESTORE_CONTEXT: | |
942 | case IPC_GLB_SHORT_REPLY: | |
943 | dev_err(hsw->dev, "error: message type %d header 0x%x\n", | |
944 | type, header); | |
945 | break; | |
946 | case IPC_GLB_STREAM_MESSAGE: | |
947 | handled = hsw_stream_message(hsw, header); | |
948 | break; | |
949 | case IPC_GLB_DEBUG_LOG_MESSAGE: | |
950 | handled = hsw_log_message(hsw, header); | |
951 | break; | |
e8e79ede LH |
952 | case IPC_GLB_MODULE_OPERATION: |
953 | handled = hsw_module_message(hsw, header); | |
954 | break; | |
a4b12990 MB |
955 | default: |
956 | dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n", | |
957 | type, header); | |
958 | break; | |
959 | } | |
960 | ||
961 | return handled; | |
962 | } | |
963 | ||
964 | static irqreturn_t hsw_irq_thread(int irq, void *context) | |
965 | { | |
966 | struct sst_dsp *sst = (struct sst_dsp *) context; | |
967 | struct sst_hsw *hsw = sst_dsp_get_thread_context(sst); | |
968 | u32 ipcx, ipcd; | |
969 | int handled; | |
970 | unsigned long flags; | |
971 | ||
972 | spin_lock_irqsave(&sst->spinlock, flags); | |
973 | ||
974 | ipcx = sst_dsp_ipc_msg_rx(hsw->dsp); | |
975 | ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD); | |
976 | ||
977 | /* reply message from DSP */ | |
978 | if (ipcx & SST_IPCX_DONE) { | |
979 | ||
980 | /* Handle Immediate reply from DSP Core */ | |
981 | handled = hsw_process_reply(hsw, ipcx); | |
982 | ||
983 | if (handled > 0) { | |
984 | /* clear DONE bit - tell DSP we have completed */ | |
985 | sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX, | |
986 | SST_IPCX_DONE, 0); | |
987 | ||
988 | /* unmask Done interrupt */ | |
989 | sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX, | |
990 | SST_IMRX_DONE, 0); | |
991 | } | |
992 | } | |
993 | ||
994 | /* new message from DSP */ | |
995 | if (ipcd & SST_IPCD_BUSY) { | |
996 | ||
997 | /* Handle Notification and Delayed reply from DSP Core */ | |
998 | handled = hsw_process_notification(hsw); | |
999 | ||
1000 | /* clear BUSY bit and set DONE bit - accept new messages */ | |
1001 | if (handled > 0) { | |
1002 | sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD, | |
1003 | SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE); | |
1004 | ||
1005 | /* unmask busy interrupt */ | |
1006 | sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX, | |
1007 | SST_IMRX_BUSY, 0); | |
1008 | } | |
1009 | } | |
1010 | ||
1011 | spin_unlock_irqrestore(&sst->spinlock, flags); | |
1012 | ||
1013 | /* continue to send any remaining messages... */ | |
1014 | queue_kthread_work(&hsw->kworker, &hsw->kwork); | |
1015 | ||
1016 | return IRQ_HANDLED; | |
1017 | } | |
1018 | ||
1019 | int sst_hsw_fw_get_version(struct sst_hsw *hsw, | |
1020 | struct sst_hsw_ipc_fw_version *version) | |
1021 | { | |
1022 | int ret; | |
1023 | ||
1024 | ret = ipc_tx_message_wait(hsw, IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION), | |
1025 | NULL, 0, version, sizeof(*version)); | |
1026 | if (ret < 0) | |
1027 | dev_err(hsw->dev, "error: get version failed\n"); | |
1028 | ||
1029 | return ret; | |
1030 | } | |
1031 | ||
1032 | /* Mixer Controls */ | |
a4b12990 MB |
1033 | int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream, |
1034 | u32 stage_id, u32 channel, u32 *volume) | |
1035 | { | |
1036 | if (channel > 1) | |
1037 | return -EINVAL; | |
1038 | ||
1039 | sst_dsp_read(hsw->dsp, volume, | |
bf657d24 CE |
1040 | stream->reply.volume_register_address[channel], |
1041 | sizeof(*volume)); | |
a4b12990 MB |
1042 | |
1043 | return 0; | |
1044 | } | |
1045 | ||
a4b12990 MB |
1046 | /* stream volume */ |
1047 | int sst_hsw_stream_set_volume(struct sst_hsw *hsw, | |
1048 | struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume) | |
1049 | { | |
1050 | struct sst_hsw_ipc_volume_req *req; | |
1051 | u32 header; | |
1052 | int ret; | |
1053 | ||
1054 | trace_ipc_request("set stream volume", stream->reply.stream_hw_id); | |
1055 | ||
f1e59825 | 1056 | if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL) |
a4b12990 MB |
1057 | return -EINVAL; |
1058 | ||
a4b12990 MB |
1059 | header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | |
1060 | IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE); | |
1061 | header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT); | |
1062 | header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT); | |
1063 | header |= (stage_id << IPC_STG_ID_SHIFT); | |
1064 | ||
1065 | req = &stream->vol_req; | |
a4b12990 MB |
1066 | req->target_volume = volume; |
1067 | ||
f1e59825 JY |
1068 | /* set both at same time ? */ |
1069 | if (channel == SST_HSW_CHANNELS_ALL) { | |
1070 | if (hsw->mute[0] && hsw->mute[1]) { | |
1071 | hsw->mute_volume[0] = hsw->mute_volume[1] = volume; | |
1072 | return 0; | |
1073 | } else if (hsw->mute[0]) | |
1074 | req->channel = 1; | |
1075 | else if (hsw->mute[1]) | |
1076 | req->channel = 0; | |
1077 | else | |
1078 | req->channel = SST_HSW_CHANNELS_ALL; | |
1079 | } else { | |
1080 | /* set only 1 channel */ | |
1081 | if (hsw->mute[channel]) { | |
1082 | hsw->mute_volume[channel] = volume; | |
1083 | return 0; | |
1084 | } | |
1085 | req->channel = channel; | |
1086 | } | |
1087 | ||
a4b12990 MB |
1088 | ret = ipc_tx_message_wait(hsw, header, req, sizeof(*req), NULL, 0); |
1089 | if (ret < 0) { | |
1090 | dev_err(hsw->dev, "error: set stream volume failed\n"); | |
1091 | return ret; | |
1092 | } | |
1093 | ||
1094 | return 0; | |
1095 | } | |
1096 | ||
a4b12990 MB |
1097 | int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel, |
1098 | u32 *volume) | |
1099 | { | |
1100 | if (channel > 1) | |
1101 | return -EINVAL; | |
1102 | ||
1103 | sst_dsp_read(hsw->dsp, volume, | |
1104 | hsw->mixer_info.volume_register_address[channel], | |
1105 | sizeof(*volume)); | |
1106 | ||
1107 | return 0; | |
1108 | } | |
1109 | ||
a4b12990 MB |
1110 | /* global mixer volume */ |
1111 | int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel, | |
1112 | u32 volume) | |
1113 | { | |
1114 | struct sst_hsw_ipc_volume_req req; | |
1115 | u32 header; | |
1116 | int ret; | |
1117 | ||
1118 | trace_ipc_request("set mixer volume", volume); | |
1119 | ||
f1e59825 JY |
1120 | if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL) |
1121 | return -EINVAL; | |
1122 | ||
a4b12990 | 1123 | /* set both at same time ? */ |
f1e59825 | 1124 | if (channel == SST_HSW_CHANNELS_ALL) { |
a4b12990 MB |
1125 | if (hsw->mute[0] && hsw->mute[1]) { |
1126 | hsw->mute_volume[0] = hsw->mute_volume[1] = volume; | |
1127 | return 0; | |
1128 | } else if (hsw->mute[0]) | |
1129 | req.channel = 1; | |
1130 | else if (hsw->mute[1]) | |
1131 | req.channel = 0; | |
1132 | else | |
f1e59825 | 1133 | req.channel = SST_HSW_CHANNELS_ALL; |
a4b12990 MB |
1134 | } else { |
1135 | /* set only 1 channel */ | |
1136 | if (hsw->mute[channel]) { | |
1137 | hsw->mute_volume[channel] = volume; | |
1138 | return 0; | |
1139 | } | |
1140 | req.channel = channel; | |
1141 | } | |
1142 | ||
1143 | header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | | |
1144 | IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE); | |
1145 | header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT); | |
1146 | header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT); | |
1147 | header |= (stage_id << IPC_STG_ID_SHIFT); | |
1148 | ||
1149 | req.curve_duration = hsw->curve_duration; | |
1150 | req.curve_type = hsw->curve_type; | |
1151 | req.target_volume = volume; | |
1152 | ||
1153 | ret = ipc_tx_message_wait(hsw, header, &req, sizeof(req), NULL, 0); | |
1154 | if (ret < 0) { | |
1155 | dev_err(hsw->dev, "error: set mixer volume failed\n"); | |
1156 | return ret; | |
1157 | } | |
1158 | ||
1159 | return 0; | |
1160 | } | |
1161 | ||
1162 | /* Stream API */ | |
1163 | struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id, | |
1164 | u32 (*notify_position)(struct sst_hsw_stream *stream, void *data), | |
1165 | void *data) | |
1166 | { | |
1167 | struct sst_hsw_stream *stream; | |
d132cb0a WD |
1168 | struct sst_dsp *sst = hsw->dsp; |
1169 | unsigned long flags; | |
a4b12990 MB |
1170 | |
1171 | stream = kzalloc(sizeof(*stream), GFP_KERNEL); | |
1172 | if (stream == NULL) | |
1173 | return NULL; | |
1174 | ||
d132cb0a | 1175 | spin_lock_irqsave(&sst->spinlock, flags); |
a0a7c48f | 1176 | stream->reply.stream_hw_id = INVALID_STREAM_HW_ID; |
a4b12990 MB |
1177 | list_add(&stream->node, &hsw->stream_list); |
1178 | stream->notify_position = notify_position; | |
1179 | stream->pdata = data; | |
1180 | stream->hsw = hsw; | |
1181 | stream->host_id = id; | |
1182 | ||
1183 | /* work to process notification messages */ | |
1184 | INIT_WORK(&stream->notify_work, hsw_notification_work); | |
d132cb0a | 1185 | spin_unlock_irqrestore(&sst->spinlock, flags); |
a4b12990 MB |
1186 | |
1187 | return stream; | |
1188 | } | |
1189 | ||
1190 | int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream) | |
1191 | { | |
1192 | u32 header; | |
1193 | int ret = 0; | |
d132cb0a WD |
1194 | struct sst_dsp *sst = hsw->dsp; |
1195 | unsigned long flags; | |
a4b12990 | 1196 | |
f81677b4 JY |
1197 | if (!stream) { |
1198 | dev_warn(hsw->dev, "warning: stream is NULL, no stream to free, ignore it.\n"); | |
1199 | return 0; | |
1200 | } | |
1201 | ||
a4b12990 MB |
1202 | /* dont free DSP streams that are not commited */ |
1203 | if (!stream->commited) | |
1204 | goto out; | |
1205 | ||
1206 | trace_ipc_request("stream free", stream->host_id); | |
1207 | ||
1208 | stream->free_req.stream_id = stream->reply.stream_hw_id; | |
1209 | header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM); | |
1210 | ||
1211 | ret = ipc_tx_message_wait(hsw, header, &stream->free_req, | |
1212 | sizeof(stream->free_req), NULL, 0); | |
1213 | if (ret < 0) { | |
1214 | dev_err(hsw->dev, "error: free stream %d failed\n", | |
1215 | stream->free_req.stream_id); | |
1216 | return -EAGAIN; | |
1217 | } | |
1218 | ||
1219 | trace_hsw_stream_free_req(stream, &stream->free_req); | |
1220 | ||
1221 | out: | |
de30a2cc | 1222 | cancel_work_sync(&stream->notify_work); |
d132cb0a | 1223 | spin_lock_irqsave(&sst->spinlock, flags); |
a4b12990 MB |
1224 | list_del(&stream->node); |
1225 | kfree(stream); | |
d132cb0a | 1226 | spin_unlock_irqrestore(&sst->spinlock, flags); |
a4b12990 MB |
1227 | |
1228 | return ret; | |
1229 | } | |
1230 | ||
1231 | int sst_hsw_stream_set_bits(struct sst_hsw *hsw, | |
1232 | struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits) | |
1233 | { | |
1234 | if (stream->commited) { | |
1235 | dev_err(hsw->dev, "error: stream committed for set bits\n"); | |
1236 | return -EINVAL; | |
1237 | } | |
1238 | ||
1239 | stream->request.format.bitdepth = bits; | |
1240 | return 0; | |
1241 | } | |
1242 | ||
1243 | int sst_hsw_stream_set_channels(struct sst_hsw *hsw, | |
1244 | struct sst_hsw_stream *stream, int channels) | |
1245 | { | |
1246 | if (stream->commited) { | |
1247 | dev_err(hsw->dev, "error: stream committed for set channels\n"); | |
1248 | return -EINVAL; | |
1249 | } | |
1250 | ||
a4b12990 MB |
1251 | stream->request.format.ch_num = channels; |
1252 | return 0; | |
1253 | } | |
1254 | ||
1255 | int sst_hsw_stream_set_rate(struct sst_hsw *hsw, | |
1256 | struct sst_hsw_stream *stream, int rate) | |
1257 | { | |
1258 | if (stream->commited) { | |
1259 | dev_err(hsw->dev, "error: stream committed for set rate\n"); | |
1260 | return -EINVAL; | |
1261 | } | |
1262 | ||
1263 | stream->request.format.frequency = rate; | |
1264 | return 0; | |
1265 | } | |
1266 | ||
1267 | int sst_hsw_stream_set_map_config(struct sst_hsw *hsw, | |
1268 | struct sst_hsw_stream *stream, u32 map, | |
1269 | enum sst_hsw_channel_config config) | |
1270 | { | |
1271 | if (stream->commited) { | |
1272 | dev_err(hsw->dev, "error: stream committed for set map\n"); | |
1273 | return -EINVAL; | |
1274 | } | |
1275 | ||
1276 | stream->request.format.map = map; | |
1277 | stream->request.format.config = config; | |
1278 | return 0; | |
1279 | } | |
1280 | ||
1281 | int sst_hsw_stream_set_style(struct sst_hsw *hsw, | |
1282 | struct sst_hsw_stream *stream, enum sst_hsw_interleaving style) | |
1283 | { | |
1284 | if (stream->commited) { | |
1285 | dev_err(hsw->dev, "error: stream committed for set style\n"); | |
1286 | return -EINVAL; | |
1287 | } | |
1288 | ||
1289 | stream->request.format.style = style; | |
1290 | return 0; | |
1291 | } | |
1292 | ||
1293 | int sst_hsw_stream_set_valid(struct sst_hsw *hsw, | |
1294 | struct sst_hsw_stream *stream, u32 bits) | |
1295 | { | |
1296 | if (stream->commited) { | |
1297 | dev_err(hsw->dev, "error: stream committed for set valid bits\n"); | |
1298 | return -EINVAL; | |
1299 | } | |
1300 | ||
1301 | stream->request.format.valid_bit = bits; | |
1302 | return 0; | |
1303 | } | |
1304 | ||
1305 | /* Stream Configuration */ | |
1306 | int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream, | |
1307 | enum sst_hsw_stream_path_id path_id, | |
1308 | enum sst_hsw_stream_type stream_type, | |
1309 | enum sst_hsw_stream_format format_id) | |
1310 | { | |
1311 | if (stream->commited) { | |
1312 | dev_err(hsw->dev, "error: stream committed for set format\n"); | |
1313 | return -EINVAL; | |
1314 | } | |
1315 | ||
1316 | stream->request.path_id = path_id; | |
1317 | stream->request.stream_type = stream_type; | |
1318 | stream->request.format_id = format_id; | |
1319 | ||
1320 | trace_hsw_stream_alloc_request(stream, &stream->request); | |
1321 | ||
1322 | return 0; | |
1323 | } | |
1324 | ||
1325 | int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream, | |
1326 | u32 ring_pt_address, u32 num_pages, | |
1327 | u32 ring_size, u32 ring_offset, u32 ring_first_pfn) | |
1328 | { | |
1329 | if (stream->commited) { | |
1330 | dev_err(hsw->dev, "error: stream committed for buffer\n"); | |
1331 | return -EINVAL; | |
1332 | } | |
1333 | ||
1334 | stream->request.ringinfo.ring_pt_address = ring_pt_address; | |
1335 | stream->request.ringinfo.num_pages = num_pages; | |
1336 | stream->request.ringinfo.ring_size = ring_size; | |
1337 | stream->request.ringinfo.ring_offset = ring_offset; | |
1338 | stream->request.ringinfo.ring_first_pfn = ring_first_pfn; | |
1339 | ||
1340 | trace_hsw_stream_buffer(stream); | |
1341 | ||
1342 | return 0; | |
1343 | } | |
1344 | ||
1345 | int sst_hsw_stream_set_module_info(struct sst_hsw *hsw, | |
e9600bc1 | 1346 | struct sst_hsw_stream *stream, struct sst_module_runtime *runtime) |
a4b12990 MB |
1347 | { |
1348 | struct sst_hsw_module_map *map = &stream->request.map; | |
e9600bc1 LG |
1349 | struct sst_dsp *dsp = sst_hsw_get_dsp(hsw); |
1350 | struct sst_module *module = runtime->module; | |
a4b12990 MB |
1351 | |
1352 | if (stream->commited) { | |
1353 | dev_err(hsw->dev, "error: stream committed for set module\n"); | |
1354 | return -EINVAL; | |
1355 | } | |
1356 | ||
1357 | /* only support initial module atm */ | |
1358 | map->module_entries_count = 1; | |
e9600bc1 LG |
1359 | map->module_entries[0].module_id = module->id; |
1360 | map->module_entries[0].entry_point = module->entry; | |
1361 | ||
1362 | stream->request.persistent_mem.offset = | |
1363 | sst_dsp_get_offset(dsp, runtime->persistent_offset, SST_MEM_DRAM); | |
1364 | stream->request.persistent_mem.size = module->persistent_size; | |
1365 | ||
1366 | stream->request.scratch_mem.offset = | |
1367 | sst_dsp_get_offset(dsp, dsp->scratch_offset, SST_MEM_DRAM); | |
1368 | stream->request.scratch_mem.size = dsp->scratch_size; | |
1369 | ||
1370 | dev_dbg(hsw->dev, "module %d runtime %d using:\n", module->id, | |
1371 | runtime->id); | |
1372 | dev_dbg(hsw->dev, " persistent offset 0x%x bytes 0x%x\n", | |
1373 | stream->request.persistent_mem.offset, | |
1374 | stream->request.persistent_mem.size); | |
1375 | dev_dbg(hsw->dev, " scratch offset 0x%x bytes 0x%x\n", | |
1376 | stream->request.scratch_mem.offset, | |
1377 | stream->request.scratch_mem.size); | |
a4b12990 MB |
1378 | |
1379 | return 0; | |
1380 | } | |
1381 | ||
1382 | int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream) | |
1383 | { | |
1384 | struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request; | |
1385 | struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply; | |
1386 | u32 header; | |
1387 | int ret; | |
1388 | ||
f81677b4 JY |
1389 | if (!stream) { |
1390 | dev_warn(hsw->dev, "warning: stream is NULL, no stream to commit, ignore it.\n"); | |
1391 | return 0; | |
1392 | } | |
1393 | ||
1394 | if (stream->commited) { | |
1395 | dev_warn(hsw->dev, "warning: stream is already committed, ignore it.\n"); | |
1396 | return 0; | |
1397 | } | |
1398 | ||
a4b12990 MB |
1399 | trace_ipc_request("stream alloc", stream->host_id); |
1400 | ||
1401 | header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM); | |
1402 | ||
1403 | ret = ipc_tx_message_wait(hsw, header, str_req, sizeof(*str_req), | |
1404 | reply, sizeof(*reply)); | |
1405 | if (ret < 0) { | |
1406 | dev_err(hsw->dev, "error: stream commit failed\n"); | |
1407 | return ret; | |
1408 | } | |
1409 | ||
1410 | stream->commited = 1; | |
1411 | trace_hsw_stream_alloc_reply(stream); | |
1412 | ||
1413 | return 0; | |
1414 | } | |
1415 | ||
1b006996 LY |
1416 | snd_pcm_uframes_t sst_hsw_stream_get_old_position(struct sst_hsw *hsw, |
1417 | struct sst_hsw_stream *stream) | |
1418 | { | |
1419 | return stream->old_position; | |
1420 | } | |
1421 | ||
1422 | void sst_hsw_stream_set_old_position(struct sst_hsw *hsw, | |
1423 | struct sst_hsw_stream *stream, snd_pcm_uframes_t val) | |
1424 | { | |
1425 | stream->old_position = val; | |
1426 | } | |
1427 | ||
1428 | bool sst_hsw_stream_get_silence_start(struct sst_hsw *hsw, | |
1429 | struct sst_hsw_stream *stream) | |
1430 | { | |
1431 | return stream->play_silence; | |
1432 | } | |
1433 | ||
1434 | void sst_hsw_stream_set_silence_start(struct sst_hsw *hsw, | |
1435 | struct sst_hsw_stream *stream, bool val) | |
1436 | { | |
1437 | stream->play_silence = val; | |
1438 | } | |
1439 | ||
a4b12990 MB |
1440 | /* Stream Information - these calls could be inline but we want the IPC |
1441 | ABI to be opaque to client PCM drivers to cope with any future ABI changes */ | |
a4b12990 MB |
1442 | int sst_hsw_mixer_get_info(struct sst_hsw *hsw) |
1443 | { | |
1444 | struct sst_hsw_ipc_stream_info_reply *reply; | |
1445 | u32 header; | |
1446 | int ret; | |
1447 | ||
1448 | reply = &hsw->mixer_info; | |
1449 | header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO); | |
1450 | ||
1451 | trace_ipc_request("get global mixer info", 0); | |
1452 | ||
1453 | ret = ipc_tx_message_wait(hsw, header, NULL, 0, reply, sizeof(*reply)); | |
1454 | if (ret < 0) { | |
1455 | dev_err(hsw->dev, "error: get stream info failed\n"); | |
1456 | return ret; | |
1457 | } | |
1458 | ||
1459 | trace_hsw_mixer_info_reply(reply); | |
1460 | ||
1461 | return 0; | |
1462 | } | |
1463 | ||
1464 | /* Send stream command */ | |
1465 | static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type, | |
1466 | int stream_id, int wait) | |
1467 | { | |
1468 | u32 header; | |
1469 | ||
1470 | header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type); | |
1471 | header |= (stream_id << IPC_STR_ID_SHIFT); | |
1472 | ||
1473 | if (wait) | |
1474 | return ipc_tx_message_wait(hsw, header, NULL, 0, NULL, 0); | |
1475 | else | |
1476 | return ipc_tx_message_nowait(hsw, header, NULL, 0); | |
1477 | } | |
1478 | ||
1479 | /* Stream ALSA trigger operations */ | |
1480 | int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream, | |
1481 | int wait) | |
1482 | { | |
1483 | int ret; | |
1484 | ||
f81677b4 JY |
1485 | if (!stream) { |
1486 | dev_warn(hsw->dev, "warning: stream is NULL, no stream to pause, ignore it.\n"); | |
1487 | return 0; | |
1488 | } | |
1489 | ||
a4b12990 MB |
1490 | trace_ipc_request("stream pause", stream->reply.stream_hw_id); |
1491 | ||
1492 | ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE, | |
1493 | stream->reply.stream_hw_id, wait); | |
1494 | if (ret < 0) | |
1495 | dev_err(hsw->dev, "error: failed to pause stream %d\n", | |
1496 | stream->reply.stream_hw_id); | |
1497 | ||
1498 | return ret; | |
1499 | } | |
1500 | ||
1501 | int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream, | |
1502 | int wait) | |
1503 | { | |
1504 | int ret; | |
1505 | ||
f81677b4 JY |
1506 | if (!stream) { |
1507 | dev_warn(hsw->dev, "warning: stream is NULL, no stream to resume, ignore it.\n"); | |
1508 | return 0; | |
1509 | } | |
1510 | ||
a4b12990 MB |
1511 | trace_ipc_request("stream resume", stream->reply.stream_hw_id); |
1512 | ||
1513 | ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME, | |
1514 | stream->reply.stream_hw_id, wait); | |
1515 | if (ret < 0) | |
1516 | dev_err(hsw->dev, "error: failed to resume stream %d\n", | |
1517 | stream->reply.stream_hw_id); | |
1518 | ||
1519 | return ret; | |
1520 | } | |
1521 | ||
1522 | int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream) | |
1523 | { | |
1524 | int ret, tries = 10; | |
1525 | ||
f81677b4 JY |
1526 | if (!stream) { |
1527 | dev_warn(hsw->dev, "warning: stream is NULL, no stream to reset, ignore it.\n"); | |
1528 | return 0; | |
1529 | } | |
1530 | ||
a4b12990 MB |
1531 | /* dont reset streams that are not commited */ |
1532 | if (!stream->commited) | |
1533 | return 0; | |
1534 | ||
1535 | /* wait for pause to complete before we reset the stream */ | |
1536 | while (stream->running && tries--) | |
1537 | msleep(1); | |
1538 | if (!tries) { | |
1539 | dev_err(hsw->dev, "error: reset stream %d still running\n", | |
1540 | stream->reply.stream_hw_id); | |
1541 | return -EINVAL; | |
1542 | } | |
1543 | ||
1544 | trace_ipc_request("stream reset", stream->reply.stream_hw_id); | |
1545 | ||
1546 | ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET, | |
1547 | stream->reply.stream_hw_id, 1); | |
1548 | if (ret < 0) | |
1549 | dev_err(hsw->dev, "error: failed to reset stream %d\n", | |
1550 | stream->reply.stream_hw_id); | |
1551 | return ret; | |
1552 | } | |
1553 | ||
1554 | /* Stream pointer positions */ | |
51b4e24f | 1555 | u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw, |
a4b12990 MB |
1556 | struct sst_hsw_stream *stream) |
1557 | { | |
51b4e24f LG |
1558 | u32 rpos; |
1559 | ||
1560 | sst_dsp_read(hsw->dsp, &rpos, | |
1561 | stream->reply.read_position_register_address, sizeof(rpos)); | |
1562 | ||
1563 | return rpos; | |
1564 | } | |
1565 | ||
1566 | /* Stream presentation (monotonic) positions */ | |
1567 | u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw, | |
1568 | struct sst_hsw_stream *stream) | |
1569 | { | |
1570 | u64 ppos; | |
1571 | ||
1572 | sst_dsp_read(hsw->dsp, &ppos, | |
1573 | stream->reply.presentation_position_register_address, | |
1574 | sizeof(ppos)); | |
1575 | ||
1576 | return ppos; | |
a4b12990 MB |
1577 | } |
1578 | ||
a4b12990 MB |
1579 | /* physical BE config */ |
1580 | int sst_hsw_device_set_config(struct sst_hsw *hsw, | |
1581 | enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk, | |
1582 | enum sst_hsw_device_mode mode, u32 clock_divider) | |
1583 | { | |
1584 | struct sst_hsw_ipc_device_config_req config; | |
1585 | u32 header; | |
1586 | int ret; | |
1587 | ||
1588 | trace_ipc_request("set device config", dev); | |
1589 | ||
1590 | config.ssp_interface = dev; | |
1591 | config.clock_frequency = mclk; | |
1592 | config.mode = mode; | |
1593 | config.clock_divider = clock_divider; | |
f07e51c5 LG |
1594 | if (mode == SST_HSW_DEVICE_TDM_CLOCK_MASTER) |
1595 | config.channels = 4; | |
1596 | else | |
1597 | config.channels = 2; | |
a4b12990 MB |
1598 | |
1599 | trace_hsw_device_config_req(&config); | |
1600 | ||
1601 | header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS); | |
1602 | ||
1603 | ret = ipc_tx_message_wait(hsw, header, &config, sizeof(config), | |
1604 | NULL, 0); | |
1605 | if (ret < 0) | |
1606 | dev_err(hsw->dev, "error: set device formats failed\n"); | |
1607 | ||
1608 | return ret; | |
1609 | } | |
1610 | EXPORT_SYMBOL_GPL(sst_hsw_device_set_config); | |
1611 | ||
1612 | /* DX Config */ | |
1613 | int sst_hsw_dx_set_state(struct sst_hsw *hsw, | |
1614 | enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx) | |
1615 | { | |
1616 | u32 header, state_; | |
543ec637 | 1617 | int ret, item; |
a4b12990 MB |
1618 | |
1619 | header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE); | |
1620 | state_ = state; | |
1621 | ||
1622 | trace_ipc_request("PM enter Dx state", state); | |
1623 | ||
1624 | ret = ipc_tx_message_wait(hsw, header, &state_, sizeof(state_), | |
7897ab78 | 1625 | dx, sizeof(*dx)); |
a4b12990 MB |
1626 | if (ret < 0) { |
1627 | dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state); | |
1628 | return ret; | |
1629 | } | |
1630 | ||
543ec637 LG |
1631 | for (item = 0; item < dx->entries_no; item++) { |
1632 | dev_dbg(hsw->dev, | |
1633 | "Item[%d] offset[%x] - size[%x] - source[%x]\n", | |
1634 | item, dx->mem_info[item].offset, | |
1635 | dx->mem_info[item].size, | |
1636 | dx->mem_info[item].source); | |
1637 | } | |
a4b12990 MB |
1638 | dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n", |
1639 | dx->entries_no, state); | |
1640 | ||
e9600bc1 | 1641 | return ret; |
a4b12990 MB |
1642 | } |
1643 | ||
e9600bc1 LG |
1644 | struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw, |
1645 | int mod_id, int offset) | |
a4b12990 | 1646 | { |
e9600bc1 LG |
1647 | struct sst_dsp *dsp = hsw->dsp; |
1648 | struct sst_module *module; | |
1649 | struct sst_module_runtime *runtime; | |
1650 | int err; | |
a4b12990 | 1651 | |
e9600bc1 LG |
1652 | module = sst_module_get_from_id(dsp, mod_id); |
1653 | if (module == NULL) { | |
1654 | dev_err(dsp->dev, "error: failed to get module %d for pcm\n", | |
1655 | mod_id); | |
1656 | return NULL; | |
1657 | } | |
a4b12990 | 1658 | |
e9600bc1 LG |
1659 | runtime = sst_module_runtime_new(module, mod_id, NULL); |
1660 | if (runtime == NULL) { | |
1661 | dev_err(dsp->dev, "error: failed to create module %d runtime\n", | |
1662 | mod_id); | |
1663 | return NULL; | |
1664 | } | |
a4b12990 | 1665 | |
e9600bc1 LG |
1666 | err = sst_module_runtime_alloc_blocks(runtime, offset); |
1667 | if (err < 0) { | |
1668 | dev_err(dsp->dev, "error: failed to alloc blocks for module %d runtime\n", | |
1669 | mod_id); | |
1670 | sst_module_runtime_free(runtime); | |
1671 | return NULL; | |
1672 | } | |
a4b12990 | 1673 | |
e9600bc1 LG |
1674 | dev_dbg(dsp->dev, "runtime id %d created for module %d\n", runtime->id, |
1675 | mod_id); | |
1676 | return runtime; | |
1677 | } | |
a4b12990 | 1678 | |
e9600bc1 LG |
1679 | void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime) |
1680 | { | |
1681 | sst_module_runtime_free_blocks(runtime); | |
1682 | sst_module_runtime_free(runtime); | |
a4b12990 MB |
1683 | } |
1684 | ||
35e03a88 | 1685 | #ifdef CONFIG_PM |
aed3c7b7 LG |
1686 | static int sst_hsw_dx_state_dump(struct sst_hsw *hsw) |
1687 | { | |
1688 | struct sst_dsp *sst = hsw->dsp; | |
1689 | u32 item, offset, size; | |
1690 | int ret = 0; | |
1691 | ||
1692 | trace_ipc_request("PM state dump. Items #", SST_HSW_MAX_DX_REGIONS); | |
1693 | ||
1694 | if (hsw->dx.entries_no > SST_HSW_MAX_DX_REGIONS) { | |
1695 | dev_err(hsw->dev, | |
1696 | "error: number of FW context regions greater than %d\n", | |
1697 | SST_HSW_MAX_DX_REGIONS); | |
1698 | memset(&hsw->dx, 0, sizeof(hsw->dx)); | |
1699 | return -EINVAL; | |
1700 | } | |
1701 | ||
1702 | ret = sst_dsp_dma_get_channel(sst, 0); | |
1703 | if (ret < 0) { | |
1704 | dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret); | |
1705 | return ret; | |
1706 | } | |
1707 | ||
1708 | /* set on-demond mode on engine 0 channel 3 */ | |
1709 | sst_dsp_shim_update_bits(sst, SST_HMDC, | |
1710 | SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH, | |
1711 | SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH); | |
1712 | ||
1713 | for (item = 0; item < hsw->dx.entries_no; item++) { | |
1714 | if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP | |
1715 | && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET | |
1716 | && hsw->dx.mem_info[item].offset < | |
1717 | DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) { | |
1718 | ||
1719 | offset = hsw->dx.mem_info[item].offset | |
1720 | - DSP_DRAM_ADDR_OFFSET; | |
1721 | size = (hsw->dx.mem_info[item].size + 3) & (~3); | |
1722 | ||
1723 | ret = sst_dsp_dma_copyfrom(sst, hsw->dx_context_paddr + offset, | |
1724 | sst->addr.lpe_base + offset, size); | |
1725 | if (ret < 0) { | |
1726 | dev_err(hsw->dev, | |
1727 | "error: FW context dump failed\n"); | |
1728 | memset(&hsw->dx, 0, sizeof(hsw->dx)); | |
1729 | goto out; | |
1730 | } | |
1731 | } | |
1732 | } | |
1733 | ||
1734 | out: | |
1735 | sst_dsp_dma_put_channel(sst); | |
1736 | return ret; | |
1737 | } | |
1738 | ||
1739 | static int sst_hsw_dx_state_restore(struct sst_hsw *hsw) | |
1740 | { | |
1741 | struct sst_dsp *sst = hsw->dsp; | |
1742 | u32 item, offset, size; | |
1743 | int ret; | |
1744 | ||
1745 | for (item = 0; item < hsw->dx.entries_no; item++) { | |
1746 | if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP | |
1747 | && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET | |
1748 | && hsw->dx.mem_info[item].offset < | |
1749 | DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) { | |
1750 | ||
1751 | offset = hsw->dx.mem_info[item].offset | |
1752 | - DSP_DRAM_ADDR_OFFSET; | |
1753 | size = (hsw->dx.mem_info[item].size + 3) & (~3); | |
1754 | ||
1755 | ret = sst_dsp_dma_copyto(sst, sst->addr.lpe_base + offset, | |
1756 | hsw->dx_context_paddr + offset, size); | |
1757 | if (ret < 0) { | |
1758 | dev_err(hsw->dev, | |
1759 | "error: FW context restore failed\n"); | |
1760 | return ret; | |
1761 | } | |
1762 | } | |
1763 | } | |
1764 | ||
1765 | return 0; | |
1766 | } | |
1767 | ||
1768 | static void sst_hsw_drop_all(struct sst_hsw *hsw) | |
1769 | { | |
1770 | struct ipc_message *msg, *tmp; | |
1771 | unsigned long flags; | |
1772 | int tx_drop_cnt = 0, rx_drop_cnt = 0; | |
1773 | ||
1774 | /* drop all TX and Rx messages before we stall + reset DSP */ | |
1775 | spin_lock_irqsave(&hsw->dsp->spinlock, flags); | |
1776 | ||
1777 | list_for_each_entry_safe(msg, tmp, &hsw->tx_list, list) { | |
1778 | list_move(&msg->list, &hsw->empty_list); | |
1779 | tx_drop_cnt++; | |
1780 | } | |
1781 | ||
1782 | list_for_each_entry_safe(msg, tmp, &hsw->rx_list, list) { | |
1783 | list_move(&msg->list, &hsw->empty_list); | |
1784 | rx_drop_cnt++; | |
1785 | } | |
1786 | ||
1787 | spin_unlock_irqrestore(&hsw->dsp->spinlock, flags); | |
1788 | ||
1789 | if (tx_drop_cnt || rx_drop_cnt) | |
1790 | dev_err(hsw->dev, "dropped IPC msg RX=%d, TX=%d\n", | |
1791 | tx_drop_cnt, rx_drop_cnt); | |
1792 | } | |
1793 | ||
1794 | int sst_hsw_dsp_load(struct sst_hsw *hsw) | |
1795 | { | |
1796 | struct sst_dsp *dsp = hsw->dsp; | |
3fe0607a | 1797 | struct sst_fw *sst_fw, *t; |
aed3c7b7 LG |
1798 | int ret; |
1799 | ||
1800 | dev_dbg(hsw->dev, "loading audio DSP...."); | |
1801 | ||
1802 | ret = sst_dsp_wake(dsp); | |
1803 | if (ret < 0) { | |
1804 | dev_err(hsw->dev, "error: failed to wake audio DSP\n"); | |
1805 | return -ENODEV; | |
1806 | } | |
1807 | ||
1808 | ret = sst_dsp_dma_get_channel(dsp, 0); | |
1809 | if (ret < 0) { | |
1810 | dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret); | |
1811 | return ret; | |
1812 | } | |
1813 | ||
3fe0607a LH |
1814 | list_for_each_entry_safe_reverse(sst_fw, t, &dsp->fw_list, list) { |
1815 | ret = sst_fw_reload(sst_fw); | |
1816 | if (ret < 0) { | |
1817 | dev_err(hsw->dev, "error: SST FW reload failed\n"); | |
1818 | sst_dsp_dma_put_channel(dsp); | |
1819 | return -ENOMEM; | |
1820 | } | |
aed3c7b7 | 1821 | } |
3fe0607a LH |
1822 | ret = sst_block_alloc_scratch(hsw->dsp); |
1823 | if (ret < 0) | |
1824 | return -EINVAL; | |
aed3c7b7 LG |
1825 | |
1826 | sst_dsp_dma_put_channel(dsp); | |
1827 | return 0; | |
1828 | } | |
1829 | ||
1830 | static int sst_hsw_dsp_restore(struct sst_hsw *hsw) | |
1831 | { | |
1832 | struct sst_dsp *dsp = hsw->dsp; | |
1833 | int ret; | |
1834 | ||
1835 | dev_dbg(hsw->dev, "restoring audio DSP...."); | |
1836 | ||
1837 | ret = sst_dsp_dma_get_channel(dsp, 0); | |
1838 | if (ret < 0) { | |
1839 | dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret); | |
1840 | return ret; | |
1841 | } | |
1842 | ||
1843 | ret = sst_hsw_dx_state_restore(hsw); | |
1844 | if (ret < 0) { | |
1845 | dev_err(hsw->dev, "error: SST FW context restore failed\n"); | |
1846 | sst_dsp_dma_put_channel(dsp); | |
1847 | return -ENOMEM; | |
1848 | } | |
1849 | sst_dsp_dma_put_channel(dsp); | |
1850 | ||
1851 | /* wait for DSP boot completion */ | |
1852 | sst_dsp_boot(dsp); | |
1853 | ||
1854 | return ret; | |
1855 | } | |
1856 | ||
1857 | int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw) | |
1858 | { | |
1859 | int ret; | |
1860 | ||
1861 | dev_dbg(hsw->dev, "audio dsp runtime suspend\n"); | |
1862 | ||
1863 | ret = sst_hsw_dx_set_state(hsw, SST_HSW_DX_STATE_D3, &hsw->dx); | |
1864 | if (ret < 0) | |
1865 | return ret; | |
1866 | ||
1867 | sst_dsp_stall(hsw->dsp); | |
1868 | ||
1869 | ret = sst_hsw_dx_state_dump(hsw); | |
1870 | if (ret < 0) | |
1871 | return ret; | |
1872 | ||
1873 | sst_hsw_drop_all(hsw); | |
1874 | ||
1875 | return 0; | |
1876 | } | |
1877 | ||
1878 | int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw) | |
1879 | { | |
3fe0607a LH |
1880 | struct sst_fw *sst_fw, *t; |
1881 | struct sst_dsp *dsp = hsw->dsp; | |
1882 | ||
1883 | list_for_each_entry_safe(sst_fw, t, &dsp->fw_list, list) { | |
1884 | sst_fw_unload(sst_fw); | |
1885 | } | |
1886 | sst_block_free_scratch(dsp); | |
aed3c7b7 LG |
1887 | |
1888 | hsw->boot_complete = false; | |
1889 | ||
3fe0607a | 1890 | sst_dsp_sleep(dsp); |
aed3c7b7 LG |
1891 | |
1892 | return 0; | |
1893 | } | |
1894 | ||
1895 | int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw) | |
1896 | { | |
1897 | struct device *dev = hsw->dev; | |
1898 | int ret; | |
1899 | ||
1900 | dev_dbg(dev, "audio dsp runtime resume\n"); | |
1901 | ||
1902 | if (hsw->boot_complete) | |
1903 | return 1; /* tell caller no action is required */ | |
1904 | ||
1905 | ret = sst_hsw_dsp_restore(hsw); | |
1906 | if (ret < 0) | |
1907 | dev_err(dev, "error: audio DSP boot failure\n"); | |
1908 | ||
9449d39b LH |
1909 | sst_hsw_init_module_state(hsw); |
1910 | ||
aed3c7b7 LG |
1911 | ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete, |
1912 | msecs_to_jiffies(IPC_BOOT_MSECS)); | |
1913 | if (ret == 0) { | |
b891f62f LG |
1914 | dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n", |
1915 | sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD), | |
1916 | sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX)); | |
aed3c7b7 LG |
1917 | return -EIO; |
1918 | } | |
1919 | ||
1920 | /* Set ADSP SSP port settings */ | |
1921 | ret = sst_hsw_device_set_config(hsw, SST_HSW_DEVICE_SSP_0, | |
1922 | SST_HSW_DEVICE_MCLK_FREQ_24_MHZ, | |
1923 | SST_HSW_DEVICE_CLOCK_MASTER, 9); | |
1924 | if (ret < 0) | |
1925 | dev_err(dev, "error: SSP re-initialization failed\n"); | |
1926 | ||
1927 | return ret; | |
1928 | } | |
1929 | #endif | |
1930 | ||
a4b12990 MB |
1931 | static int msg_empty_list_init(struct sst_hsw *hsw) |
1932 | { | |
1933 | int i; | |
1934 | ||
1935 | hsw->msg = kzalloc(sizeof(struct ipc_message) * | |
1936 | IPC_EMPTY_LIST_SIZE, GFP_KERNEL); | |
1937 | if (hsw->msg == NULL) | |
1938 | return -ENOMEM; | |
1939 | ||
1940 | for (i = 0; i < IPC_EMPTY_LIST_SIZE; i++) { | |
1941 | init_waitqueue_head(&hsw->msg[i].waitq); | |
1942 | list_add(&hsw->msg[i].list, &hsw->empty_list); | |
1943 | } | |
1944 | ||
1945 | return 0; | |
1946 | } | |
1947 | ||
a4b12990 MB |
1948 | struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw) |
1949 | { | |
1950 | return hsw->dsp; | |
1951 | } | |
1952 | ||
9449d39b LH |
1953 | void sst_hsw_init_module_state(struct sst_hsw *hsw) |
1954 | { | |
1955 | struct sst_module *module; | |
1956 | enum sst_hsw_module_id id; | |
1957 | ||
1958 | /* the base fw contains several modules */ | |
1959 | for (id = SST_HSW_MODULE_BASE_FW; id < SST_HSW_MAX_MODULE_ID; id++) { | |
1960 | module = sst_module_get_from_id(hsw->dsp, id); | |
8c43fc2f LH |
1961 | if (module) { |
1962 | /* module waves is active only after being enabled */ | |
1963 | if (id == SST_HSW_MODULE_WAVES) | |
1964 | module->state = SST_MODULE_STATE_INITIALIZED; | |
1965 | else | |
1966 | module->state = SST_MODULE_STATE_ACTIVE; | |
1967 | } | |
9449d39b LH |
1968 | } |
1969 | } | |
1970 | ||
8c43fc2f LH |
1971 | bool sst_hsw_is_module_loaded(struct sst_hsw *hsw, u32 module_id) |
1972 | { | |
1973 | struct sst_module *module; | |
1974 | ||
1975 | module = sst_module_get_from_id(hsw->dsp, module_id); | |
1976 | if (module == NULL || module->state == SST_MODULE_STATE_UNLOADED) | |
1977 | return false; | |
1978 | else | |
1979 | return true; | |
1980 | } | |
1981 | ||
e8e79ede LH |
1982 | bool sst_hsw_is_module_active(struct sst_hsw *hsw, u32 module_id) |
1983 | { | |
1984 | struct sst_module *module; | |
1985 | ||
1986 | module = sst_module_get_from_id(hsw->dsp, module_id); | |
1987 | if (module != NULL && module->state == SST_MODULE_STATE_ACTIVE) | |
1988 | return true; | |
1989 | else | |
1990 | return false; | |
1991 | } | |
1992 | ||
76c07b82 LH |
1993 | void sst_hsw_set_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id) |
1994 | { | |
1995 | hsw->enabled_modules_rtd3 |= (1 << module_id); | |
1996 | } | |
1997 | ||
1998 | void sst_hsw_set_module_disabled_rtd3(struct sst_hsw *hsw, u32 module_id) | |
1999 | { | |
2000 | hsw->enabled_modules_rtd3 &= ~(1 << module_id); | |
2001 | } | |
2002 | ||
2003 | bool sst_hsw_is_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id) | |
2004 | { | |
2005 | return hsw->enabled_modules_rtd3 & (1 << module_id); | |
2006 | } | |
2007 | ||
9449d39b LH |
2008 | int sst_hsw_module_load(struct sst_hsw *hsw, |
2009 | u32 module_id, u32 instance_id, char *name) | |
2010 | { | |
2011 | int ret = 0; | |
2012 | const struct firmware *fw = NULL; | |
2013 | struct sst_fw *hsw_sst_fw; | |
2014 | struct sst_module *module; | |
2015 | struct device *dev = hsw->dev; | |
2016 | struct sst_dsp *dsp = hsw->dsp; | |
2017 | ||
2018 | dev_dbg(dev, "sst_hsw_module_load id=%d, name='%s'", module_id, name); | |
2019 | ||
2020 | module = sst_module_get_from_id(dsp, module_id); | |
2021 | if (module == NULL) { | |
2022 | /* loading for the first time */ | |
2023 | if (module_id == SST_HSW_MODULE_BASE_FW) { | |
2024 | /* for base module: use fw requested in acpi probe */ | |
2025 | fw = dsp->pdata->fw; | |
2026 | if (!fw) { | |
2027 | dev_err(dev, "request Base fw failed\n"); | |
2028 | return -ENODEV; | |
2029 | } | |
2030 | } else { | |
2031 | /* try and load any other optional modules if they are | |
2032 | * available. Use dev_info instead of dev_err in case | |
2033 | * request firmware failed */ | |
2034 | ret = request_firmware(&fw, name, dev); | |
2035 | if (ret) { | |
2036 | dev_info(dev, "fw image %s not available(%d)\n", | |
2037 | name, ret); | |
2038 | return ret; | |
2039 | } | |
2040 | } | |
2041 | hsw_sst_fw = sst_fw_new(dsp, fw, hsw); | |
2042 | if (hsw_sst_fw == NULL) { | |
2043 | dev_err(dev, "error: failed to load firmware\n"); | |
2044 | ret = -ENOMEM; | |
2045 | goto out; | |
2046 | } | |
2047 | module = sst_module_get_from_id(dsp, module_id); | |
2048 | if (module == NULL) { | |
2049 | dev_err(dev, "error: no module %d in firmware %s\n", | |
2050 | module_id, name); | |
2051 | } | |
2052 | } else | |
2053 | dev_info(dev, "module %d (%s) already loaded\n", | |
2054 | module_id, name); | |
2055 | out: | |
2056 | /* release fw, but base fw should be released by acpi driver */ | |
2057 | if (fw && module_id != SST_HSW_MODULE_BASE_FW) | |
2058 | release_firmware(fw); | |
2059 | ||
2060 | return ret; | |
2061 | } | |
2062 | ||
e8e79ede LH |
2063 | int sst_hsw_module_enable(struct sst_hsw *hsw, |
2064 | u32 module_id, u32 instance_id) | |
2065 | { | |
2066 | int ret; | |
2067 | u32 header = 0; | |
2068 | struct sst_hsw_ipc_module_config config; | |
2069 | struct sst_module *module; | |
2070 | struct sst_module_runtime *runtime; | |
2071 | struct device *dev = hsw->dev; | |
2072 | struct sst_dsp *dsp = hsw->dsp; | |
2073 | ||
2074 | if (!sst_hsw_is_module_loaded(hsw, module_id)) { | |
2075 | dev_dbg(dev, "module %d not loaded\n", module_id); | |
2076 | return 0; | |
2077 | } | |
2078 | ||
2079 | if (sst_hsw_is_module_active(hsw, module_id)) { | |
2080 | dev_info(dev, "module %d already enabled\n", module_id); | |
2081 | return 0; | |
2082 | } | |
2083 | ||
2084 | module = sst_module_get_from_id(dsp, module_id); | |
2085 | if (module == NULL) { | |
2086 | dev_err(dev, "module %d not valid\n", module_id); | |
2087 | return -ENXIO; | |
2088 | } | |
2089 | ||
2090 | runtime = sst_module_runtime_get_from_id(module, module_id); | |
2091 | if (runtime == NULL) { | |
2092 | dev_err(dev, "runtime %d not valid", module_id); | |
2093 | return -ENXIO; | |
2094 | } | |
2095 | ||
2096 | header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) | | |
2097 | IPC_MODULE_OPERATION(IPC_MODULE_ENABLE) | | |
2098 | IPC_MODULE_ID(module_id); | |
2099 | dev_dbg(dev, "module enable header: %x\n", header); | |
2100 | ||
2101 | config.map.module_entries_count = 1; | |
2102 | config.map.module_entries[0].module_id = module->id; | |
2103 | config.map.module_entries[0].entry_point = module->entry; | |
2104 | ||
2105 | config.persistent_mem.offset = | |
2106 | sst_dsp_get_offset(dsp, | |
2107 | runtime->persistent_offset, SST_MEM_DRAM); | |
2108 | config.persistent_mem.size = module->persistent_size; | |
2109 | ||
2110 | config.scratch_mem.offset = | |
2111 | sst_dsp_get_offset(dsp, | |
2112 | dsp->scratch_offset, SST_MEM_DRAM); | |
2113 | config.scratch_mem.size = module->scratch_size; | |
2114 | dev_dbg(dev, "mod %d enable p:%d @ %x, s:%d @ %x, ep: %x", | |
2115 | config.map.module_entries[0].module_id, | |
2116 | config.persistent_mem.size, | |
2117 | config.persistent_mem.offset, | |
2118 | config.scratch_mem.size, config.scratch_mem.offset, | |
2119 | config.map.module_entries[0].entry_point); | |
2120 | ||
2121 | ret = ipc_tx_message_wait(hsw, header, | |
2122 | &config, sizeof(config), NULL, 0); | |
2123 | if (ret < 0) | |
2124 | dev_err(dev, "ipc: module enable failed - %d\n", ret); | |
2125 | else | |
2126 | module->state = SST_MODULE_STATE_ACTIVE; | |
2127 | ||
2128 | return ret; | |
2129 | } | |
2130 | ||
2131 | int sst_hsw_module_disable(struct sst_hsw *hsw, | |
2132 | u32 module_id, u32 instance_id) | |
2133 | { | |
2134 | int ret; | |
2135 | u32 header; | |
2136 | struct sst_module *module; | |
2137 | struct device *dev = hsw->dev; | |
2138 | struct sst_dsp *dsp = hsw->dsp; | |
2139 | ||
2140 | if (!sst_hsw_is_module_loaded(hsw, module_id)) { | |
2141 | dev_dbg(dev, "module %d not loaded\n", module_id); | |
2142 | return 0; | |
2143 | } | |
2144 | ||
2145 | if (!sst_hsw_is_module_active(hsw, module_id)) { | |
2146 | dev_info(dev, "module %d already disabled\n", module_id); | |
2147 | return 0; | |
2148 | } | |
2149 | ||
2150 | module = sst_module_get_from_id(dsp, module_id); | |
2151 | if (module == NULL) { | |
2152 | dev_err(dev, "module %d not valid\n", module_id); | |
2153 | return -ENXIO; | |
2154 | } | |
2155 | ||
2156 | header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) | | |
2157 | IPC_MODULE_OPERATION(IPC_MODULE_DISABLE) | | |
2158 | IPC_MODULE_ID(module_id); | |
2159 | ||
2160 | ret = ipc_tx_message_wait(hsw, header, NULL, 0, NULL, 0); | |
2161 | if (ret < 0) | |
2162 | dev_err(dev, "module disable failed - %d\n", ret); | |
2163 | else | |
2164 | module->state = SST_MODULE_STATE_INITIALIZED; | |
2165 | ||
2166 | return ret; | |
2167 | } | |
2168 | ||
20189226 LH |
2169 | int sst_hsw_module_set_param(struct sst_hsw *hsw, |
2170 | u32 module_id, u32 instance_id, u32 parameter_id, | |
2171 | u32 param_size, char *param) | |
2172 | { | |
2173 | int ret; | |
2174 | unsigned char *data = NULL; | |
2175 | u32 header = 0; | |
2176 | u32 payload_size = 0, transfer_parameter_size = 0; | |
2177 | dma_addr_t dma_addr = 0; | |
2178 | struct sst_hsw_transfer_parameter *parameter; | |
2179 | struct device *dev = hsw->dev; | |
2180 | ||
2181 | header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) | | |
2182 | IPC_MODULE_OPERATION(IPC_MODULE_SET_PARAMETER) | | |
2183 | IPC_MODULE_ID(module_id); | |
2184 | dev_dbg(dev, "sst_hsw_module_set_param header=%x\n", header); | |
2185 | ||
2186 | payload_size = param_size + | |
2187 | sizeof(struct sst_hsw_transfer_parameter) - | |
2188 | sizeof(struct sst_hsw_transfer_list); | |
2189 | dev_dbg(dev, "parameter size : %d\n", param_size); | |
2190 | dev_dbg(dev, "payload size : %d\n", payload_size); | |
2191 | ||
2192 | if (payload_size <= SST_HSW_IPC_MAX_SHORT_PARAMETER_SIZE) { | |
2193 | /* short parameter, mailbox can contain data */ | |
2194 | dev_dbg(dev, "transfer parameter size : %d\n", | |
2195 | transfer_parameter_size); | |
2196 | ||
2197 | transfer_parameter_size = ALIGN(payload_size, 4); | |
2198 | dev_dbg(dev, "transfer parameter aligned size : %d\n", | |
2199 | transfer_parameter_size); | |
2200 | ||
2201 | parameter = kzalloc(transfer_parameter_size, GFP_KERNEL); | |
2202 | if (parameter == NULL) | |
2203 | return -ENOMEM; | |
2204 | ||
2205 | memcpy(parameter->data, param, param_size); | |
2206 | } else { | |
2207 | dev_warn(dev, "transfer parameter size too large!"); | |
2208 | return 0; | |
2209 | } | |
2210 | ||
2211 | parameter->parameter_id = parameter_id; | |
2212 | parameter->data_size = param_size; | |
2213 | ||
2214 | ret = ipc_tx_message_wait(hsw, header, | |
2215 | parameter, transfer_parameter_size , NULL, 0); | |
2216 | if (ret < 0) | |
2217 | dev_err(dev, "ipc: module set parameter failed - %d\n", ret); | |
2218 | ||
2219 | kfree(parameter); | |
2220 | ||
2221 | if (data) | |
2222 | dma_free_coherent(hsw->dsp->dma_dev, | |
2223 | param_size, (void *)data, dma_addr); | |
2224 | ||
2225 | return ret; | |
2226 | } | |
2227 | ||
a4b12990 MB |
2228 | static struct sst_dsp_device hsw_dev = { |
2229 | .thread = hsw_irq_thread, | |
2230 | .ops = &haswell_ops, | |
2231 | }; | |
2232 | ||
2233 | int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata) | |
2234 | { | |
2235 | struct sst_hsw_ipc_fw_version version; | |
2236 | struct sst_hsw *hsw; | |
a4b12990 MB |
2237 | int ret; |
2238 | ||
2239 | dev_dbg(dev, "initialising Audio DSP IPC\n"); | |
2240 | ||
2241 | hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL); | |
2242 | if (hsw == NULL) | |
2243 | return -ENOMEM; | |
2244 | ||
2245 | hsw->dev = dev; | |
2246 | INIT_LIST_HEAD(&hsw->stream_list); | |
2247 | INIT_LIST_HEAD(&hsw->tx_list); | |
2248 | INIT_LIST_HEAD(&hsw->rx_list); | |
2249 | INIT_LIST_HEAD(&hsw->empty_list); | |
2250 | init_waitqueue_head(&hsw->boot_wait); | |
2251 | init_waitqueue_head(&hsw->wait_txq); | |
2252 | ||
2253 | ret = msg_empty_list_init(hsw); | |
2254 | if (ret < 0) | |
9cf0e452 | 2255 | return -ENOMEM; |
a4b12990 MB |
2256 | |
2257 | /* start the IPC message thread */ | |
2258 | init_kthread_worker(&hsw->kworker); | |
2259 | hsw->tx_thread = kthread_run(kthread_worker_fn, | |
35386320 | 2260 | &hsw->kworker, "%s", |
a4b12990 MB |
2261 | dev_name(hsw->dev)); |
2262 | if (IS_ERR(hsw->tx_thread)) { | |
2263 | ret = PTR_ERR(hsw->tx_thread); | |
2264 | dev_err(hsw->dev, "error: failed to create message TX task\n"); | |
9cf0e452 | 2265 | goto err_free_msg; |
a4b12990 MB |
2266 | } |
2267 | init_kthread_work(&hsw->kwork, ipc_tx_msgs); | |
2268 | ||
2269 | hsw_dev.thread_context = hsw; | |
2270 | ||
2271 | /* init SST shim */ | |
2272 | hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata); | |
2273 | if (hsw->dsp == NULL) { | |
2274 | ret = -ENODEV; | |
9cf0e452 | 2275 | goto dsp_err; |
a4b12990 MB |
2276 | } |
2277 | ||
aed3c7b7 LG |
2278 | /* allocate DMA buffer for context storage */ |
2279 | hsw->dx_context = dma_alloc_coherent(hsw->dsp->dma_dev, | |
2280 | SST_HSW_DX_CONTEXT_SIZE, &hsw->dx_context_paddr, GFP_KERNEL); | |
2281 | if (hsw->dx_context == NULL) { | |
2282 | ret = -ENOMEM; | |
2283 | goto dma_err; | |
2284 | } | |
2285 | ||
a4b12990 MB |
2286 | /* keep the DSP in reset state for base FW loading */ |
2287 | sst_dsp_reset(hsw->dsp); | |
2288 | ||
9449d39b LH |
2289 | /* load base module and other modules in base firmware image */ |
2290 | ret = sst_hsw_module_load(hsw, SST_HSW_MODULE_BASE_FW, 0, "Base"); | |
2291 | if (ret < 0) | |
a4b12990 | 2292 | goto fw_err; |
a4b12990 | 2293 | |
8c43fc2f LH |
2294 | /* try to load module waves */ |
2295 | sst_hsw_module_load(hsw, SST_HSW_MODULE_WAVES, 0, "intel/IntcPP01.bin"); | |
2296 | ||
3fe0607a LH |
2297 | /* allocate scratch mem regions */ |
2298 | ret = sst_block_alloc_scratch(hsw->dsp); | |
2299 | if (ret < 0) | |
2300 | goto boot_err; | |
2301 | ||
a4b12990 MB |
2302 | /* wait for DSP boot completion */ |
2303 | sst_dsp_boot(hsw->dsp); | |
2304 | ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete, | |
2305 | msecs_to_jiffies(IPC_BOOT_MSECS)); | |
2306 | if (ret == 0) { | |
2307 | ret = -EIO; | |
b891f62f LG |
2308 | dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n", |
2309 | sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD), | |
2310 | sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX)); | |
a4b12990 MB |
2311 | goto boot_err; |
2312 | } | |
2313 | ||
9449d39b LH |
2314 | /* init module state after boot */ |
2315 | sst_hsw_init_module_state(hsw); | |
2316 | ||
a4b12990 MB |
2317 | /* get the FW version */ |
2318 | sst_hsw_fw_get_version(hsw, &version); | |
a4b12990 MB |
2319 | |
2320 | /* get the globalmixer */ | |
2321 | ret = sst_hsw_mixer_get_info(hsw); | |
2322 | if (ret < 0) { | |
2323 | dev_err(hsw->dev, "error: failed to get stream info\n"); | |
2324 | goto boot_err; | |
2325 | } | |
2326 | ||
2327 | pdata->dsp = hsw; | |
2328 | return 0; | |
2329 | ||
2330 | boot_err: | |
2331 | sst_dsp_reset(hsw->dsp); | |
9449d39b | 2332 | sst_fw_free_all(hsw->dsp); |
a4b12990 | 2333 | fw_err: |
aed3c7b7 LG |
2334 | dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE, |
2335 | hsw->dx_context, hsw->dx_context_paddr); | |
2336 | dma_err: | |
a4b12990 | 2337 | sst_dsp_free(hsw->dsp); |
9cf0e452 ID |
2338 | dsp_err: |
2339 | kthread_stop(hsw->tx_thread); | |
2340 | err_free_msg: | |
a4b12990 | 2341 | kfree(hsw->msg); |
9cf0e452 | 2342 | |
a4b12990 MB |
2343 | return ret; |
2344 | } | |
2345 | EXPORT_SYMBOL_GPL(sst_hsw_dsp_init); | |
2346 | ||
2347 | void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata) | |
2348 | { | |
2349 | struct sst_hsw *hsw = pdata->dsp; | |
2350 | ||
2351 | sst_dsp_reset(hsw->dsp); | |
2352 | sst_fw_free_all(hsw->dsp); | |
aed3c7b7 LG |
2353 | dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE, |
2354 | hsw->dx_context, hsw->dx_context_paddr); | |
a4b12990 | 2355 | sst_dsp_free(hsw->dsp); |
9cf0e452 | 2356 | kthread_stop(hsw->tx_thread); |
a4b12990 MB |
2357 | kfree(hsw->msg); |
2358 | } | |
2359 | EXPORT_SYMBOL_GPL(sst_hsw_dsp_free); |