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ASoC: Intel: Delete message when IPC timeout occurs
[deliverable/linux.git] / sound / soc / intel / sst-haswell-ipc.c
CommitLineData
a4b12990
MB		 1/*
2 * Intel SST Haswell/Broadwell IPC Support
3 *
4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/types.h>
18#include <linux/kernel.h>
19#include <linux/list.h>
20#include <linux/device.h>
21#include <linux/wait.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/export.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
a4b12990
MB		 28#include <linux/platform_device.h>
29#include <linux/kthread.h>
30#include <linux/firmware.h>
31#include <linux/dma-mapping.h>
32#include <linux/debugfs.h>
33
34#include "sst-haswell-ipc.h"
35#include "sst-dsp.h"
36#include "sst-dsp-priv.h"
37
38/* Global Message - Generic */
39#define IPC_GLB_TYPE_SHIFT 24
40#define IPC_GLB_TYPE_MASK (0x1f << IPC_GLB_TYPE_SHIFT)
41#define IPC_GLB_TYPE(x) (x << IPC_GLB_TYPE_SHIFT)
42
43/* Global Message - Reply */
44#define IPC_GLB_REPLY_SHIFT 0
45#define IPC_GLB_REPLY_MASK (0x1f << IPC_GLB_REPLY_SHIFT)
46#define IPC_GLB_REPLY_TYPE(x) (x << IPC_GLB_REPLY_TYPE_SHIFT)
47
48/* Stream Message - Generic */
49#define IPC_STR_TYPE_SHIFT 20
50#define IPC_STR_TYPE_MASK (0xf << IPC_STR_TYPE_SHIFT)
51#define IPC_STR_TYPE(x) (x << IPC_STR_TYPE_SHIFT)
52#define IPC_STR_ID_SHIFT 16
53#define IPC_STR_ID_MASK (0xf << IPC_STR_ID_SHIFT)
54#define IPC_STR_ID(x) (x << IPC_STR_ID_SHIFT)
55
56/* Stream Message - Reply */
57#define IPC_STR_REPLY_SHIFT 0
58#define IPC_STR_REPLY_MASK (0x1f << IPC_STR_REPLY_SHIFT)
59
60/* Stream Stage Message - Generic */
61#define IPC_STG_TYPE_SHIFT 12
62#define IPC_STG_TYPE_MASK (0xf << IPC_STG_TYPE_SHIFT)
63#define IPC_STG_TYPE(x) (x << IPC_STG_TYPE_SHIFT)
64#define IPC_STG_ID_SHIFT 10
65#define IPC_STG_ID_MASK (0x3 << IPC_STG_ID_SHIFT)
66#define IPC_STG_ID(x) (x << IPC_STG_ID_SHIFT)
67
68/* Stream Stage Message - Reply */
69#define IPC_STG_REPLY_SHIFT 0
70#define IPC_STG_REPLY_MASK (0x1f << IPC_STG_REPLY_SHIFT)
71
72/* Debug Log Message - Generic */
73#define IPC_LOG_OP_SHIFT 20
74#define IPC_LOG_OP_MASK (0xf << IPC_LOG_OP_SHIFT)
75#define IPC_LOG_OP_TYPE(x) (x << IPC_LOG_OP_SHIFT)
76#define IPC_LOG_ID_SHIFT 16
77#define IPC_LOG_ID_MASK (0xf << IPC_LOG_ID_SHIFT)
78#define IPC_LOG_ID(x) (x << IPC_LOG_ID_SHIFT)
79
80/* IPC message timeout (msecs) */
81#define IPC_TIMEOUT_MSECS 300
82#define IPC_BOOT_MSECS 200
83#define IPC_MSG_WAIT 0
84#define IPC_MSG_NOWAIT 1
85
86/* Firmware Ready Message */
87#define IPC_FW_READY (0x1 << 29)
88#define IPC_STATUS_MASK (0x3 << 30)
89
90#define IPC_EMPTY_LIST_SIZE 8
91#define IPC_MAX_STREAMS 4
92
93/* Mailbox */
94#define IPC_MAX_MAILBOX_BYTES 256
95
96/* Global Message - Types and Replies */
97enum ipc_glb_type {
98 IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
99 IPC_GLB_PERFORMANCE_MONITOR = 1, /* Performance monitoring actions */
100 IPC_GLB_ALLOCATE_STREAM = 3, /* Request to allocate new stream */
101 IPC_GLB_FREE_STREAM = 4, /* Request to free stream */
102 IPC_GLB_GET_FW_CAPABILITIES = 5, /* Retrieves firmware capabilities */
103 IPC_GLB_STREAM_MESSAGE = 6, /* Message directed to stream or its stages */
104 /* Request to store firmware context during D0->D3 transition */
105 IPC_GLB_REQUEST_DUMP = 7,
106 /* Request to restore firmware context during D3->D0 transition */
107 IPC_GLB_RESTORE_CONTEXT = 8,
108 IPC_GLB_GET_DEVICE_FORMATS = 9, /* Set device format */
109 IPC_GLB_SET_DEVICE_FORMATS = 10, /* Get device format */
110 IPC_GLB_SHORT_REPLY = 11,
111 IPC_GLB_ENTER_DX_STATE = 12,
112 IPC_GLB_GET_MIXER_STREAM_INFO = 13, /* Request mixer stream params */
113 IPC_GLB_DEBUG_LOG_MESSAGE = 14, /* Message to or from the debug logger. */
114 IPC_GLB_REQUEST_TRANSFER = 16, /* < Request Transfer for host */
115 IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17, /* Maximum message number */
116};
117
118enum ipc_glb_reply {
119 IPC_GLB_REPLY_SUCCESS = 0, /* The operation was successful. */
120 IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1, /* Invalid parameter was passed. */
121 IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */
122 IPC_GLB_REPLY_OUT_OF_RESOURCES = 3, /* No resources to satisfy the request. */
123 IPC_GLB_REPLY_BUSY = 4, /* The system or resource is busy. */
124 IPC_GLB_REPLY_PENDING = 5, /* The action was scheduled for processing. */
125 IPC_GLB_REPLY_FAILURE = 6, /* Critical error happened. */
126 IPC_GLB_REPLY_INVALID_REQUEST = 7, /* Request can not be completed. */
127 IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8, /* Processing stage was uninitialized. */
128 IPC_GLB_REPLY_NOT_FOUND = 9, /* Required resource can not be found. */
129 IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10, /* Source was not started. */
130};
131
132/* Stream Message - Types */
133enum ipc_str_operation {
134 IPC_STR_RESET = 0,
135 IPC_STR_PAUSE = 1,
136 IPC_STR_RESUME = 2,
137 IPC_STR_STAGE_MESSAGE = 3,
138 IPC_STR_NOTIFICATION = 4,
139 IPC_STR_MAX_MESSAGE
140};
141
142/* Stream Stage Message Types */
143enum ipc_stg_operation {
144 IPC_STG_GET_VOLUME = 0,
145 IPC_STG_SET_VOLUME,
146 IPC_STG_SET_WRITE_POSITION,
147 IPC_STG_SET_FX_ENABLE,
148 IPC_STG_SET_FX_DISABLE,
149 IPC_STG_SET_FX_GET_PARAM,
150 IPC_STG_SET_FX_SET_PARAM,
151 IPC_STG_SET_FX_GET_INFO,
152 IPC_STG_MUTE_LOOPBACK,
153 IPC_STG_MAX_MESSAGE
154};
155
156/* Stream Stage Message Types For Notification*/
157enum ipc_stg_operation_notify {
158 IPC_POSITION_CHANGED = 0,
159 IPC_STG_GLITCH,
160 IPC_STG_MAX_NOTIFY
161};
162
163enum ipc_glitch_type {
164 IPC_GLITCH_UNDERRUN = 1,
165 IPC_GLITCH_DECODER_ERROR,
166 IPC_GLITCH_DOUBLED_WRITE_POS,
167 IPC_GLITCH_MAX
168};
169
170/* Debug Control */
171enum ipc_debug_operation {
172 IPC_DEBUG_ENABLE_LOG = 0,
173 IPC_DEBUG_DISABLE_LOG = 1,
174 IPC_DEBUG_REQUEST_LOG_DUMP = 2,
175 IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
176 IPC_DEBUG_MAX_DEBUG_LOG
177};
178
179/* Firmware Ready */
180struct sst_hsw_ipc_fw_ready {
181 u32 inbox_offset;
182 u32 outbox_offset;
183 u32 inbox_size;
184 u32 outbox_size;
185 u32 fw_info_size;
249adddb 186 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
a4b12990
MB		 187} __attribute__((packed));
188
189struct ipc_message {
190 struct list_head list;
191 u32 header;
192
193 /* direction wrt host CPU */
194 char tx_data[IPC_MAX_MAILBOX_BYTES];
195 size_t tx_size;
196 char rx_data[IPC_MAX_MAILBOX_BYTES];
197 size_t rx_size;
198
199 wait_queue_head_t waitq;
200 bool pending;
201 bool complete;
202 bool wait;
203 int errno;
204};
205
206struct sst_hsw_stream;
207struct sst_hsw;
208
209/* Stream infomation */
210struct sst_hsw_stream {
211 /* configuration */
212 struct sst_hsw_ipc_stream_alloc_req request;
213 struct sst_hsw_ipc_stream_alloc_reply reply;
214 struct sst_hsw_ipc_stream_free_req free_req;
215
216 /* Mixer info */
217 u32 mute_volume[SST_HSW_NO_CHANNELS];
218 u32 mute[SST_HSW_NO_CHANNELS];
219
220 /* runtime info */
221 struct sst_hsw *hsw;
222 int host_id;
223 bool commited;
224 bool running;
225
226 /* Notification work */
227 struct work_struct notify_work;
228 u32 header;
229
230 /* Position info from DSP */
231 struct sst_hsw_ipc_stream_set_position wpos;
232 struct sst_hsw_ipc_stream_get_position rpos;
233 struct sst_hsw_ipc_stream_glitch_position glitch;
234
235 /* Volume info */
236 struct sst_hsw_ipc_volume_req vol_req;
237
238 /* driver callback */
239 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
240 void *pdata;
241
242 struct list_head node;
243};
244
245/* FW log ring information */
246struct sst_hsw_log_stream {
247 dma_addr_t dma_addr;
248 unsigned char *dma_area;
249 unsigned char *ring_descr;
250 int pages;
251 int size;
252
253 /* Notification work */
254 struct work_struct notify_work;
255 wait_queue_head_t readers_wait_q;
256 struct mutex rw_mutex;
257
258 u32 last_pos;
259 u32 curr_pos;
260 u32 reader_pos;
261
262 /* fw log config */
263 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
264
265 struct sst_hsw *hsw;
266};
267
268/* SST Haswell IPC data */
269struct sst_hsw {
270 struct device *dev;
271 struct sst_dsp *dsp;
272 struct platform_device *pdev_pcm;
273
274 /* FW config */
275 struct sst_hsw_ipc_fw_ready fw_ready;
276 struct sst_hsw_ipc_fw_version version;
277 struct sst_module *scratch;
278 bool fw_done;
279
280 /* stream */
281 struct list_head stream_list;
282
283 /* global mixer */
284 struct sst_hsw_ipc_stream_info_reply mixer_info;
285 enum sst_hsw_volume_curve curve_type;
286 u32 curve_duration;
287 u32 mute[SST_HSW_NO_CHANNELS];
288 u32 mute_volume[SST_HSW_NO_CHANNELS];
289
290 /* DX */
291 struct sst_hsw_ipc_dx_reply dx;
292
293 /* boot */
294 wait_queue_head_t boot_wait;
295 bool boot_complete;
296 bool shutdown;
297
298 /* IPC messaging */
299 struct list_head tx_list;
300 struct list_head rx_list;
301 struct list_head empty_list;
302 wait_queue_head_t wait_txq;
303 struct task_struct *tx_thread;
304 struct kthread_worker kworker;
305 struct kthread_work kwork;
306 bool pending;
307 struct ipc_message *msg;
308
309 /* FW log stream */
310 struct sst_hsw_log_stream log_stream;
311};
312
313#define CREATE_TRACE_POINTS
314#include <trace/events/hswadsp.h>
315
316static inline u32 msg_get_global_type(u32 msg)
317{
318 return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
319}
320
321static inline u32 msg_get_global_reply(u32 msg)
322{
323 return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
324}
325
326static inline u32 msg_get_stream_type(u32 msg)
327{
328 return (msg & IPC_STR_TYPE_MASK) >> IPC_STR_TYPE_SHIFT;
329}
330
331static inline u32 msg_get_stage_type(u32 msg)
332{
333 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
334}
335
336static inline u32 msg_set_stage_type(u32 msg, u32 type)
337{
338 return (msg & ~IPC_STG_TYPE_MASK) +
339 (type << IPC_STG_TYPE_SHIFT);
340}
341
342static inline u32 msg_get_stream_id(u32 msg)
343{
344 return (msg & IPC_STR_ID_MASK) >> IPC_STR_ID_SHIFT;
345}
346
347static inline u32 msg_get_notify_reason(u32 msg)
348{
349 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
350}
351
352u32 create_channel_map(enum sst_hsw_channel_config config)
353{
354 switch (config) {
355 case SST_HSW_CHANNEL_CONFIG_MONO:
356 return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
357 case SST_HSW_CHANNEL_CONFIG_STEREO:
358 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
359 | (SST_HSW_CHANNEL_RIGHT << 4));
360 case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
361 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
362 | (SST_HSW_CHANNEL_RIGHT << 4)
363 | (SST_HSW_CHANNEL_LFE << 8 ));
364 case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
365 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
366 | (SST_HSW_CHANNEL_CENTER << 4)
367 | (SST_HSW_CHANNEL_RIGHT << 8));
368 case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
369 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
370 | (SST_HSW_CHANNEL_CENTER << 4)
371 | (SST_HSW_CHANNEL_RIGHT << 8)
372 | (SST_HSW_CHANNEL_LFE << 12));
373 case SST_HSW_CHANNEL_CONFIG_QUATRO:
374 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
375 | (SST_HSW_CHANNEL_RIGHT << 4)
376 | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
377 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
378 case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
379 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
380 | (SST_HSW_CHANNEL_CENTER << 4)
381 | (SST_HSW_CHANNEL_RIGHT << 8)
382 | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
383 case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
384 return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
385 | (SST_HSW_CHANNEL_CENTER << 4)
386 | (SST_HSW_CHANNEL_RIGHT << 8)
387 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
388 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
389 case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
390 return (0xFF000000 | SST_HSW_CHANNEL_CENTER
391 | (SST_HSW_CHANNEL_LEFT << 4)
392 | (SST_HSW_CHANNEL_RIGHT << 8)
393 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
394 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
395 | (SST_HSW_CHANNEL_LFE << 20));
396 case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
397 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
398 | (SST_HSW_CHANNEL_LEFT << 4));
399 default:
400 return 0xFFFFFFFF;
401 }
402}
403
404static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
405 int stream_id)
406{
407 struct sst_hsw_stream *stream;
408
409 list_for_each_entry(stream, &hsw->stream_list, node) {
410 if (stream->reply.stream_hw_id == stream_id)
411 return stream;
412 }
413
414 return NULL;
415}
416
417static void ipc_shim_dbg(struct sst_hsw *hsw, const char *text)
418{
419 struct sst_dsp *sst = hsw->dsp;
420 u32 isr, ipcd, imrx, ipcx;
421
422 ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
423 isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
424 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
425 imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
426
427 dev_err(hsw->dev, "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
428 text, ipcx, isr, ipcd, imrx);
429}
430
431/* locks held by caller */
432static struct ipc_message *msg_get_empty(struct sst_hsw *hsw)
433{
434 struct ipc_message *msg = NULL;
435
436 if (!list_empty(&hsw->empty_list)) {
437 msg = list_first_entry(&hsw->empty_list, struct ipc_message,
438 list);
439 list_del(&msg->list);
440 }
441
442 return msg;
443}
444
445static void ipc_tx_msgs(struct kthread_work *work)
446{
447 struct sst_hsw *hsw =
448 container_of(work, struct sst_hsw, kwork);
449 struct ipc_message *msg;
450 unsigned long flags;
451 u32 ipcx;
452
453 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
454
455 if (list_empty(&hsw->tx_list) || hsw->pending) {
456 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
457 return;
458 }
459
460 /* if the DSP is busy we will TX messages after IRQ */
461 ipcx = sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX);
462 if (ipcx & SST_IPCX_BUSY) {
463 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
464 return;
465 }
466
467 msg = list_first_entry(&hsw->tx_list, struct ipc_message, list);
468
469 list_move(&msg->list, &hsw->rx_list);
470
471 /* send the message */
472 sst_dsp_outbox_write(hsw->dsp, msg->tx_data, msg->tx_size);
473 sst_dsp_ipc_msg_tx(hsw->dsp, msg->header | SST_IPCX_BUSY);
474
475 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
476}
477
478/* locks held by caller */
479static void tx_msg_reply_complete(struct sst_hsw *hsw, struct ipc_message *msg)
480{
481 msg->complete = true;
482 trace_ipc_reply("completed", msg->header);
483
484 if (!msg->wait)
485 list_add_tail(&msg->list, &hsw->empty_list);
486 else
487 wake_up(&msg->waitq);
488}
489
490static int tx_wait_done(struct sst_hsw *hsw, struct ipc_message *msg,
491 void *rx_data)
492{
493 unsigned long flags;
494 int ret;
495
496 /* wait for DSP completion (in all cases atm inc pending) */
497 ret = wait_event_timeout(msg->waitq, msg->complete,
498 msecs_to_jiffies(IPC_TIMEOUT_MSECS));
499
500 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
501 if (ret == 0) {
502 ipc_shim_dbg(hsw, "message timeout");
503
504 trace_ipc_error("error message timeout for", msg->header);
97cfc751 505 list_del(&msg->list);
a4b12990
MB		 506 ret = -ETIMEDOUT;
507 } else {
508
509 /* copy the data returned from DSP */
510 if (msg->rx_size)
511 memcpy(rx_data, msg->rx_data, msg->rx_size);
512 ret = msg->errno;
513 }
514
515 list_add_tail(&msg->list, &hsw->empty_list);
516 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
517 return ret;
518}
519
520static int ipc_tx_message(struct sst_hsw *hsw, u32 header, void *tx_data,
521 size_t tx_bytes, void *rx_data, size_t rx_bytes, int wait)
522{
523 struct ipc_message *msg;
524 unsigned long flags;
525
526 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
527
528 msg = msg_get_empty(hsw);
529 if (msg == NULL) {
530 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
531 return -EBUSY;
532 }
533
534 if (tx_bytes)
535 memcpy(msg->tx_data, tx_data, tx_bytes);
536
537 msg->header = header;
538 msg->tx_size = tx_bytes;
539 msg->rx_size = rx_bytes;
540 msg->wait = wait;
541 msg->errno = 0;
542 msg->pending = false;
543 msg->complete = false;
544
545 list_add_tail(&msg->list, &hsw->tx_list);
546 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
547
548 queue_kthread_work(&hsw->kworker, &hsw->kwork);
549
550 if (wait)
551 return tx_wait_done(hsw, msg, rx_data);
552 else
553 return 0;
554}
555
556static inline int ipc_tx_message_wait(struct sst_hsw *hsw, u32 header,
557 void *tx_data, size_t tx_bytes, void *rx_data, size_t rx_bytes)
558{
559 return ipc_tx_message(hsw, header, tx_data, tx_bytes, rx_data,
560 rx_bytes, 1);
561}
562
563static inline int ipc_tx_message_nowait(struct sst_hsw *hsw, u32 header,
564 void *tx_data, size_t tx_bytes)
565{
566 return ipc_tx_message(hsw, header, tx_data, tx_bytes, NULL, 0, 0);
567}
568
569static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
570{
571 struct sst_hsw_ipc_fw_ready fw_ready;
572 u32 offset;
249adddb
JY		 573 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
574 char *tmp[5], *pinfo;
575 int i = 0;
a4b12990
MB		 576
577 offset = (header & 0x1FFFFFFF) << 3;
578
579 dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
580 header, offset);
581
582 /* copy data from the DSP FW ready offset */
583 sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
584
585 sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
586 fw_ready.inbox_size, fw_ready.outbox_offset,
587 fw_ready.outbox_size);
588
589 hsw->boot_complete = true;
590 wake_up(&hsw->boot_wait);
591
592 dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
593 fw_ready.inbox_offset, fw_ready.inbox_size);
594 dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
595 fw_ready.outbox_offset, fw_ready.outbox_size);
249adddb
JY		 596 if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) {
597 fw_ready.fw_info[fw_ready.fw_info_size] = 0;
598 dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info);
599
600 /* log the FW version info got from the mailbox here. */
601 memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size);
602 pinfo = &fw_info[0];
603 for (i = 0; i < sizeof(tmp) / sizeof(char *); i++)
604 tmp[i] = strsep(&pinfo, " ");
605 dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - "
606 "version: %s.%s, build %s, source commit id: %s\n",
607 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]);
608 }
a4b12990
MB		 609}
610
611static void hsw_notification_work(struct work_struct *work)
612{
613 struct sst_hsw_stream *stream = container_of(work,
614 struct sst_hsw_stream, notify_work);
615 struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
616 struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
617 struct sst_hsw *hsw = stream->hsw;
618 u32 reason;
619
620 reason = msg_get_notify_reason(stream->header);
621
622 switch (reason) {
623 case IPC_STG_GLITCH:
624 trace_ipc_notification("DSP stream under/overrun",
625 stream->reply.stream_hw_id);
626 sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
627
628 dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
629 glitch->glitch_type, glitch->present_pos,
630 glitch->write_pos);
631 break;
632
633 case IPC_POSITION_CHANGED:
634 trace_ipc_notification("DSP stream position changed for",
635 stream->reply.stream_hw_id);
7897ab78 636 sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
a4b12990
MB		 637
638 if (stream->notify_position)
639 stream->notify_position(stream, stream->pdata);
640
641 break;
642 default:
643 dev_err(hsw->dev, "error: unknown notification 0x%x\n",
644 stream->header);
645 break;
646 }
647
648 /* tell DSP that notification has been handled */
649 sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IPCD,
650 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
651
652 /* unmask busy interrupt */
653 sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
654}
655
656static struct ipc_message *reply_find_msg(struct sst_hsw *hsw, u32 header)
657{
658 struct ipc_message *msg;
659
660 /* clear reply bits & status bits */
661 header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
662
663 if (list_empty(&hsw->rx_list)) {
664 dev_err(hsw->dev, "error: rx list empty but received 0x%x\n",
665 header);
666 return NULL;
667 }
668
669 list_for_each_entry(msg, &hsw->rx_list, list) {
670 if (msg->header == header)
671 return msg;
672 }
673
674 return NULL;
675}
676
677static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
678{
679 struct sst_hsw_stream *stream;
680 u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
681 u32 stream_id = msg_get_stream_id(header);
682 u32 stream_msg = msg_get_stream_type(header);
683
684 stream = get_stream_by_id(hsw, stream_id);
685 if (stream == NULL)
686 return;
687
688 switch (stream_msg) {
689 case IPC_STR_STAGE_MESSAGE:
690 case IPC_STR_NOTIFICATION:
81552612 691 break;
a4b12990 692 case IPC_STR_RESET:
81552612 693 trace_ipc_notification("stream reset", stream->reply.stream_hw_id);
a4b12990
MB		 694 break;
695 case IPC_STR_PAUSE:
696 stream->running = false;
697 trace_ipc_notification("stream paused",
698 stream->reply.stream_hw_id);
699 break;
700 case IPC_STR_RESUME:
701 stream->running = true;
702 trace_ipc_notification("stream running",
703 stream->reply.stream_hw_id);
704 break;
705 }
706}
707
708static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
709{
710 struct ipc_message *msg;
711 u32 reply = msg_get_global_reply(header);
712
713 trace_ipc_reply("processing -->", header);
714
715 msg = reply_find_msg(hsw, header);
716 if (msg == NULL) {
717 trace_ipc_error("error: can't find message header", header);
718 return -EIO;
719 }
720
721 /* first process the header */
722 switch (reply) {
723 case IPC_GLB_REPLY_PENDING:
724 trace_ipc_pending_reply("received", header);
725 msg->pending = true;
726 hsw->pending = true;
727 return 1;
728 case IPC_GLB_REPLY_SUCCESS:
729 if (msg->pending) {
730 trace_ipc_pending_reply("completed", header);
731 sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
732 msg->rx_size);
733 hsw->pending = false;
734 } else {
735 /* copy data from the DSP */
736 sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
737 msg->rx_size);
738 }
739 break;
740 /* these will be rare - but useful for debug */
741 case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
742 trace_ipc_error("error: unknown message type", header);
743 msg->errno = -EBADMSG;
744 break;
745 case IPC_GLB_REPLY_OUT_OF_RESOURCES:
746 trace_ipc_error("error: out of resources", header);
747 msg->errno = -ENOMEM;
748 break;
749 case IPC_GLB_REPLY_BUSY:
750 trace_ipc_error("error: reply busy", header);
751 msg->errno = -EBUSY;
752 break;
753 case IPC_GLB_REPLY_FAILURE:
754 trace_ipc_error("error: reply failure", header);
755 msg->errno = -EINVAL;
756 break;
757 case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
758 trace_ipc_error("error: stage uninitialized", header);
759 msg->errno = -EINVAL;
760 break;
761 case IPC_GLB_REPLY_NOT_FOUND:
762 trace_ipc_error("error: reply not found", header);
763 msg->errno = -EINVAL;
764 break;
765 case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
766 trace_ipc_error("error: source not started", header);
767 msg->errno = -EINVAL;
768 break;
769 case IPC_GLB_REPLY_INVALID_REQUEST:
770 trace_ipc_error("error: invalid request", header);
771 msg->errno = -EINVAL;
772 break;
773 case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
774 trace_ipc_error("error: invalid parameter", header);
775 msg->errno = -EINVAL;
776 break;
777 default:
778 trace_ipc_error("error: unknown reply", header);
779 msg->errno = -EINVAL;
780 break;
781 }
782
783 /* update any stream states */
784 hsw_stream_update(hsw, msg);
785
786 /* wake up and return the error if we have waiters on this message ? */
787 list_del(&msg->list);
788 tx_msg_reply_complete(hsw, msg);
789
790 return 1;
791}
792
793static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
794{
795 u32 stream_msg, stream_id, stage_type;
796 struct sst_hsw_stream *stream;
797 int handled = 0;
798
799 stream_msg = msg_get_stream_type(header);
800 stream_id = msg_get_stream_id(header);
801 stage_type = msg_get_stage_type(header);
802
803 stream = get_stream_by_id(hsw, stream_id);
804 if (stream == NULL)
805 return handled;
806
807 stream->header = header;
808
809 switch (stream_msg) {
810 case IPC_STR_STAGE_MESSAGE:
811 dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
812 header);
813 break;
814 case IPC_STR_NOTIFICATION:
815 schedule_work(&stream->notify_work);
816 break;
817 default:
818 /* handle pending message complete request */
819 handled = hsw_process_reply(hsw, header);
820 break;
821 }
822
823 return handled;
824}
825
826static int hsw_log_message(struct sst_hsw *hsw, u32 header)
827{
828 u32 operation = (header & IPC_LOG_OP_MASK) >> IPC_LOG_OP_SHIFT;
829 struct sst_hsw_log_stream *stream = &hsw->log_stream;
830 int ret = 1;
831
832 if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
833 dev_err(hsw->dev,
834 "error: log msg not implemented 0x%8.8x\n", header);
835 return 0;
836 }
837
838 mutex_lock(&stream->rw_mutex);
839 stream->last_pos = stream->curr_pos;
840 sst_dsp_inbox_read(
841 hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
842 mutex_unlock(&stream->rw_mutex);
843
844 schedule_work(&stream->notify_work);
845
846 return ret;
847}
848
849static int hsw_process_notification(struct sst_hsw *hsw)
850{
851 struct sst_dsp *sst = hsw->dsp;
852 u32 type, header;
853 int handled = 1;
854
855 header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
856 type = msg_get_global_type(header);
857
858 trace_ipc_request("processing -->", header);
859
860 /* FW Ready is a special case */
861 if (!hsw->boot_complete && header & IPC_FW_READY) {
862 hsw_fw_ready(hsw, header);
863 return handled;
864 }
865
866 switch (type) {
867 case IPC_GLB_GET_FW_VERSION:
868 case IPC_GLB_ALLOCATE_STREAM:
869 case IPC_GLB_FREE_STREAM:
870 case IPC_GLB_GET_FW_CAPABILITIES:
871 case IPC_GLB_REQUEST_DUMP:
872 case IPC_GLB_GET_DEVICE_FORMATS:
873 case IPC_GLB_SET_DEVICE_FORMATS:
874 case IPC_GLB_ENTER_DX_STATE:
875 case IPC_GLB_GET_MIXER_STREAM_INFO:
876 case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
877 case IPC_GLB_RESTORE_CONTEXT:
878 case IPC_GLB_SHORT_REPLY:
879 dev_err(hsw->dev, "error: message type %d header 0x%x\n",
880 type, header);
881 break;
882 case IPC_GLB_STREAM_MESSAGE:
883 handled = hsw_stream_message(hsw, header);
884 break;
885 case IPC_GLB_DEBUG_LOG_MESSAGE:
886 handled = hsw_log_message(hsw, header);
887 break;
888 default:
889 dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
890 type, header);
891 break;
892 }
893
894 return handled;
895}
896
897static irqreturn_t hsw_irq_thread(int irq, void *context)
898{
899 struct sst_dsp *sst = (struct sst_dsp *) context;
900 struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
901 u32 ipcx, ipcd;
902 int handled;
903 unsigned long flags;
904
905 spin_lock_irqsave(&sst->spinlock, flags);
906
907 ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
908 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
909
910 /* reply message from DSP */
911 if (ipcx & SST_IPCX_DONE) {
912
913 /* Handle Immediate reply from DSP Core */
914 handled = hsw_process_reply(hsw, ipcx);
915
916 if (handled > 0) {
917 /* clear DONE bit - tell DSP we have completed */
918 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
919 SST_IPCX_DONE, 0);
920
921 /* unmask Done interrupt */
922 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
923 SST_IMRX_DONE, 0);
924 }
925 }
926
927 /* new message from DSP */
928 if (ipcd & SST_IPCD_BUSY) {
929
930 /* Handle Notification and Delayed reply from DSP Core */
931 handled = hsw_process_notification(hsw);
932
933 /* clear BUSY bit and set DONE bit - accept new messages */
934 if (handled > 0) {
935 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
936 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
937
938 /* unmask busy interrupt */
939 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
940 SST_IMRX_BUSY, 0);
941 }
942 }
943
944 spin_unlock_irqrestore(&sst->spinlock, flags);
945
946 /* continue to send any remaining messages... */
947 queue_kthread_work(&hsw->kworker, &hsw->kwork);
948
949 return IRQ_HANDLED;
950}
951
952int sst_hsw_fw_get_version(struct sst_hsw *hsw,
953 struct sst_hsw_ipc_fw_version *version)
954{
955 int ret;
956
957 ret = ipc_tx_message_wait(hsw, IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
958 NULL, 0, version, sizeof(*version));
959 if (ret < 0)
960 dev_err(hsw->dev, "error: get version failed\n");
961
962 return ret;
963}
964
965/* Mixer Controls */
966int sst_hsw_stream_mute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
967 u32 stage_id, u32 channel)
968{
969 int ret;
970
971 ret = sst_hsw_stream_get_volume(hsw, stream, stage_id, channel,
972 &stream->mute_volume[channel]);
973 if (ret < 0)
974 return ret;
975
976 ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel, 0);
977 if (ret < 0) {
978 dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
979 stream->reply.stream_hw_id, channel);
980 return ret;
981 }
982
983 stream->mute[channel] = 1;
984 return 0;
985}
986
987int sst_hsw_stream_unmute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
988 u32 stage_id, u32 channel)
989
990{
991 int ret;
992
993 stream->mute[channel] = 0;
994 ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel,
995 stream->mute_volume[channel]);
996 if (ret < 0) {
997 dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
998 stream->reply.stream_hw_id, channel);
999 return ret;
1000 }
1001
1002 return 0;
1003}
1004
1005int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1006 u32 stage_id, u32 channel, u32 *volume)
1007{
1008 if (channel > 1)
1009 return -EINVAL;
1010
1011 sst_dsp_read(hsw->dsp, volume,
bf657d24
CE		 1012 stream->reply.volume_register_address[channel],
1013 sizeof(*volume));
a4b12990
MB		 1014
1015 return 0;
1016}
1017
1018int sst_hsw_stream_set_volume_curve(struct sst_hsw *hsw,
1019 struct sst_hsw_stream *stream, u64 curve_duration,
1020 enum sst_hsw_volume_curve curve)
1021{
1022 /* curve duration in steps of 100ns */
1023 stream->vol_req.curve_duration = curve_duration;
1024 stream->vol_req.curve_type = curve;
1025
1026 return 0;
1027}
1028
1029/* stream volume */
1030int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
1031 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
1032{
1033 struct sst_hsw_ipc_volume_req *req;
1034 u32 header;
1035 int ret;
1036
1037 trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
1038
1039 if (channel > 1)
1040 return -EINVAL;
1041
1042 if (stream->mute[channel]) {
1043 stream->mute_volume[channel] = volume;
1044 return 0;
1045 }
1046
1047 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1048 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1049 header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
1050 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
1051 header |= (stage_id << IPC_STG_ID_SHIFT);
1052
1053 req = &stream->vol_req;
1054 req->channel = channel;
1055 req->target_volume = volume;
1056
1057 ret = ipc_tx_message_wait(hsw, header, req, sizeof(*req), NULL, 0);
1058 if (ret < 0) {
1059 dev_err(hsw->dev, "error: set stream volume failed\n");
1060 return ret;
1061 }
1062
1063 return 0;
1064}
1065
1066int sst_hsw_mixer_mute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
1067{
1068 int ret;
1069
1070 ret = sst_hsw_mixer_get_volume(hsw, stage_id, channel,
1071 &hsw->mute_volume[channel]);
1072 if (ret < 0)
1073 return ret;
1074
1075 ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel, 0);
1076 if (ret < 0) {
1077 dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
1078 channel);
1079 return ret;
1080 }
1081
1082 hsw->mute[channel] = 1;
1083 return 0;
1084}
1085
1086int sst_hsw_mixer_unmute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
1087{
1088 int ret;
1089
1090 ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel,
1091 hsw->mixer_info.volume_register_address[channel]);
1092 if (ret < 0) {
1093 dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
1094 channel);
1095 return ret;
1096 }
1097
1098 hsw->mute[channel] = 0;
1099 return 0;
1100}
1101
1102int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
1103 u32 *volume)
1104{
1105 if (channel > 1)
1106 return -EINVAL;
1107
1108 sst_dsp_read(hsw->dsp, volume,
1109 hsw->mixer_info.volume_register_address[channel],
1110 sizeof(*volume));
1111
1112 return 0;
1113}
1114
1115int sst_hsw_mixer_set_volume_curve(struct sst_hsw *hsw,
1116 u64 curve_duration, enum sst_hsw_volume_curve curve)
1117{
1118 /* curve duration in steps of 100ns */
1119 hsw->curve_duration = curve_duration;
1120 hsw->curve_type = curve;
1121
1122 return 0;
1123}
1124
1125/* global mixer volume */
1126int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
1127 u32 volume)
1128{
1129 struct sst_hsw_ipc_volume_req req;
1130 u32 header;
1131 int ret;
1132
1133 trace_ipc_request("set mixer volume", volume);
1134
1135 /* set both at same time ? */
1136 if (channel == 2) {
1137 if (hsw->mute[0] && hsw->mute[1]) {
1138 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
1139 return 0;
1140 } else if (hsw->mute[0])
1141 req.channel = 1;
1142 else if (hsw->mute[1])
1143 req.channel = 0;
1144 else
1145 req.channel = 0xffffffff;
1146 } else {
1147 /* set only 1 channel */
1148 if (hsw->mute[channel]) {
1149 hsw->mute_volume[channel] = volume;
1150 return 0;
1151 }
1152 req.channel = channel;
1153 }
1154
1155 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1156 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1157 header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
1158 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
1159 header |= (stage_id << IPC_STG_ID_SHIFT);
1160
1161 req.curve_duration = hsw->curve_duration;
1162 req.curve_type = hsw->curve_type;
1163 req.target_volume = volume;
1164
1165 ret = ipc_tx_message_wait(hsw, header, &req, sizeof(req), NULL, 0);
1166 if (ret < 0) {
1167 dev_err(hsw->dev, "error: set mixer volume failed\n");
1168 return ret;
1169 }
1170
1171 return 0;
1172}
1173
1174/* Stream API */
1175struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
1176 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
1177 void *data)
1178{
1179 struct sst_hsw_stream *stream;
d132cb0a
WD		 1180 struct sst_dsp *sst = hsw->dsp;
1181 unsigned long flags;
a4b12990
MB		 1182
1183 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
1184 if (stream == NULL)
1185 return NULL;
1186
d132cb0a 1187 spin_lock_irqsave(&sst->spinlock, flags);
a4b12990
MB		 1188 list_add(&stream->node, &hsw->stream_list);
1189 stream->notify_position = notify_position;
1190 stream->pdata = data;
1191 stream->hsw = hsw;
1192 stream->host_id = id;
1193
1194 /* work to process notification messages */
1195 INIT_WORK(&stream->notify_work, hsw_notification_work);
d132cb0a 1196 spin_unlock_irqrestore(&sst->spinlock, flags);
a4b12990
MB		 1197
1198 return stream;
1199}
1200
1201int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1202{
1203 u32 header;
1204 int ret = 0;
d132cb0a
WD		 1205 struct sst_dsp *sst = hsw->dsp;
1206 unsigned long flags;
a4b12990
MB		 1207
1208 /* dont free DSP streams that are not commited */
1209 if (!stream->commited)
1210 goto out;
1211
1212 trace_ipc_request("stream free", stream->host_id);
1213
1214 stream->free_req.stream_id = stream->reply.stream_hw_id;
1215 header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
1216
1217 ret = ipc_tx_message_wait(hsw, header, &stream->free_req,
1218 sizeof(stream->free_req), NULL, 0);
1219 if (ret < 0) {
1220 dev_err(hsw->dev, "error: free stream %d failed\n",
1221 stream->free_req.stream_id);
1222 return -EAGAIN;
1223 }
1224
1225 trace_hsw_stream_free_req(stream, &stream->free_req);
1226
1227out:
de30a2cc 1228 cancel_work_sync(&stream->notify_work);
d132cb0a 1229 spin_lock_irqsave(&sst->spinlock, flags);
a4b12990
MB		 1230 list_del(&stream->node);
1231 kfree(stream);
d132cb0a 1232 spin_unlock_irqrestore(&sst->spinlock, flags);
a4b12990
MB		 1233
1234 return ret;
1235}
1236
1237int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
1238 struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
1239{
1240 if (stream->commited) {
1241 dev_err(hsw->dev, "error: stream committed for set bits\n");
1242 return -EINVAL;
1243 }
1244
1245 stream->request.format.bitdepth = bits;
1246 return 0;
1247}
1248
1249int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
1250 struct sst_hsw_stream *stream, int channels)
1251{
1252 if (stream->commited) {
1253 dev_err(hsw->dev, "error: stream committed for set channels\n");
1254 return -EINVAL;
1255 }
1256
1257 /* stereo is only supported atm */
1258 if (channels != 2)
1259 return -EINVAL;
1260
1261 stream->request.format.ch_num = channels;
1262 return 0;
1263}
1264
1265int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
1266 struct sst_hsw_stream *stream, int rate)
1267{
1268 if (stream->commited) {
1269 dev_err(hsw->dev, "error: stream committed for set rate\n");
1270 return -EINVAL;
1271 }
1272
1273 stream->request.format.frequency = rate;
1274 return 0;
1275}
1276
1277int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
1278 struct sst_hsw_stream *stream, u32 map,
1279 enum sst_hsw_channel_config config)
1280{
1281 if (stream->commited) {
1282 dev_err(hsw->dev, "error: stream committed for set map\n");
1283 return -EINVAL;
1284 }
1285
1286 stream->request.format.map = map;
1287 stream->request.format.config = config;
1288 return 0;
1289}
1290
1291int sst_hsw_stream_set_style(struct sst_hsw *hsw,
1292 struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
1293{
1294 if (stream->commited) {
1295 dev_err(hsw->dev, "error: stream committed for set style\n");
1296 return -EINVAL;
1297 }
1298
1299 stream->request.format.style = style;
1300 return 0;
1301}
1302
1303int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
1304 struct sst_hsw_stream *stream, u32 bits)
1305{
1306 if (stream->commited) {
1307 dev_err(hsw->dev, "error: stream committed for set valid bits\n");
1308 return -EINVAL;
1309 }
1310
1311 stream->request.format.valid_bit = bits;
1312 return 0;
1313}
1314
1315/* Stream Configuration */
1316int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1317 enum sst_hsw_stream_path_id path_id,
1318 enum sst_hsw_stream_type stream_type,
1319 enum sst_hsw_stream_format format_id)
1320{
1321 if (stream->commited) {
1322 dev_err(hsw->dev, "error: stream committed for set format\n");
1323 return -EINVAL;
1324 }
1325
1326 stream->request.path_id = path_id;
1327 stream->request.stream_type = stream_type;
1328 stream->request.format_id = format_id;
1329
1330 trace_hsw_stream_alloc_request(stream, &stream->request);
1331
1332 return 0;
1333}
1334
1335int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1336 u32 ring_pt_address, u32 num_pages,
1337 u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
1338{
1339 if (stream->commited) {
1340 dev_err(hsw->dev, "error: stream committed for buffer\n");
1341 return -EINVAL;
1342 }
1343
1344 stream->request.ringinfo.ring_pt_address = ring_pt_address;
1345 stream->request.ringinfo.num_pages = num_pages;
1346 stream->request.ringinfo.ring_size = ring_size;
1347 stream->request.ringinfo.ring_offset = ring_offset;
1348 stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
1349
1350 trace_hsw_stream_buffer(stream);
1351
1352 return 0;
1353}
1354
1355int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
1356 struct sst_hsw_stream *stream, enum sst_hsw_module_id module_id,
1357 u32 entry_point)
1358{
1359 struct sst_hsw_module_map *map = &stream->request.map;
1360
1361 if (stream->commited) {
1362 dev_err(hsw->dev, "error: stream committed for set module\n");
1363 return -EINVAL;
1364 }
1365
1366 /* only support initial module atm */
1367 map->module_entries_count = 1;
1368 map->module_entries[0].module_id = module_id;
1369 map->module_entries[0].entry_point = entry_point;
1370
1371 return 0;
1372}
1373
1374int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw,
1375 struct sst_hsw_stream *stream, u32 offset, u32 size)
1376{
1377 if (stream->commited) {
1378 dev_err(hsw->dev, "error: stream committed for set pmem\n");
1379 return -EINVAL;
1380 }
1381
1382 stream->request.persistent_mem.offset = offset;
1383 stream->request.persistent_mem.size = size;
1384
1385 return 0;
1386}
1387
1388int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw,
1389 struct sst_hsw_stream *stream, u32 offset, u32 size)
1390{
1391 if (stream->commited) {
1392 dev_err(hsw->dev, "error: stream committed for set smem\n");
1393 return -EINVAL;
1394 }
1395
1396 stream->request.scratch_mem.offset = offset;
1397 stream->request.scratch_mem.size = size;
1398
1399 return 0;
1400}
1401
1402int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1403{
1404 struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
1405 struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
1406 u32 header;
1407 int ret;
1408
1409 trace_ipc_request("stream alloc", stream->host_id);
1410
1411 header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
1412
1413 ret = ipc_tx_message_wait(hsw, header, str_req, sizeof(*str_req),
1414 reply, sizeof(*reply));
1415 if (ret < 0) {
1416 dev_err(hsw->dev, "error: stream commit failed\n");
1417 return ret;
1418 }
1419
1420 stream->commited = 1;
1421 trace_hsw_stream_alloc_reply(stream);
1422
1423 return 0;
1424}
1425
1426/* Stream Information - these calls could be inline but we want the IPC
1427 ABI to be opaque to client PCM drivers to cope with any future ABI changes */
1428int sst_hsw_stream_get_hw_id(struct sst_hsw *hsw,
1429 struct sst_hsw_stream *stream)
1430{
1431 return stream->reply.stream_hw_id;
1432}
1433
1434int sst_hsw_stream_get_mixer_id(struct sst_hsw *hsw,
1435 struct sst_hsw_stream *stream)
1436{
1437 return stream->reply.mixer_hw_id;
1438}
1439
1440u32 sst_hsw_stream_get_read_reg(struct sst_hsw *hsw,
1441 struct sst_hsw_stream *stream)
1442{
1443 return stream->reply.read_position_register_address;
1444}
1445
1446u32 sst_hsw_stream_get_pointer_reg(struct sst_hsw *hsw,
1447 struct sst_hsw_stream *stream)
1448{
1449 return stream->reply.presentation_position_register_address;
1450}
1451
1452u32 sst_hsw_stream_get_peak_reg(struct sst_hsw *hsw,
1453 struct sst_hsw_stream *stream, u32 channel)
1454{
1455 if (channel >= 2)
1456 return 0;
1457
1458 return stream->reply.peak_meter_register_address[channel];
1459}
1460
1461u32 sst_hsw_stream_get_vol_reg(struct sst_hsw *hsw,
1462 struct sst_hsw_stream *stream, u32 channel)
1463{
1464 if (channel >= 2)
1465 return 0;
1466
1467 return stream->reply.volume_register_address[channel];
1468}
1469
1470int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
1471{
1472 struct sst_hsw_ipc_stream_info_reply *reply;
1473 u32 header;
1474 int ret;
1475
1476 reply = &hsw->mixer_info;
1477 header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
1478
1479 trace_ipc_request("get global mixer info", 0);
1480
1481 ret = ipc_tx_message_wait(hsw, header, NULL, 0, reply, sizeof(*reply));
1482 if (ret < 0) {
1483 dev_err(hsw->dev, "error: get stream info failed\n");
1484 return ret;
1485 }
1486
1487 trace_hsw_mixer_info_reply(reply);
1488
1489 return 0;
1490}
1491
1492/* Send stream command */
1493static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
1494 int stream_id, int wait)
1495{
1496 u32 header;
1497
1498 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
1499 header |= (stream_id << IPC_STR_ID_SHIFT);
1500
1501 if (wait)
1502 return ipc_tx_message_wait(hsw, header, NULL, 0, NULL, 0);
1503 else
1504 return ipc_tx_message_nowait(hsw, header, NULL, 0);
1505}
1506
1507/* Stream ALSA trigger operations */
1508int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1509 int wait)
1510{
1511 int ret;
1512
1513 trace_ipc_request("stream pause", stream->reply.stream_hw_id);
1514
1515 ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
1516 stream->reply.stream_hw_id, wait);
1517 if (ret < 0)
1518 dev_err(hsw->dev, "error: failed to pause stream %d\n",
1519 stream->reply.stream_hw_id);
1520
1521 return ret;
1522}
1523
1524int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1525 int wait)
1526{
1527 int ret;
1528
1529 trace_ipc_request("stream resume", stream->reply.stream_hw_id);
1530
1531 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
1532 stream->reply.stream_hw_id, wait);
1533 if (ret < 0)
1534 dev_err(hsw->dev, "error: failed to resume stream %d\n",
1535 stream->reply.stream_hw_id);
1536
1537 return ret;
1538}
1539
1540int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1541{
1542 int ret, tries = 10;
1543
1544 /* dont reset streams that are not commited */
1545 if (!stream->commited)
1546 return 0;
1547
1548 /* wait for pause to complete before we reset the stream */
1549 while (stream->running && tries--)
1550 msleep(1);
1551 if (!tries) {
1552 dev_err(hsw->dev, "error: reset stream %d still running\n",
1553 stream->reply.stream_hw_id);
1554 return -EINVAL;
1555 }
1556
1557 trace_ipc_request("stream reset", stream->reply.stream_hw_id);
1558
1559 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
1560 stream->reply.stream_hw_id, 1);
1561 if (ret < 0)
1562 dev_err(hsw->dev, "error: failed to reset stream %d\n",
1563 stream->reply.stream_hw_id);
1564 return ret;
1565}
1566
1567/* Stream pointer positions */
51b4e24f 1568u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
a4b12990
MB		 1569 struct sst_hsw_stream *stream)
1570{
51b4e24f
LG		 1571 u32 rpos;
1572
1573 sst_dsp_read(hsw->dsp, &rpos,
1574 stream->reply.read_position_register_address, sizeof(rpos));
1575
1576 return rpos;
1577}
1578
1579/* Stream presentation (monotonic) positions */
1580u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
1581 struct sst_hsw_stream *stream)
1582{
1583 u64 ppos;
1584
1585 sst_dsp_read(hsw->dsp, &ppos,
1586 stream->reply.presentation_position_register_address,
1587 sizeof(ppos));
1588
1589 return ppos;
a4b12990
MB		 1590}
1591
1592int sst_hsw_stream_set_write_position(struct sst_hsw *hsw,
1593 struct sst_hsw_stream *stream, u32 stage_id, u32 position)
1594{
1595 u32 header;
1596 int ret;
1597
1598 trace_stream_write_position(stream->reply.stream_hw_id, position);
1599
1600 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1601 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1602 header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
1603 header |= (IPC_STG_SET_WRITE_POSITION << IPC_STG_TYPE_SHIFT);
1604 header |= (stage_id << IPC_STG_ID_SHIFT);
1605 stream->wpos.position = position;
1606
1607 ret = ipc_tx_message_nowait(hsw, header, &stream->wpos,
1608 sizeof(stream->wpos));
1609 if (ret < 0)
1610 dev_err(hsw->dev, "error: stream %d set position %d failed\n",
1611 stream->reply.stream_hw_id, position);
1612
1613 return ret;
1614}
1615
1616/* physical BE config */
1617int sst_hsw_device_set_config(struct sst_hsw *hsw,
1618 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
1619 enum sst_hsw_device_mode mode, u32 clock_divider)
1620{
1621 struct sst_hsw_ipc_device_config_req config;
1622 u32 header;
1623 int ret;
1624
1625 trace_ipc_request("set device config", dev);
1626
1627 config.ssp_interface = dev;
1628 config.clock_frequency = mclk;
1629 config.mode = mode;
1630 config.clock_divider = clock_divider;
1631
1632 trace_hsw_device_config_req(&config);
1633
1634 header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
1635
1636 ret = ipc_tx_message_wait(hsw, header, &config, sizeof(config),
1637 NULL, 0);
1638 if (ret < 0)
1639 dev_err(hsw->dev, "error: set device formats failed\n");
1640
1641 return ret;
1642}
1643EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
1644
1645/* DX Config */
1646int sst_hsw_dx_set_state(struct sst_hsw *hsw,
1647 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
1648{
1649 u32 header, state_;
543ec637 1650 int ret, item;
a4b12990
MB		 1651
1652 header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
1653 state_ = state;
1654
1655 trace_ipc_request("PM enter Dx state", state);
1656
1657 ret = ipc_tx_message_wait(hsw, header, &state_, sizeof(state_),
7897ab78 1658 dx, sizeof(*dx));
a4b12990
MB		 1659 if (ret < 0) {
1660 dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
1661 return ret;
1662 }
1663
543ec637
LG		 1664 for (item = 0; item < dx->entries_no; item++) {
1665 dev_dbg(hsw->dev,
1666 "Item[%d] offset[%x] - size[%x] - source[%x]\n",
1667 item, dx->mem_info[item].offset,
1668 dx->mem_info[item].size,
1669 dx->mem_info[item].source);
1670 }
a4b12990
MB		 1671 dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
1672 dx->entries_no, state);
1673
1674 memcpy(&hsw->dx, dx, sizeof(*dx));
1675 return 0;
1676}
1677
1678/* Used to save state into hsw->dx_reply */
1679int sst_hsw_dx_get_state(struct sst_hsw *hsw, u32 item,
1680 u32 *offset, u32 *size, u32 *source)
1681{
1682 struct sst_hsw_ipc_dx_memory_item *dx_mem;
1683 struct sst_hsw_ipc_dx_reply *dx_reply;
1684 int entry_no;
1685
1686 dx_reply = &hsw->dx;
1687 entry_no = dx_reply->entries_no;
1688
1689 trace_ipc_request("PM get Dx state", entry_no);
1690
1691 if (item >= entry_no)
1692 return -EINVAL;
1693
1694 dx_mem = &dx_reply->mem_info[item];
1695 *offset = dx_mem->offset;
1696 *size = dx_mem->size;
1697 *source = dx_mem->source;
1698
1699 return 0;
1700}
1701
1702static int msg_empty_list_init(struct sst_hsw *hsw)
1703{
1704 int i;
1705
1706 hsw->msg = kzalloc(sizeof(struct ipc_message) *
1707 IPC_EMPTY_LIST_SIZE, GFP_KERNEL);
1708 if (hsw->msg == NULL)
1709 return -ENOMEM;
1710
1711 for (i = 0; i < IPC_EMPTY_LIST_SIZE; i++) {
1712 init_waitqueue_head(&hsw->msg[i].waitq);
1713 list_add(&hsw->msg[i].list, &hsw->empty_list);
1714 }
1715
1716 return 0;
1717}
1718
1719void sst_hsw_set_scratch_module(struct sst_hsw *hsw,
1720 struct sst_module *scratch)
1721{
1722 hsw->scratch = scratch;
1723}
1724
1725struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
1726{
1727 return hsw->dsp;
1728}
1729
1730static struct sst_dsp_device hsw_dev = {
1731 .thread = hsw_irq_thread,
1732 .ops = &haswell_ops,
1733};
1734
1735int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
1736{
1737 struct sst_hsw_ipc_fw_version version;
1738 struct sst_hsw *hsw;
1739 struct sst_fw *hsw_sst_fw;
1740 int ret;
1741
1742 dev_dbg(dev, "initialising Audio DSP IPC\n");
1743
1744 hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
1745 if (hsw == NULL)
1746 return -ENOMEM;
1747
1748 hsw->dev = dev;
1749 INIT_LIST_HEAD(&hsw->stream_list);
1750 INIT_LIST_HEAD(&hsw->tx_list);
1751 INIT_LIST_HEAD(&hsw->rx_list);
1752 INIT_LIST_HEAD(&hsw->empty_list);
1753 init_waitqueue_head(&hsw->boot_wait);
1754 init_waitqueue_head(&hsw->wait_txq);
1755
1756 ret = msg_empty_list_init(hsw);
1757 if (ret < 0)
9cf0e452 1758 return -ENOMEM;
a4b12990
MB		 1759
1760 /* start the IPC message thread */
1761 init_kthread_worker(&hsw->kworker);
1762 hsw->tx_thread = kthread_run(kthread_worker_fn,
35386320 1763 &hsw->kworker, "%s",
a4b12990
MB		 1764 dev_name(hsw->dev));
1765 if (IS_ERR(hsw->tx_thread)) {
1766 ret = PTR_ERR(hsw->tx_thread);
1767 dev_err(hsw->dev, "error: failed to create message TX task\n");
9cf0e452 1768 goto err_free_msg;
a4b12990
MB		 1769 }
1770 init_kthread_work(&hsw->kwork, ipc_tx_msgs);
1771
1772 hsw_dev.thread_context = hsw;
1773
1774 /* init SST shim */
1775 hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
1776 if (hsw->dsp == NULL) {
1777 ret = -ENODEV;
9cf0e452 1778 goto dsp_err;
a4b12990
MB		 1779 }
1780
1781 /* keep the DSP in reset state for base FW loading */
1782 sst_dsp_reset(hsw->dsp);
1783
1784 hsw_sst_fw = sst_fw_new(hsw->dsp, pdata->fw, hsw);
1785
1786 if (hsw_sst_fw == NULL) {
1787 ret = -ENODEV;
1788 dev_err(dev, "error: failed to load firmware\n");
1789 goto fw_err;
1790 }
1791
1792 /* wait for DSP boot completion */
1793 sst_dsp_boot(hsw->dsp);
1794 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
1795 msecs_to_jiffies(IPC_BOOT_MSECS));
1796 if (ret == 0) {
1797 ret = -EIO;
1798 dev_err(hsw->dev, "error: ADSP boot timeout\n");
1799 goto boot_err;
1800 }
1801
1802 /* get the FW version */
1803 sst_hsw_fw_get_version(hsw, &version);
a4b12990
MB		 1804
1805 /* get the globalmixer */
1806 ret = sst_hsw_mixer_get_info(hsw);
1807 if (ret < 0) {
1808 dev_err(hsw->dev, "error: failed to get stream info\n");
1809 goto boot_err;
1810 }
1811
1812 pdata->dsp = hsw;
1813 return 0;
1814
1815boot_err:
1816 sst_dsp_reset(hsw->dsp);
1817 sst_fw_free(hsw_sst_fw);
1818fw_err:
1819 sst_dsp_free(hsw->dsp);
9cf0e452
ID		 1820dsp_err:
1821 kthread_stop(hsw->tx_thread);
1822err_free_msg:
a4b12990 1823 kfree(hsw->msg);
9cf0e452 1824
a4b12990
MB		 1825 return ret;
1826}
1827EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
1828
1829void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
1830{
1831 struct sst_hsw *hsw = pdata->dsp;
1832
1833 sst_dsp_reset(hsw->dsp);
1834 sst_fw_free_all(hsw->dsp);
1835 sst_dsp_free(hsw->dsp);
1836 kfree(hsw->scratch);
9cf0e452 1837 kthread_stop(hsw->tx_thread);
a4b12990
MB		 1838 kfree(hsw->msg);
1839}
1840EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);
Linux kernel - Deliverables
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