Merge branch 'fixes' into next/fixes-non-critical
[deliverable/linux.git] / sound / soc / intel / sst-haswell-ipc.h
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1/*
2 * Intel SST Haswell/Broadwell IPC Support
3 *
4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __SST_HASWELL_IPC_H
18#define __SST_HASWELL_IPC_H
19
20#include <linux/types.h>
21#include <linux/kernel.h>
22#include <linux/platform_device.h>
1b006996 23#include <sound/asound.h>
a4b12990 24
f74e2c9c 25#define SST_HSW_NO_CHANNELS 4
a4b12990 26#define SST_HSW_MAX_DX_REGIONS 14
aed3c7b7 27#define SST_HSW_DX_CONTEXT_SIZE (640 * 1024)
f1e59825 28#define SST_HSW_CHANNELS_ALL 0xffffffff
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29
30#define SST_HSW_FW_LOG_CONFIG_DWORDS 12
31#define SST_HSW_GLOBAL_LOG 15
32
33/**
34 * Upfront defined maximum message size that is
35 * expected by the in/out communication pipes in FW.
36 */
37#define SST_HSW_IPC_MAX_PAYLOAD_SIZE 400
38#define SST_HSW_MAX_INFO_SIZE 64
39#define SST_HSW_BUILD_HASH_LENGTH 40
40
41struct sst_hsw;
42struct sst_hsw_stream;
43struct sst_hsw_log_stream;
44struct sst_pdata;
45struct sst_module;
e9600bc1 46struct sst_module_runtime;
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47extern struct sst_ops haswell_ops;
48
49/* Stream Allocate Path ID */
50enum sst_hsw_stream_path_id {
51 SST_HSW_STREAM_PATH_SSP0_OUT = 0,
52 SST_HSW_STREAM_PATH_SSP0_IN = 1,
53 SST_HSW_STREAM_PATH_MAX_PATH_ID = 2,
54};
55
56/* Stream Allocate Stream Type */
57enum sst_hsw_stream_type {
58 SST_HSW_STREAM_TYPE_RENDER = 0,
59 SST_HSW_STREAM_TYPE_SYSTEM = 1,
60 SST_HSW_STREAM_TYPE_CAPTURE = 2,
61 SST_HSW_STREAM_TYPE_LOOPBACK = 3,
62 SST_HSW_STREAM_TYPE_MAX_STREAM_TYPE = 4,
63};
64
65/* Stream Allocate Stream Format */
66enum sst_hsw_stream_format {
67 SST_HSW_STREAM_FORMAT_PCM_FORMAT = 0,
68 SST_HSW_STREAM_FORMAT_MP3_FORMAT = 1,
69 SST_HSW_STREAM_FORMAT_AAC_FORMAT = 2,
70 SST_HSW_STREAM_FORMAT_MAX_FORMAT_ID = 3,
71};
72
73/* Device ID */
74enum sst_hsw_device_id {
75 SST_HSW_DEVICE_SSP_0 = 0,
76 SST_HSW_DEVICE_SSP_1 = 1,
77};
78
79/* Device Master Clock Frequency */
80enum sst_hsw_device_mclk {
81 SST_HSW_DEVICE_MCLK_OFF = 0,
82 SST_HSW_DEVICE_MCLK_FREQ_6_MHZ = 1,
83 SST_HSW_DEVICE_MCLK_FREQ_12_MHZ = 2,
84 SST_HSW_DEVICE_MCLK_FREQ_24_MHZ = 3,
85};
86
87/* Device Clock Master */
88enum sst_hsw_device_mode {
89 SST_HSW_DEVICE_CLOCK_SLAVE = 0,
90 SST_HSW_DEVICE_CLOCK_MASTER = 1,
f07e51c5 91 SST_HSW_DEVICE_TDM_CLOCK_MASTER = 2,
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92};
93
94/* DX Power State */
95enum sst_hsw_dx_state {
96 SST_HSW_DX_STATE_D0 = 0,
97 SST_HSW_DX_STATE_D1 = 1,
98 SST_HSW_DX_STATE_D3 = 3,
99 SST_HSW_DX_STATE_MAX = 3,
100};
101
102/* Audio stream stage IDs */
103enum sst_hsw_fx_stage_id {
104 SST_HSW_STAGE_ID_WAVES = 0,
105 SST_HSW_STAGE_ID_DTS = 1,
106 SST_HSW_STAGE_ID_DOLBY = 2,
107 SST_HSW_STAGE_ID_BOOST = 3,
108 SST_HSW_STAGE_ID_MAX_FX_ID
109};
110
111/* DX State Type */
112enum sst_hsw_dx_type {
113 SST_HSW_DX_TYPE_FW_IMAGE = 0,
114 SST_HSW_DX_TYPE_MEMORY_DUMP = 1
115};
116
117/* Volume Curve Type*/
118enum sst_hsw_volume_curve {
119 SST_HSW_VOLUME_CURVE_NONE = 0,
120 SST_HSW_VOLUME_CURVE_FADE = 1
121};
122
123/* Sample ordering */
124enum sst_hsw_interleaving {
125 SST_HSW_INTERLEAVING_PER_CHANNEL = 0,
126 SST_HSW_INTERLEAVING_PER_SAMPLE = 1,
127};
128
129/* Channel indices */
130enum sst_hsw_channel_index {
131 SST_HSW_CHANNEL_LEFT = 0,
132 SST_HSW_CHANNEL_CENTER = 1,
133 SST_HSW_CHANNEL_RIGHT = 2,
134 SST_HSW_CHANNEL_LEFT_SURROUND = 3,
135 SST_HSW_CHANNEL_CENTER_SURROUND = 3,
136 SST_HSW_CHANNEL_RIGHT_SURROUND = 4,
137 SST_HSW_CHANNEL_LFE = 7,
138 SST_HSW_CHANNEL_INVALID = 0xF,
139};
140
141/* List of supported channel maps. */
142enum sst_hsw_channel_config {
143 SST_HSW_CHANNEL_CONFIG_MONO = 0, /* mono only. */
144 SST_HSW_CHANNEL_CONFIG_STEREO = 1, /* L & R. */
145 SST_HSW_CHANNEL_CONFIG_2_POINT_1 = 2, /* L, R & LFE; PCM only. */
146 SST_HSW_CHANNEL_CONFIG_3_POINT_0 = 3, /* L, C & R; MP3 & AAC only. */
147 SST_HSW_CHANNEL_CONFIG_3_POINT_1 = 4, /* L, C, R & LFE; PCM only. */
148 SST_HSW_CHANNEL_CONFIG_QUATRO = 5, /* L, R, Ls & Rs; PCM only. */
149 SST_HSW_CHANNEL_CONFIG_4_POINT_0 = 6, /* L, C, R & Cs; MP3 & AAC only. */
150 SST_HSW_CHANNEL_CONFIG_5_POINT_0 = 7, /* L, C, R, Ls & Rs. */
151 SST_HSW_CHANNEL_CONFIG_5_POINT_1 = 8, /* L, C, R, Ls, Rs & LFE. */
152 SST_HSW_CHANNEL_CONFIG_DUAL_MONO = 9, /* One channel replicated in two. */
153 SST_HSW_CHANNEL_CONFIG_INVALID,
154};
155
156/* List of supported bit depths. */
157enum sst_hsw_bitdepth {
158 SST_HSW_DEPTH_8BIT = 8,
159 SST_HSW_DEPTH_16BIT = 16,
160 SST_HSW_DEPTH_24BIT = 24, /* Default. */
161 SST_HSW_DEPTH_32BIT = 32,
162 SST_HSW_DEPTH_INVALID = 33,
163};
164
165enum sst_hsw_module_id {
166 SST_HSW_MODULE_BASE_FW = 0x0,
167 SST_HSW_MODULE_MP3 = 0x1,
168 SST_HSW_MODULE_AAC_5_1 = 0x2,
169 SST_HSW_MODULE_AAC_2_0 = 0x3,
170 SST_HSW_MODULE_SRC = 0x4,
171 SST_HSW_MODULE_WAVES = 0x5,
172 SST_HSW_MODULE_DOLBY = 0x6,
173 SST_HSW_MODULE_BOOST = 0x7,
174 SST_HSW_MODULE_LPAL = 0x8,
175 SST_HSW_MODULE_DTS = 0x9,
176 SST_HSW_MODULE_PCM_CAPTURE = 0xA,
177 SST_HSW_MODULE_PCM_SYSTEM = 0xB,
178 SST_HSW_MODULE_PCM_REFERENCE = 0xC,
179 SST_HSW_MODULE_PCM = 0xD,
180 SST_HSW_MODULE_BLUETOOTH_RENDER_MODULE = 0xE,
181 SST_HSW_MODULE_BLUETOOTH_CAPTURE_MODULE = 0xF,
182 SST_HSW_MAX_MODULE_ID,
183};
184
185enum sst_hsw_performance_action {
186 SST_HSW_PERF_START = 0,
187 SST_HSW_PERF_STOP = 1,
188};
189
190/* SST firmware module info */
191struct sst_hsw_module_info {
192 u8 name[SST_HSW_MAX_INFO_SIZE];
193 u8 version[SST_HSW_MAX_INFO_SIZE];
194} __attribute__((packed));
195
196/* Module entry point */
197struct sst_hsw_module_entry {
198 enum sst_hsw_module_id module_id;
199 u32 entry_point;
200} __attribute__((packed));
201
202/* Module map - alignement matches DSP */
203struct sst_hsw_module_map {
204 u8 module_entries_count;
205 struct sst_hsw_module_entry module_entries[1];
206} __attribute__((packed));
207
208struct sst_hsw_memory_info {
209 u32 offset;
210 u32 size;
211} __attribute__((packed));
212
213struct sst_hsw_fx_enable {
214 struct sst_hsw_module_map module_map;
215 struct sst_hsw_memory_info persistent_mem;
216} __attribute__((packed));
217
218struct sst_hsw_get_fx_param {
219 u32 parameter_id;
220 u32 param_size;
221} __attribute__((packed));
222
223struct sst_hsw_perf_action {
224 u32 action;
225} __attribute__((packed));
226
227struct sst_hsw_perf_data {
228 u64 timestamp;
229 u64 cycles;
230 u64 datatime;
231} __attribute__((packed));
232
233/* FW version */
234struct sst_hsw_ipc_fw_version {
235 u8 build;
236 u8 minor;
237 u8 major;
238 u8 type;
239 u8 fw_build_hash[SST_HSW_BUILD_HASH_LENGTH];
240 u32 fw_log_providers_hash;
241} __attribute__((packed));
242
243/* Stream ring info */
244struct sst_hsw_ipc_stream_ring {
245 u32 ring_pt_address;
246 u32 num_pages;
247 u32 ring_size;
248 u32 ring_offset;
249 u32 ring_first_pfn;
250} __attribute__((packed));
251
252/* Debug Dump Log Enable Request */
253struct sst_hsw_ipc_debug_log_enable_req {
254 struct sst_hsw_ipc_stream_ring ringinfo;
255 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
256} __attribute__((packed));
257
258/* Debug Dump Log Reply */
259struct sst_hsw_ipc_debug_log_reply {
260 u32 log_buffer_begining;
261 u32 log_buffer_size;
262} __attribute__((packed));
263
264/* Stream glitch position */
265struct sst_hsw_ipc_stream_glitch_position {
266 u32 glitch_type;
267 u32 present_pos;
268 u32 write_pos;
269} __attribute__((packed));
270
271/* Stream get position */
272struct sst_hsw_ipc_stream_get_position {
273 u32 position;
274 u32 fw_cycle_count;
275} __attribute__((packed));
276
277/* Stream set position */
278struct sst_hsw_ipc_stream_set_position {
279 u32 position;
280 u32 end_of_buffer;
281} __attribute__((packed));
282
283/* Stream Free Request */
284struct sst_hsw_ipc_stream_free_req {
285 u8 stream_id;
286 u8 reserved[3];
287} __attribute__((packed));
288
289/* Set Volume Request */
290struct sst_hsw_ipc_volume_req {
291 u32 channel;
292 u32 target_volume;
293 u64 curve_duration;
294 u32 curve_type;
295} __attribute__((packed));
296
297/* Device Configuration Request */
298struct sst_hsw_ipc_device_config_req {
299 u32 ssp_interface;
300 u32 clock_frequency;
301 u32 mode;
302 u16 clock_divider;
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303 u8 channels;
304 u8 reserved;
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305} __attribute__((packed));
306
307/* Audio Data formats */
308struct sst_hsw_audio_data_format_ipc {
309 u32 frequency;
310 u32 bitdepth;
311 u32 map;
312 u32 config;
313 u32 style;
314 u8 ch_num;
315 u8 valid_bit;
316 u8 reserved[2];
317} __attribute__((packed));
318
319/* Stream Allocate Request */
320struct sst_hsw_ipc_stream_alloc_req {
321 u8 path_id;
322 u8 stream_type;
323 u8 format_id;
324 u8 reserved;
325 struct sst_hsw_audio_data_format_ipc format;
326 struct sst_hsw_ipc_stream_ring ringinfo;
327 struct sst_hsw_module_map map;
328 struct sst_hsw_memory_info persistent_mem;
329 struct sst_hsw_memory_info scratch_mem;
330 u32 number_of_notifications;
331} __attribute__((packed));
332
333/* Stream Allocate Reply */
334struct sst_hsw_ipc_stream_alloc_reply {
335 u32 stream_hw_id;
336 u32 mixer_hw_id; // returns rate ????
337 u32 read_position_register_address;
338 u32 presentation_position_register_address;
339 u32 peak_meter_register_address[SST_HSW_NO_CHANNELS];
340 u32 volume_register_address[SST_HSW_NO_CHANNELS];
341} __attribute__((packed));
342
343/* Get Mixer Stream Info */
344struct sst_hsw_ipc_stream_info_reply {
345 u32 mixer_hw_id;
346 u32 peak_meter_register_address[SST_HSW_NO_CHANNELS];
347 u32 volume_register_address[SST_HSW_NO_CHANNELS];
348} __attribute__((packed));
349
350/* DX State Request */
351struct sst_hsw_ipc_dx_req {
352 u8 state;
353 u8 reserved[3];
354} __attribute__((packed));
355
356/* DX State Reply Memory Info Item */
357struct sst_hsw_ipc_dx_memory_item {
358 u32 offset;
359 u32 size;
360 u32 source;
361} __attribute__((packed));
362
363/* DX State Reply */
364struct sst_hsw_ipc_dx_reply {
365 u32 entries_no;
366 struct sst_hsw_ipc_dx_memory_item mem_info[SST_HSW_MAX_DX_REGIONS];
367} __attribute__((packed));
368
369struct sst_hsw_ipc_fw_version;
370
371/* SST Init & Free */
372struct sst_hsw *sst_hsw_new(struct device *dev, const u8 *fw, size_t fw_length,
373 u32 fw_offset);
374void sst_hsw_free(struct sst_hsw *hsw);
375int sst_hsw_fw_get_version(struct sst_hsw *hsw,
376 struct sst_hsw_ipc_fw_version *version);
377u32 create_channel_map(enum sst_hsw_channel_config config);
378
379/* Stream Mixer Controls - */
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380int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
381 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume);
382int sst_hsw_stream_get_volume(struct sst_hsw *hsw,
383 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 *volume);
384
a4b12990 385/* Global Mixer Controls - */
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386int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
387 u32 volume);
388int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
389 u32 *volume);
390
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391/* Stream API */
392struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
393 u32 (*get_write_position)(struct sst_hsw_stream *stream, void *data),
394 void *data);
395
396int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
397
398/* Stream Configuration */
399int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
400 enum sst_hsw_stream_path_id path_id,
401 enum sst_hsw_stream_type stream_type,
402 enum sst_hsw_stream_format format_id);
403
404int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
405 u32 ring_pt_address, u32 num_pages,
406 u32 ring_size, u32 ring_offset, u32 ring_first_pfn);
407
408int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
409
410int sst_hsw_stream_set_valid(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
411 u32 bits);
412int sst_hsw_stream_set_rate(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
413 int rate);
414int sst_hsw_stream_set_bits(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
415 enum sst_hsw_bitdepth bits);
416int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
417 struct sst_hsw_stream *stream, int channels);
418int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
419 struct sst_hsw_stream *stream, u32 map,
420 enum sst_hsw_channel_config config);
421int sst_hsw_stream_set_style(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
422 enum sst_hsw_interleaving style);
423int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
e9600bc1 424 struct sst_hsw_stream *stream, struct sst_module_runtime *runtime);
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425int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw,
426 struct sst_hsw_stream *stream, u32 offset, u32 size);
427int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw,
428 struct sst_hsw_stream *stream, u32 offset, u32 size);
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429snd_pcm_uframes_t sst_hsw_stream_get_old_position(struct sst_hsw *hsw,
430 struct sst_hsw_stream *stream);
431void sst_hsw_stream_set_old_position(struct sst_hsw *hsw,
432 struct sst_hsw_stream *stream, snd_pcm_uframes_t val);
433bool sst_hsw_stream_get_silence_start(struct sst_hsw *hsw,
434 struct sst_hsw_stream *stream);
435void sst_hsw_stream_set_silence_start(struct sst_hsw *hsw,
436 struct sst_hsw_stream *stream, bool val);
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437int sst_hsw_mixer_get_info(struct sst_hsw *hsw);
438
439/* Stream ALSA trigger operations */
440int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
441 int wait);
442int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
443 int wait);
444int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
445
446/* Stream pointer positions */
447int sst_hsw_stream_get_read_pos(struct sst_hsw *hsw,
448 struct sst_hsw_stream *stream, u32 *position);
449int sst_hsw_stream_get_write_pos(struct sst_hsw *hsw,
450 struct sst_hsw_stream *stream, u32 *position);
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451u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
452 struct sst_hsw_stream *stream);
453u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
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454 struct sst_hsw_stream *stream);
455
456/* HW port config */
457int sst_hsw_device_set_config(struct sst_hsw *hsw,
458 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
459 enum sst_hsw_device_mode mode, u32 clock_divider);
460
461/* DX Config */
462int sst_hsw_dx_set_state(struct sst_hsw *hsw,
463 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx);
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464
465/* init */
466int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata);
467void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata);
468struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw);
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469
470/* runtime module management */
471struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
472 int mod_id, int offset);
473void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime);
a4b12990 474
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475/* PM */
476int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw);
477int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw);
478int sst_hsw_dsp_load(struct sst_hsw *hsw);
479int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw);
480
a4b12990 481#endif
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