[deliverable/linux.git] / sound / soc / jz4740 / jz4740-i2s.c

/*
 *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under  the terms of the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <linux/clk.h>
#include <linux/delay.h>

#include <linux/dma-mapping.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/dmaengine_pcm.h>

#include "jz4740-i2s.h"

#define JZ4740_DMA_TYPE_AIC_TRANSMIT 24
#define JZ4740_DMA_TYPE_AIC_RECEIVE 25

#define JZ_REG_AIC_CONF		0x00
#define JZ_REG_AIC_CTRL		0x04
#define JZ_REG_AIC_I2S_FMT	0x10
#define JZ_REG_AIC_FIFO_STATUS	0x14
#define JZ_REG_AIC_I2S_STATUS	0x1c
#define JZ_REG_AIC_CLK_DIV	0x30
#define JZ_REG_AIC_FIFO		0x34

#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf <<  8)
#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
#define JZ_AIC_CONF_I2S BIT(4)
#define JZ_AIC_CONF_RESET BIT(3)
#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
#define JZ_AIC_CONF_ENABLE BIT(0)

#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
#define JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 24
#define JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 16
#define JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_MASK \
			(0xf << JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET)
#define JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_MASK \
			(0x1f <<  JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET)

#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
#define JZ_AIC_CTRL_FLUSH		BIT(8)
#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)

#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET  16

#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13)
#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
#define JZ_AIC_I2S_FMT_MSB BIT(0)

#define JZ_AIC_I2S_STATUS_BUSY BIT(2)

#define JZ_AIC_CLK_DIV_MASK 0xf
#define I2SDIV_DV_SHIFT 8
#define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT)
#define I2SDIV_IDV_SHIFT 8
#define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT)

enum jz47xx_i2s_version {
	JZ_I2S_JZ4740,
	JZ_I2S_JZ4780,
};

struct jz4740_i2s {
	struct resource *mem;
	void __iomem *base;
	dma_addr_t phys_base;

	struct clk *clk_aic;
	struct clk *clk_i2s;

	struct snd_dmaengine_dai_dma_data playback_dma_data;
	struct snd_dmaengine_dai_dma_data capture_dma_data;

	enum jz47xx_i2s_version version;
};

static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
	unsigned int reg)
{
	return readl(i2s->base + reg);
}

static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
	unsigned int reg, uint32_t value)
{
	writel(value, i2s->base + reg);
}

static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	uint32_t conf, ctrl;

	if (dai->active)
		return 0;

	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
	ctrl |= JZ_AIC_CTRL_FLUSH;
	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);

	clk_prepare_enable(i2s->clk_i2s);

	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	conf |= JZ_AIC_CONF_ENABLE;
	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

	return 0;
}

static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	uint32_t conf;

	if (dai->active)
		return;

	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	conf &= ~JZ_AIC_CONF_ENABLE;
	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

	clk_disable_unprepare(i2s->clk_i2s);
}

static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
	struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	uint32_t ctrl;
	uint32_t mask;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
	else
		mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;

	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		ctrl |= mask;
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		ctrl &= ~mask;
		break;
	default:
		return -EINVAL;
	}

	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);

	return 0;
}

static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	uint32_t format = 0;
	uint32_t conf;

	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);

	conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
		format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
		break;
	case SND_SOC_DAIFMT_CBS_CFM:
		conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_MSB:
		format |= JZ_AIC_I2S_FMT_MSB;
		break;
	case SND_SOC_DAIFMT_I2S:
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		break;
	default:
		return -EINVAL;
	}

	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);

	return 0;
}

static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	unsigned int sample_size;
	uint32_t ctrl, div_reg;
	int div;

	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);

	div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV);
	div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params));

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		sample_size = 0;
		break;
	case SNDRV_PCM_FORMAT_S16:
		sample_size = 1;
		break;
	default:
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
		ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
		if (params_channels(params) == 1)
			ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
		else
			ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;

		div_reg &= ~I2SDIV_DV_MASK;
		div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
	} else {
		ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
		ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;

		if (i2s->version >= JZ_I2S_JZ4780) {
			div_reg &= ~I2SDIV_IDV_MASK;
			div_reg |= (div - 1) << I2SDIV_IDV_SHIFT;
		} else {
			div_reg &= ~I2SDIV_DV_MASK;
			div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
		}
	}

	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
	jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg);

	return 0;
}

static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
	unsigned int freq, int dir)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	struct clk *parent;
	int ret = 0;

	switch (clk_id) {
	case JZ4740_I2S_CLKSRC_EXT:
		parent = clk_get(NULL, "ext");
		clk_set_parent(i2s->clk_i2s, parent);
		break;
	case JZ4740_I2S_CLKSRC_PLL:
		parent = clk_get(NULL, "pll half");
		clk_set_parent(i2s->clk_i2s, parent);
		ret = clk_set_rate(i2s->clk_i2s, freq);
		break;
	default:
		return -EINVAL;
	}
	clk_put(parent);

	return ret;
}

static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	uint32_t conf;

	if (dai->active) {
		conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
		conf &= ~JZ_AIC_CONF_ENABLE;
		jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

		clk_disable_unprepare(i2s->clk_i2s);
	}

	clk_disable_unprepare(i2s->clk_aic);

	return 0;
}

static int jz4740_i2s_resume(struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	uint32_t conf;

	clk_prepare_enable(i2s->clk_aic);

	if (dai->active) {
		clk_prepare_enable(i2s->clk_i2s);

		conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
		conf |= JZ_AIC_CONF_ENABLE;
		jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	}

	return 0;
}

static void jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
{
	struct snd_dmaengine_dai_dma_data *dma_data;

	/* Playback */
	dma_data = &i2s->playback_dma_data;
	dma_data->maxburst = 16;
	dma_data->slave_id = JZ4740_DMA_TYPE_AIC_TRANSMIT;
	dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;

	/* Capture */
	dma_data = &i2s->capture_dma_data;
	dma_data->maxburst = 16;
	dma_data->slave_id = JZ4740_DMA_TYPE_AIC_RECEIVE;
	dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
}

static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	uint32_t conf;

	clk_prepare_enable(i2s->clk_aic);

	jz4740_i2c_init_pcm_config(i2s);
	snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
		&i2s->capture_dma_data);

	if (i2s->version >= JZ_I2S_JZ4780) {
		conf = (7 << JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
			(8 << JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
			JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
			JZ_AIC_CONF_I2S |
			JZ_AIC_CONF_INTERNAL_CODEC;
	} else {
		conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
			(8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
			JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
			JZ_AIC_CONF_I2S |
			JZ_AIC_CONF_INTERNAL_CODEC;
	}

	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

	return 0;
}

static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	clk_disable_unprepare(i2s->clk_aic);
	return 0;
}

static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
	.startup = jz4740_i2s_startup,
	.shutdown = jz4740_i2s_shutdown,
	.trigger = jz4740_i2s_trigger,
	.hw_params = jz4740_i2s_hw_params,
	.set_fmt = jz4740_i2s_set_fmt,
	.set_sysclk = jz4740_i2s_set_sysclk,
};

#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
		SNDRV_PCM_FMTBIT_S16_LE)

static struct snd_soc_dai_driver jz4740_i2s_dai = {
	.probe = jz4740_i2s_dai_probe,
	.remove = jz4740_i2s_dai_remove,
	.playback = {
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = JZ4740_I2S_FMTS,
	},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = JZ4740_I2S_FMTS,
	},
	.symmetric_rates = 1,
	.ops = &jz4740_i2s_dai_ops,
	.suspend = jz4740_i2s_suspend,
	.resume = jz4740_i2s_resume,
};

static struct snd_soc_dai_driver jz4780_i2s_dai = {
	.probe = jz4740_i2s_dai_probe,
	.remove = jz4740_i2s_dai_remove,
	.playback = {
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = JZ4740_I2S_FMTS,
	},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = JZ4740_I2S_FMTS,
	},
	.ops = &jz4740_i2s_dai_ops,
	.suspend = jz4740_i2s_suspend,
	.resume = jz4740_i2s_resume,
};

static const struct snd_soc_component_driver jz4740_i2s_component = {
	.name		= "jz4740-i2s",
};

#ifdef CONFIG_OF
static const struct of_device_id jz4740_of_matches[] = {
	{ .compatible = "ingenic,jz4740-i2s", .data = (void *)JZ_I2S_JZ4740 },
	{ .compatible = "ingenic,jz4780-i2s", .data = (void *)JZ_I2S_JZ4780 },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jz4740_of_matches);
#endif

static int jz4740_i2s_dev_probe(struct platform_device *pdev)
{
	struct jz4740_i2s *i2s;
	struct resource *mem;
	int ret;
	const struct of_device_id *match;

	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
	if (!i2s)
		return -ENOMEM;

	match = of_match_device(jz4740_of_matches, &pdev->dev);
	if (match)
		i2s->version = (enum jz47xx_i2s_version)match->data;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	i2s->base = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(i2s->base))
		return PTR_ERR(i2s->base);

	i2s->phys_base = mem->start;

	i2s->clk_aic = devm_clk_get(&pdev->dev, "aic");
	if (IS_ERR(i2s->clk_aic))
		return PTR_ERR(i2s->clk_aic);

	i2s->clk_i2s = devm_clk_get(&pdev->dev, "i2s");
	if (IS_ERR(i2s->clk_i2s))
		return PTR_ERR(i2s->clk_i2s);

	platform_set_drvdata(pdev, i2s);

	if (i2s->version == JZ_I2S_JZ4780)
		ret = devm_snd_soc_register_component(&pdev->dev,
			&jz4740_i2s_component, &jz4780_i2s_dai, 1);
	else
		ret = devm_snd_soc_register_component(&pdev->dev,
			&jz4740_i2s_component, &jz4740_i2s_dai, 1);

	if (ret)
		return ret;

	return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
		SND_DMAENGINE_PCM_FLAG_COMPAT);
}

static struct platform_driver jz4740_i2s_driver = {
	.probe = jz4740_i2s_dev_probe,
	.driver = {
		.name = "jz4740-i2s",
		.of_match_table = of_match_ptr(jz4740_of_matches)
	},
};

module_platform_driver(jz4740_i2s_driver);

MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:jz4740-i2s");
Commit	Line	Data
11bd3dd1 LPC	1	/*
	2	* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the
	6	* Free Software Foundation; either version 2 of the License, or (at your
	7	* option) any later version.
	8	*
	9	* You should have received a copy of the GNU General Public License along
	10	* with this program; if not, write to the Free Software Foundation, Inc.,
	11	* 675 Mass Ave, Cambridge, MA 02139, USA.
	12	*
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/io.h>
f2610571 ZLK	17	#include <linux/of.h>
f2610571 ZLK	18	#include <linux/of_device.h>
11bd3dd1 LPC	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/slab.h>
	23
	24	#include <linux/clk.h>
	25	#include <linux/delay.h>
	26
	27	#include <linux/dma-mapping.h>
	28
	29	#include <sound/core.h>
	30	#include <sound/pcm.h>
	31	#include <sound/pcm_params.h>
	32	#include <sound/soc.h>
11bd3dd1	33	#include <sound/initval.h>
0406a40a LPC	34	#include <sound/dmaengine_pcm.h>
0406a40a LPC	35
11bd3dd1	36	#include "jz4740-i2s.h"
11bd3dd1	37
0aa2a15a LPC	38	#define JZ4740_DMA_TYPE_AIC_TRANSMIT 24
	39	#define JZ4740_DMA_TYPE_AIC_RECEIVE 25
	40
11bd3dd1 LPC	41	#define JZ_REG_AIC_CONF 0x00
	42	#define JZ_REG_AIC_CTRL 0x04
	43	#define JZ_REG_AIC_I2S_FMT 0x10
	44	#define JZ_REG_AIC_FIFO_STATUS 0x14
	45	#define JZ_REG_AIC_I2S_STATUS 0x1c
	46	#define JZ_REG_AIC_CLK_DIV 0x30
	47	#define JZ_REG_AIC_FIFO 0x34
	48
	49	#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
	50	#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8)
	51	#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
	52	#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
	53	#define JZ_AIC_CONF_I2S BIT(4)
	54	#define JZ_AIC_CONF_RESET BIT(3)
	55	#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
	56	#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
	57	#define JZ_AIC_CONF_ENABLE BIT(0)
	58
	59	#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
	60	#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
967beb2e ZLK	61	#define JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 24
	62	#define JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 16
	63	#define JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_MASK \
	64	(0xf << JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET)
	65	#define JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_MASK \
	66	(0x1f << JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET)
11bd3dd1 LPC	67
	68	#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
	69	#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
	70	#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
	71	#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
	72	#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
	73	#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
	74	#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
	75	#define JZ_AIC_CTRL_FLUSH BIT(8)
	76	#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
	77	#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
	78	#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
	79	#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
	80	#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
	81	#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
	82	#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
	83
	84	#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
	85	#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16
	86
	87	#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
967beb2e	88	#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13)
11bd3dd1 LPC	89	#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
	90	#define JZ_AIC_I2S_FMT_MSB BIT(0)
	91
	92	#define JZ_AIC_I2S_STATUS_BUSY BIT(2)
	93
	94	#define JZ_AIC_CLK_DIV_MASK 0xf
26b0aad8 ZLK	95	#define I2SDIV_DV_SHIFT 8
26b0aad8 ZLK	96	#define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT)
967beb2e ZLK	97	#define I2SDIV_IDV_SHIFT 8
	98	#define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT)
	99
	100	enum jz47xx_i2s_version {
	101	JZ_I2S_JZ4740,
	102	JZ_I2S_JZ4780,
	103	};
11bd3dd1 LPC	104
	105	struct jz4740_i2s {
	106	struct resource *mem;
	107	void __iomem *base;
	108	dma_addr_t phys_base;
	109
	110	struct clk *clk_aic;
	111	struct clk *clk_i2s;
	112
0406a40a LPC	113	struct snd_dmaengine_dai_dma_data playback_dma_data;
0406a40a LPC	114	struct snd_dmaengine_dai_dma_data capture_dma_data;
967beb2e ZLK	115
967beb2e ZLK	116	enum jz47xx_i2s_version version;
11bd3dd1 LPC	117	};
	118
	119	static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
	120	unsigned int reg)
	121	{
	122	return readl(i2s->base + reg);
	123	}
	124
	125	static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
	126	unsigned int reg, uint32_t value)
	127	{
	128	writel(value, i2s->base + reg);
	129	}
	130
11bd3dd1 LPC	131	static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
	132	struct snd_soc_dai *dai)
	133	{
f0fba2ad	134	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	135	uint32_t conf, ctrl;
	136
	137	if (dai->active)
	138	return 0;
	139
	140	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
	141	ctrl \|= JZ_AIC_CTRL_FLUSH;
	142	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
	143
010187fb	144	clk_prepare_enable(i2s->clk_i2s);
11bd3dd1 LPC	145
	146	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	147	conf \|= JZ_AIC_CONF_ENABLE;
	148	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	149
	150	return 0;
	151	}
	152
	153	static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
	154	struct snd_soc_dai *dai)
	155	{
f0fba2ad	156	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	157	uint32_t conf;
11bd3dd1 LPC	158
005967a1	159	if (dai->active)
11bd3dd1 LPC	160	return;
	161
	162	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	163	conf &= ~JZ_AIC_CONF_ENABLE;
	164	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	165
010187fb	166	clk_disable_unprepare(i2s->clk_i2s);
11bd3dd1 LPC	167	}
	168
	169	static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
	170	struct snd_soc_dai *dai)
	171	{
f0fba2ad	172	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	173
	174	uint32_t ctrl;
	175	uint32_t mask;
	176
	177	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	178	mask = JZ_AIC_CTRL_ENABLE_PLAYBACK \| JZ_AIC_CTRL_ENABLE_TX_DMA;
	179	else
	180	mask = JZ_AIC_CTRL_ENABLE_CAPTURE \| JZ_AIC_CTRL_ENABLE_RX_DMA;
	181
	182	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
	183
	184	switch (cmd) {
	185	case SNDRV_PCM_TRIGGER_START:
	186	case SNDRV_PCM_TRIGGER_RESUME:
	187	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	188	ctrl \|= mask;
	189	break;
	190	case SNDRV_PCM_TRIGGER_STOP:
	191	case SNDRV_PCM_TRIGGER_SUSPEND:
	192	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	193	ctrl &= ~mask;
	194	break;
	195	default:
	196	return -EINVAL;
	197	}
	198
	199	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
	200
	201	return 0;
	202	}
	203
	204	static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
	205	{
f0fba2ad	206	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	207
	208	uint32_t format = 0;
	209	uint32_t conf;
	210
	211	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	212
	213	conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER \| JZ_AIC_CONF_SYNC_CLK_MASTER);
	214
	215	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	216	case SND_SOC_DAIFMT_CBS_CFS:
	217	conf \|= JZ_AIC_CONF_BIT_CLK_MASTER \| JZ_AIC_CONF_SYNC_CLK_MASTER;
	218	format \|= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
	219	break;
	220	case SND_SOC_DAIFMT_CBM_CFS:
	221	conf \|= JZ_AIC_CONF_SYNC_CLK_MASTER;
	222	break;
	223	case SND_SOC_DAIFMT_CBS_CFM:
	224	conf \|= JZ_AIC_CONF_BIT_CLK_MASTER;
	225	break;
	226	case SND_SOC_DAIFMT_CBM_CFM:
	227	break;
	228	default:
	229	return -EINVAL;
	230	}
	231
	232	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	233	case SND_SOC_DAIFMT_MSB:
	234	format \|= JZ_AIC_I2S_FMT_MSB;
	235	break;
	236	case SND_SOC_DAIFMT_I2S:
	237	break;
	238	default:
	239	return -EINVAL;
	240	}
	241
	242	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	243	case SND_SOC_DAIFMT_NB_NF:
	244	break;
	245	default:
	246	return -EINVAL;
	247	}
	248
	249	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	250	jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
	251
	252	return 0;
	253	}
	254
	255	static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
	256	struct snd_pcm_hw_params params, struct snd_soc_dai dai)
	257	{
f0fba2ad	258	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1	259	unsigned int sample_size;
26b0aad8 ZLK	260	uint32_t ctrl, div_reg;
26b0aad8 ZLK	261	int div;
11bd3dd1 LPC	262
	263	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
	264
26b0aad8 ZLK	265	div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV);
	266	div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params));
	267
11bd3dd1 LPC	268	switch (params_format(params)) {
	269	case SNDRV_PCM_FORMAT_S8:
	270	sample_size = 0;
11bd3dd1 LPC	271	break;
	272	case SNDRV_PCM_FORMAT_S16:
	273	sample_size = 1;
11bd3dd1 LPC	274	break;
	275	default:
	276	return -EINVAL;
	277	}
	278
	279	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	280	ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
	281	ctrl \|= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
	282	if (params_channels(params) == 1)
	283	ctrl \|= JZ_AIC_CTRL_MONO_TO_STEREO;
	284	else
	285	ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
967beb2e ZLK	286
	287	div_reg &= ~I2SDIV_DV_MASK;
	288	div_reg \|= (div - 1) << I2SDIV_DV_SHIFT;
11bd3dd1 LPC	289	} else {
	290	ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
	291	ctrl \|= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
967beb2e ZLK	292
	293	if (i2s->version >= JZ_I2S_JZ4780) {
	294	div_reg &= ~I2SDIV_IDV_MASK;
	295	div_reg \|= (div - 1) << I2SDIV_IDV_SHIFT;
	296	} else {
	297	div_reg &= ~I2SDIV_DV_MASK;
	298	div_reg \|= (div - 1) << I2SDIV_DV_SHIFT;
	299	}
11bd3dd1 LPC	300	}
	301
	302	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
26b0aad8	303	jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg);
11bd3dd1	304
11bd3dd1 LPC	305	return 0;
	306	}
	307
	308	static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
	309	unsigned int freq, int dir)
	310	{
f0fba2ad	311	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	312	struct clk *parent;
	313	int ret = 0;
	314
	315	switch (clk_id) {
	316	case JZ4740_I2S_CLKSRC_EXT:
	317	parent = clk_get(NULL, "ext");
	318	clk_set_parent(i2s->clk_i2s, parent);
	319	break;
	320	case JZ4740_I2S_CLKSRC_PLL:
	321	parent = clk_get(NULL, "pll half");
	322	clk_set_parent(i2s->clk_i2s, parent);
	323	ret = clk_set_rate(i2s->clk_i2s, freq);
	324	break;
	325	default:
	326	return -EINVAL;
	327	}
	328	clk_put(parent);
	329
	330	return ret;
	331	}
	332
	333	static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
	334	{
f0fba2ad	335	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	336	uint32_t conf;
	337
	338	if (dai->active) {
	339	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	340	conf &= ~JZ_AIC_CONF_ENABLE;
	341	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	342
010187fb	343	clk_disable_unprepare(i2s->clk_i2s);
11bd3dd1 LPC	344	}
11bd3dd1 LPC	345
010187fb	346	clk_disable_unprepare(i2s->clk_aic);
11bd3dd1 LPC	347
	348	return 0;
	349	}
	350
	351	static int jz4740_i2s_resume(struct snd_soc_dai *dai)
	352	{
f0fba2ad	353	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	354	uint32_t conf;
11bd3dd1 LPC	355
010187fb	356	clk_prepare_enable(i2s->clk_aic);
11bd3dd1 LPC	357
11bd3dd1 LPC	358	if (dai->active) {
010187fb	359	clk_prepare_enable(i2s->clk_i2s);
11bd3dd1 LPC	360
	361	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	362	conf \|= JZ_AIC_CONF_ENABLE;
	363	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	364	}
	365
	366	return 0;
	367	}
	368
f0fba2ad	369	static void jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
11bd3dd1	370	{
0406a40a	371	struct snd_dmaengine_dai_dma_data *dma_data;
f0fba2ad LG	372
f0fba2ad LG	373	/* Playback */
0406a40a LPC	374	dma_data = &i2s->playback_dma_data;
	375	dma_data->maxburst = 16;
	376	dma_data->slave_id = JZ4740_DMA_TYPE_AIC_TRANSMIT;
	377	dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
f0fba2ad LG	378
f0fba2ad LG	379	/* Capture */
0406a40a LPC	380	dma_data = &i2s->capture_dma_data;
	381	dma_data->maxburst = 16;
	382	dma_data->slave_id = JZ4740_DMA_TYPE_AIC_RECEIVE;
	383	dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
f0fba2ad LG	384	}
	385
	386	static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
	387	{
	388	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	389	uint32_t conf;
11bd3dd1 LPC	390
010187fb	391	clk_prepare_enable(i2s->clk_aic);
f0fba2ad LG	392
f0fba2ad LG	393	jz4740_i2c_init_pcm_config(i2s);
0406a40a LPC	394	snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
0406a40a LPC	395	&i2s->capture_dma_data);
f0fba2ad	396
967beb2e ZLK	397	if (i2s->version >= JZ_I2S_JZ4780) {
	398	conf = (7 << JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) \|
	399	(8 << JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) \|
	400	JZ_AIC_CONF_OVERFLOW_PLAY_LAST \|
	401	JZ_AIC_CONF_I2S \|
	402	JZ_AIC_CONF_INTERNAL_CODEC;
	403	} else {
	404	conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) \|
	405	(8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) \|
	406	JZ_AIC_CONF_OVERFLOW_PLAY_LAST \|
	407	JZ_AIC_CONF_I2S \|
	408	JZ_AIC_CONF_INTERNAL_CODEC;
	409	}
11bd3dd1 LPC	410
	411	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
	412	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	413
	414	return 0;
	415	}
	416
f0fba2ad LG	417	static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
	418	{
	419	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	420
010187fb	421	clk_disable_unprepare(i2s->clk_aic);
f0fba2ad LG	422	return 0;
	423	}
	424
85e7652d	425	static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
11bd3dd1 LPC	426	.startup = jz4740_i2s_startup,
	427	.shutdown = jz4740_i2s_shutdown,
	428	.trigger = jz4740_i2s_trigger,
	429	.hw_params = jz4740_i2s_hw_params,
	430	.set_fmt = jz4740_i2s_set_fmt,
	431	.set_sysclk = jz4740_i2s_set_sysclk,
	432	};
	433
	434	#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 \| \
	435	SNDRV_PCM_FMTBIT_S16_LE)
	436
f0fba2ad LG	437	static struct snd_soc_dai_driver jz4740_i2s_dai = {
	438	.probe = jz4740_i2s_dai_probe,
	439	.remove = jz4740_i2s_dai_remove,
11bd3dd1 LPC	440	.playback = {
	441	.channels_min = 1,
	442	.channels_max = 2,
	443	.rates = SNDRV_PCM_RATE_8000_48000,
	444	.formats = JZ4740_I2S_FMTS,
	445	},
	446	.capture = {
	447	.channels_min = 2,
	448	.channels_max = 2,
	449	.rates = SNDRV_PCM_RATE_8000_48000,
	450	.formats = JZ4740_I2S_FMTS,
	451	},
	452	.symmetric_rates = 1,
	453	.ops = &jz4740_i2s_dai_ops,
	454	.suspend = jz4740_i2s_suspend,
	455	.resume = jz4740_i2s_resume,
	456	};
11bd3dd1	457
967beb2e ZLK	458	static struct snd_soc_dai_driver jz4780_i2s_dai = {
	459	.probe = jz4740_i2s_dai_probe,
	460	.remove = jz4740_i2s_dai_remove,
	461	.playback = {
	462	.channels_min = 1,
	463	.channels_max = 2,
	464	.rates = SNDRV_PCM_RATE_8000_48000,
	465	.formats = JZ4740_I2S_FMTS,
	466	},
	467	.capture = {
	468	.channels_min = 2,
	469	.channels_max = 2,
	470	.rates = SNDRV_PCM_RATE_8000_48000,
	471	.formats = JZ4740_I2S_FMTS,
	472	},
	473	.ops = &jz4740_i2s_dai_ops,
	474	.suspend = jz4740_i2s_suspend,
	475	.resume = jz4740_i2s_resume,
	476	};
	477
29cc15cf KM	478	static const struct snd_soc_component_driver jz4740_i2s_component = {
	479	.name = "jz4740-i2s",
	480	};
	481
f2610571 ZLK	482	#ifdef CONFIG_OF
f2610571 ZLK	483	static const struct of_device_id jz4740_of_matches[] = {
967beb2e ZLK	484	{ .compatible = "ingenic,jz4740-i2s", .data = (void *)JZ_I2S_JZ4740 },
967beb2e ZLK	485	{ .compatible = "ingenic,jz4780-i2s", .data = (void *)JZ_I2S_JZ4780 },
f2610571 ZLK	486	{ /* sentinel */ }
f2610571 ZLK	487	};
27fcf913	488	MODULE_DEVICE_TABLE(of, jz4740_of_matches);
f2610571 ZLK	489	#endif
f2610571 ZLK	490
d6a29e3d	491	static int jz4740_i2s_dev_probe(struct platform_device *pdev)
11bd3dd1 LPC	492	{
11bd3dd1 LPC	493	struct jz4740_i2s *i2s;
b84c9ce8	494	struct resource *mem;
11bd3dd1	495	int ret;
967beb2e	496	const struct of_device_id *match;
11bd3dd1	497
b84c9ce8	498	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
11bd3dd1 LPC	499	if (!i2s)
	500	return -ENOMEM;
	501
967beb2e ZLK	502	match = of_match_device(jz4740_of_matches, &pdev->dev);
	503	if (match)
	504	i2s->version = (enum jz47xx_i2s_version)match->data;
	505
b84c9ce8 LPC	506	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	507	i2s->base = devm_ioremap_resource(&pdev->dev, mem);
	508	if (IS_ERR(i2s->base))
	509	return PTR_ERR(i2s->base);
11bd3dd1	510
b84c9ce8	511	i2s->phys_base = mem->start;
11bd3dd1	512
b84c9ce8 LPC	513	i2s->clk_aic = devm_clk_get(&pdev->dev, "aic");
	514	if (IS_ERR(i2s->clk_aic))
	515	return PTR_ERR(i2s->clk_aic);
11bd3dd1	516
b84c9ce8 LPC	517	i2s->clk_i2s = devm_clk_get(&pdev->dev, "i2s");
	518	if (IS_ERR(i2s->clk_i2s))
	519	return PTR_ERR(i2s->clk_i2s);
11bd3dd1	520
f0fba2ad	521	platform_set_drvdata(pdev, i2s);
11bd3dd1	522
967beb2e ZLK	523	if (i2s->version == JZ_I2S_JZ4780)
	524	ret = devm_snd_soc_register_component(&pdev->dev,
	525	&jz4740_i2s_component, &jz4780_i2s_dai, 1);
	526	else
	527	ret = devm_snd_soc_register_component(&pdev->dev,
	528	&jz4740_i2s_component, &jz4740_i2s_dai, 1);
	529
0406a40a LPC	530	if (ret)
	531	return ret;
	532
	533	return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
	534	SND_DMAENGINE_PCM_FLAG_COMPAT);
11bd3dd1 LPC	535	}
	536
	537	static struct platform_driver jz4740_i2s_driver = {
	538	.probe = jz4740_i2s_dev_probe,
11bd3dd1 LPC	539	.driver = {
11bd3dd1 LPC	540	.name = "jz4740-i2s",
f2610571	541	.of_match_table = of_match_ptr(jz4740_of_matches)
11bd3dd1 LPC	542	},
	543	};
	544
c32986e6	545	module_platform_driver(jz4740_i2s_driver);
11bd3dd1 LPC	546
	547	MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
	548	MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
	549	MODULE_LICENSE("GPL");
	550	MODULE_ALIAS("platform:jz4740-i2s");