[deliverable/linux.git] / sound / soc / jz4740 / jz4740-i2s.c

/*
 *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under  the terms of the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <linux/clk.h>
#include <linux/delay.h>

#include <linux/dma-mapping.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>

#include "jz4740-i2s.h"
#include "jz4740-pcm.h"

#define JZ_REG_AIC_CONF		0x00
#define JZ_REG_AIC_CTRL		0x04
#define JZ_REG_AIC_I2S_FMT	0x10
#define JZ_REG_AIC_FIFO_STATUS	0x14
#define JZ_REG_AIC_I2S_STATUS	0x1c
#define JZ_REG_AIC_CLK_DIV	0x30
#define JZ_REG_AIC_FIFO		0x34

#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf <<  8)
#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
#define JZ_AIC_CONF_I2S BIT(4)
#define JZ_AIC_CONF_RESET BIT(3)
#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
#define JZ_AIC_CONF_ENABLE BIT(0)

#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8

#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
#define JZ_AIC_CTRL_FLUSH		BIT(8)
#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)

#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET  16

#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
#define JZ_AIC_I2S_FMT_MSB BIT(0)

#define JZ_AIC_I2S_STATUS_BUSY BIT(2)

#define JZ_AIC_CLK_DIV_MASK 0xf

struct jz4740_i2s {
	struct resource *mem;
	void __iomem *base;
	dma_addr_t phys_base;

	struct clk *clk_aic;
	struct clk *clk_i2s;

	struct jz4740_pcm_config pcm_config_playback;
	struct jz4740_pcm_config pcm_config_capture;
};

static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
	unsigned int reg)
{
	return readl(i2s->base + reg);
}

static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
	unsigned int reg, uint32_t value)
{
	writel(value, i2s->base + reg);
}

static inline struct jz4740_i2s *jz4740_dai_to_i2s(struct snd_soc_dai *dai)
{
	return dai->private_data;
}

static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
	uint32_t conf, ctrl;

	if (dai->active)
		return 0;

	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
	ctrl |= JZ_AIC_CTRL_FLUSH;
	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);

	clk_enable(i2s->clk_i2s);

	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	conf |= JZ_AIC_CONF_ENABLE;
	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

	return 0;
}

static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
	uint32_t conf;

	if (!dai->active)
		return;

	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	conf &= ~JZ_AIC_CONF_ENABLE;
	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

	clk_disable(i2s->clk_i2s);
}

static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
	struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);

	uint32_t ctrl;
	uint32_t mask;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
	else
		mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;

	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		ctrl |= mask;
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		ctrl &= ~mask;
		break;
	default:
		return -EINVAL;
	}

	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);

	return 0;
}

static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);

	uint32_t format = 0;
	uint32_t conf;

	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);

	conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
		format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
		break;
	case SND_SOC_DAIFMT_CBS_CFM:
		conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_MSB:
		format |= JZ_AIC_I2S_FMT_MSB;
		break;
	case SND_SOC_DAIFMT_I2S:
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		break;
	default:
		return -EINVAL;
	}

	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);

	return 0;
}

static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
	enum jz4740_dma_width dma_width;
	struct jz4740_pcm_config *pcm_config;
	unsigned int sample_size;
	uint32_t ctrl;

	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		sample_size = 0;
		dma_width = JZ4740_DMA_WIDTH_8BIT;
		break;
	case SNDRV_PCM_FORMAT_S16:
		sample_size = 1;
		dma_width = JZ4740_DMA_WIDTH_16BIT;
		break;
	default:
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
		ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
		if (params_channels(params) == 1)
			ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
		else
			ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;

		pcm_config = &i2s->pcm_config_playback;
		pcm_config->dma_config.dst_width = dma_width;

	} else {
		ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
		ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;

		pcm_config = &i2s->pcm_config_capture;
		pcm_config->dma_config.src_width = dma_width;
	}

	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);

	snd_soc_dai_set_dma_data(dai, substream, pcm_config);

	return 0;
}

static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
	unsigned int freq, int dir)
{
	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
	struct clk *parent;
	int ret = 0;

	switch (clk_id) {
	case JZ4740_I2S_CLKSRC_EXT:
		parent = clk_get(NULL, "ext");
		clk_set_parent(i2s->clk_i2s, parent);
		break;
	case JZ4740_I2S_CLKSRC_PLL:
		parent = clk_get(NULL, "pll half");
		clk_set_parent(i2s->clk_i2s, parent);
		ret = clk_set_rate(i2s->clk_i2s, freq);
		break;
	default:
		return -EINVAL;
	}
	clk_put(parent);

	return ret;
}

static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
	uint32_t conf;

	if (dai->active) {
		conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
		conf &= ~JZ_AIC_CONF_ENABLE;
		jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

		clk_disable(i2s->clk_i2s);
	}

	clk_disable(i2s->clk_aic);

	return 0;
}

static int jz4740_i2s_resume(struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
	uint32_t conf;

	clk_enable(i2s->clk_aic);

	if (dai->active) {
		clk_enable(i2s->clk_i2s);

		conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
		conf |= JZ_AIC_CONF_ENABLE;
		jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	}

	return 0;
}

static int jz4740_i2s_probe(struct platform_device *pdev, struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
	uint32_t conf;

	conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
		(8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
		JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
		JZ_AIC_CONF_I2S |
		JZ_AIC_CONF_INTERNAL_CODEC;

	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

	return 0;
}

static struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
	.startup = jz4740_i2s_startup,
	.shutdown = jz4740_i2s_shutdown,
	.trigger = jz4740_i2s_trigger,
	.hw_params = jz4740_i2s_hw_params,
	.set_fmt = jz4740_i2s_set_fmt,
	.set_sysclk = jz4740_i2s_set_sysclk,
};

#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
		SNDRV_PCM_FMTBIT_S16_LE)

struct snd_soc_dai jz4740_i2s_dai = {
	.name = "jz4740-i2s",
	.probe = jz4740_i2s_probe,
	.playback = {
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = JZ4740_I2S_FMTS,
	},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = JZ4740_I2S_FMTS,
	},
	.symmetric_rates = 1,
	.ops = &jz4740_i2s_dai_ops,
	.suspend = jz4740_i2s_suspend,
	.resume = jz4740_i2s_resume,
};
EXPORT_SYMBOL_GPL(jz4740_i2s_dai);

static void __devinit jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
{
	struct jz4740_dma_config *dma_config;

	/* Playback */
	dma_config = &i2s->pcm_config_playback.dma_config;
	dma_config->src_width = JZ4740_DMA_WIDTH_32BIT,
	dma_config->transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE;
	dma_config->request_type = JZ4740_DMA_TYPE_AIC_TRANSMIT;
	dma_config->flags = JZ4740_DMA_SRC_AUTOINC;
	dma_config->mode = JZ4740_DMA_MODE_SINGLE;
	i2s->pcm_config_playback.fifo_addr = i2s->phys_base + JZ_REG_AIC_FIFO;

	/* Capture */
	dma_config = &i2s->pcm_config_capture.dma_config;
	dma_config->dst_width = JZ4740_DMA_WIDTH_32BIT,
	dma_config->transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE;
	dma_config->request_type = JZ4740_DMA_TYPE_AIC_RECEIVE;
	dma_config->flags = JZ4740_DMA_DST_AUTOINC;
	dma_config->mode = JZ4740_DMA_MODE_SINGLE;
	i2s->pcm_config_capture.fifo_addr = i2s->phys_base + JZ_REG_AIC_FIFO;
}

static int __devinit jz4740_i2s_dev_probe(struct platform_device *pdev)
{
	struct jz4740_i2s *i2s;
	int ret;

	i2s = kzalloc(sizeof(*i2s), GFP_KERNEL);

	if (!i2s)
		return -ENOMEM;

	i2s->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!i2s->mem) {
		ret = -ENOENT;
		goto err_free;
	}

	i2s->mem = request_mem_region(i2s->mem->start, resource_size(i2s->mem),
				pdev->name);
	if (!i2s->mem) {
		ret = -EBUSY;
		goto err_free;
	}

	i2s->base = ioremap_nocache(i2s->mem->start, resource_size(i2s->mem));
	if (!i2s->base) {
		ret = -EBUSY;
		goto err_release_mem_region;
	}

	i2s->phys_base = i2s->mem->start;

	i2s->clk_aic = clk_get(&pdev->dev, "aic");
	if (IS_ERR(i2s->clk_aic)) {
		ret = PTR_ERR(i2s->clk_aic);
		goto err_iounmap;
	}

	i2s->clk_i2s = clk_get(&pdev->dev, "i2s");
	if (IS_ERR(i2s->clk_i2s)) {
		ret = PTR_ERR(i2s->clk_i2s);
		goto err_clk_put_aic;
	}

	clk_enable(i2s->clk_aic);

	jz4740_i2c_init_pcm_config(i2s);

	jz4740_i2s_dai.private_data = i2s;
	ret = snd_soc_register_dai(&jz4740_i2s_dai);

	if (ret) {
		dev_err(&pdev->dev, "Failed to register DAI\n");
		goto err_clk_put_i2s;
	}

	platform_set_drvdata(pdev, i2s);

	return 0;

err_clk_put_i2s:
	clk_disable(i2s->clk_aic);
	clk_put(i2s->clk_i2s);
err_clk_put_aic:
	clk_put(i2s->clk_aic);
err_iounmap:
	iounmap(i2s->base);
err_release_mem_region:
	release_mem_region(i2s->mem->start, resource_size(i2s->mem));
err_free:
	kfree(i2s);

	return ret;
}

static int __devexit jz4740_i2s_dev_remove(struct platform_device *pdev)
{
	struct jz4740_i2s *i2s = platform_get_drvdata(pdev);

	snd_soc_unregister_dai(&jz4740_i2s_dai);

	clk_disable(i2s->clk_aic);
	clk_put(i2s->clk_i2s);
	clk_put(i2s->clk_aic);

	iounmap(i2s->base);
	release_mem_region(i2s->mem->start, resource_size(i2s->mem));

	platform_set_drvdata(pdev, NULL);
	kfree(i2s);

	return 0;
}

static struct platform_driver jz4740_i2s_driver = {
	.probe = jz4740_i2s_dev_probe,
	.remove = __devexit_p(jz4740_i2s_dev_remove),
	.driver = {
		.name = "jz4740-i2s",
		.owner = THIS_MODULE,
	},
};

static int __init jz4740_i2s_init(void)
{
	return platform_driver_register(&jz4740_i2s_driver);
}
module_init(jz4740_i2s_init);

static void __exit jz4740_i2s_exit(void)
{
	platform_driver_unregister(&jz4740_i2s_driver);
}
module_exit(jz4740_i2s_exit);

MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:jz4740-i2s");
Commit	Line	Data
11bd3dd1 LPC	1	/*
	2	* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the
	6	* Free Software Foundation; either version 2 of the License, or (at your
	7	* option) any later version.
	8	*
	9	* You should have received a copy of the GNU General Public License along
	10	* with this program; if not, write to the Free Software Foundation, Inc.,
	11	* 675 Mass Ave, Cambridge, MA 02139, USA.
	12	*
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/io.h>
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/slab.h>
	21
	22	#include <linux/clk.h>
	23	#include <linux/delay.h>
	24
	25	#include <linux/dma-mapping.h>
	26
	27	#include <sound/core.h>
	28	#include <sound/pcm.h>
	29	#include <sound/pcm_params.h>
	30	#include <sound/soc.h>
	31	#include <sound/soc-dapm.h>
	32	#include <sound/initval.h>
	33
	34	#include "jz4740-i2s.h"
	35	#include "jz4740-pcm.h"
	36
	37	#define JZ_REG_AIC_CONF 0x00
	38	#define JZ_REG_AIC_CTRL 0x04
	39	#define JZ_REG_AIC_I2S_FMT 0x10
	40	#define JZ_REG_AIC_FIFO_STATUS 0x14
	41	#define JZ_REG_AIC_I2S_STATUS 0x1c
	42	#define JZ_REG_AIC_CLK_DIV 0x30
	43	#define JZ_REG_AIC_FIFO 0x34
	44
	45	#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
	46	#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8)
	47	#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
	48	#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
	49	#define JZ_AIC_CONF_I2S BIT(4)
	50	#define JZ_AIC_CONF_RESET BIT(3)
	51	#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
	52	#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
	53	#define JZ_AIC_CONF_ENABLE BIT(0)
	54
	55	#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
	56	#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
	57
	58	#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
	59	#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
	60	#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
	61	#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
	62	#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
	63	#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
	64	#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
65	#define JZ_AIC_CTRL_FLUSH BIT(8)
66	#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
67	#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
68	#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
69	#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
70	#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
71	#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
72	#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
73
74	#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
75	#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16
76
77	#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
78	#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
79	#define JZ_AIC_I2S_FMT_MSB BIT(0)
80
81	#define JZ_AIC_I2S_STATUS_BUSY BIT(2)
82
83	#define JZ_AIC_CLK_DIV_MASK 0xf
84
85	struct jz4740_i2s {
86	struct resource *mem;
87	void __iomem *base;
88	dma_addr_t phys_base;
89
90	struct clk *clk_aic;
91	struct clk *clk_i2s;
92
93	struct jz4740_pcm_config pcm_config_playback;
94	struct jz4740_pcm_config pcm_config_capture;
95	};
96
97	static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
98	unsigned int reg)
99	{
100	return readl(i2s->base + reg);
101	}
102
103	static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
104	unsigned int reg, uint32_t value)
105	{
106	writel(value, i2s->base + reg);
107	}
108
109	static inline struct jz4740_i2s jz4740_dai_to_i2s(struct snd_soc_dai dai)
110	{
111	return dai->private_data;
112	}
113
114	static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
115	struct snd_soc_dai *dai)
116	{
117	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
118	uint32_t conf, ctrl;
119
120	if (dai->active)
121	return 0;
122
123	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
124	ctrl \|= JZ_AIC_CTRL_FLUSH;
125	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
126
127	clk_enable(i2s->clk_i2s);
128
129	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
130	conf \|= JZ_AIC_CONF_ENABLE;
131	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
132
133	return 0;
134	}
135
136	static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
137	struct snd_soc_dai *dai)
138	{
139	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
140	uint32_t conf;
141
142	if (!dai->active)
143	return;
144
145	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
146	conf &= ~JZ_AIC_CONF_ENABLE;
147	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
148
149	clk_disable(i2s->clk_i2s);
150	}
151
152	static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
153	struct snd_soc_dai *dai)
154	{
155	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
156
157	uint32_t ctrl;
158	uint32_t mask;
159
160	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
161	mask = JZ_AIC_CTRL_ENABLE_PLAYBACK \| JZ_AIC_CTRL_ENABLE_TX_DMA;
162	else
163	mask = JZ_AIC_CTRL_ENABLE_CAPTURE \| JZ_AIC_CTRL_ENABLE_RX_DMA;
164
165	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
166
167	switch (cmd) {
168	case SNDRV_PCM_TRIGGER_START:
169	case SNDRV_PCM_TRIGGER_RESUME:
170	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
171	ctrl \|= mask;
172	break;
173	case SNDRV_PCM_TRIGGER_STOP:
174	case SNDRV_PCM_TRIGGER_SUSPEND:
175	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
176	ctrl &= ~mask;
177	break;
178	default:
179	return -EINVAL;
180	}
181
182	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
183
184	return 0;
185	}
186
187	static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
188	{
189	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
190
191	uint32_t format = 0;
192	uint32_t conf;
193
194	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
195
196	conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER \| JZ_AIC_CONF_SYNC_CLK_MASTER);
197
198	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
199	case SND_SOC_DAIFMT_CBS_CFS:
200	conf \|= JZ_AIC_CONF_BIT_CLK_MASTER \| JZ_AIC_CONF_SYNC_CLK_MASTER;
201	format \|= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
202	break;
203	case SND_SOC_DAIFMT_CBM_CFS:
204	conf \|= JZ_AIC_CONF_SYNC_CLK_MASTER;
205	break;
206	case SND_SOC_DAIFMT_CBS_CFM:
207	conf \|= JZ_AIC_CONF_BIT_CLK_MASTER;
208	break;
209	case SND_SOC_DAIFMT_CBM_CFM:
210	break;
211	default:
212	return -EINVAL;
213	}
214
215	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
216	case SND_SOC_DAIFMT_MSB:
217	format \|= JZ_AIC_I2S_FMT_MSB;
218	break;
219	case SND_SOC_DAIFMT_I2S:
220	break;
221	default:
222	return -EINVAL;
223	}
224
225	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
226	case SND_SOC_DAIFMT_NB_NF:
227	break;
228	default:
229	return -EINVAL;
230	}
231
232	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
233	jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
234
235	return 0;
236	}
237
238	static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
239	struct snd_pcm_hw_params params, struct snd_soc_dai dai)
240	{
241	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
242	enum jz4740_dma_width dma_width;
243	struct jz4740_pcm_config *pcm_config;
244	unsigned int sample_size;
245	uint32_t ctrl;
246
247	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
248
249	switch (params_format(params)) {
250	case SNDRV_PCM_FORMAT_S8:
251	sample_size = 0;
252	dma_width = JZ4740_DMA_WIDTH_8BIT;
253	break;
254	case SNDRV_PCM_FORMAT_S16:
255	sample_size = 1;
256	dma_width = JZ4740_DMA_WIDTH_16BIT;
257	break;
258	default:
259	return -EINVAL;
260	}
261
262	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
263	ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
264	ctrl \|= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
265	if (params_channels(params) == 1)
266	ctrl \|= JZ_AIC_CTRL_MONO_TO_STEREO;
267	else
268	ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
269
270	pcm_config = &i2s->pcm_config_playback;
271	pcm_config->dma_config.dst_width = dma_width;
272
273	} else {
274	ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
275	ctrl \|= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
276
277	pcm_config = &i2s->pcm_config_capture;
278	pcm_config->dma_config.src_width = dma_width;
279	}
280
281	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
282
283	snd_soc_dai_set_dma_data(dai, substream, pcm_config);
284
285	return 0;
286	}
287
288	static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
289	unsigned int freq, int dir)
290	{
291	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
292	struct clk *parent;
293	int ret = 0;
294
295	switch (clk_id) {
296	case JZ4740_I2S_CLKSRC_EXT:
297	parent = clk_get(NULL, "ext");
298	clk_set_parent(i2s->clk_i2s, parent);
299	break;
300	case JZ4740_I2S_CLKSRC_PLL:
301	parent = clk_get(NULL, "pll half");
302	clk_set_parent(i2s->clk_i2s, parent);
303	ret = clk_set_rate(i2s->clk_i2s, freq);
304	break;
305	default:
306	return -EINVAL;
307	}
308	clk_put(parent);
309
310	return ret;
311	}
312
313	static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
314	{
315	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
316	uint32_t conf;
317
318	if (dai->active) {
319	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
320	conf &= ~JZ_AIC_CONF_ENABLE;
321	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
322
323	clk_disable(i2s->clk_i2s);
324	}
325
326	clk_disable(i2s->clk_aic);
327
328	return 0;
329	}
330
331	static int jz4740_i2s_resume(struct snd_soc_dai *dai)
332	{
333	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
334	uint32_t conf;
335
336	clk_enable(i2s->clk_aic);
337
338	if (dai->active) {
339	clk_enable(i2s->clk_i2s);
340
341	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
342	conf \|= JZ_AIC_CONF_ENABLE;
343	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
344	}
345
346	return 0;
347	}
348
349	static int jz4740_i2s_probe(struct platform_device pdev, struct snd_soc_dai dai)
350	{
351	struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
352	uint32_t conf;
353
354	conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) \|
355	(8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) \|
356	JZ_AIC_CONF_OVERFLOW_PLAY_LAST \|
357	JZ_AIC_CONF_I2S \|
358	JZ_AIC_CONF_INTERNAL_CODEC;
359
360	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
361	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
362
363	return 0;
364	}
365
366	static struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
367	.startup = jz4740_i2s_startup,
368	.shutdown = jz4740_i2s_shutdown,
369	.trigger = jz4740_i2s_trigger,
370	.hw_params = jz4740_i2s_hw_params,
371	.set_fmt = jz4740_i2s_set_fmt,
372	.set_sysclk = jz4740_i2s_set_sysclk,
373	};
374
375	#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 \| \
376	SNDRV_PCM_FMTBIT_S16_LE)
377
378	struct snd_soc_dai jz4740_i2s_dai = {
379	.name = "jz4740-i2s",
380	.probe = jz4740_i2s_probe,
381	.playback = {
382	.channels_min = 1,
383	.channels_max = 2,
384	.rates = SNDRV_PCM_RATE_8000_48000,
385	.formats = JZ4740_I2S_FMTS,
386	},
387	.capture = {
388	.channels_min = 2,
389	.channels_max = 2,
390	.rates = SNDRV_PCM_RATE_8000_48000,
391	.formats = JZ4740_I2S_FMTS,
392	},
393	.symmetric_rates = 1,
394	.ops = &jz4740_i2s_dai_ops,
395	.suspend = jz4740_i2s_suspend,
396	.resume = jz4740_i2s_resume,
397	};
398	EXPORT_SYMBOL_GPL(jz4740_i2s_dai);
399
400	static void __devinit jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
401	{
402	struct jz4740_dma_config *dma_config;
403
404	/* Playback */
405	dma_config = &i2s->pcm_config_playback.dma_config;
406	dma_config->src_width = JZ4740_DMA_WIDTH_32BIT,
407	dma_config->transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE;
408	dma_config->request_type = JZ4740_DMA_TYPE_AIC_TRANSMIT;
409	dma_config->flags = JZ4740_DMA_SRC_AUTOINC;
410	dma_config->mode = JZ4740_DMA_MODE_SINGLE;
411	i2s->pcm_config_playback.fifo_addr = i2s->phys_base + JZ_REG_AIC_FIFO;
412
413	/* Capture */
414	dma_config = &i2s->pcm_config_capture.dma_config;
415	dma_config->dst_width = JZ4740_DMA_WIDTH_32BIT,
416	dma_config->transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE;
417	dma_config->request_type = JZ4740_DMA_TYPE_AIC_RECEIVE;
418	dma_config->flags = JZ4740_DMA_DST_AUTOINC;
419	dma_config->mode = JZ4740_DMA_MODE_SINGLE;
420	i2s->pcm_config_capture.fifo_addr = i2s->phys_base + JZ_REG_AIC_FIFO;
421	}
422
423	static int __devinit jz4740_i2s_dev_probe(struct platform_device *pdev)
424	{
425	struct jz4740_i2s *i2s;
426	int ret;
427
428	i2s = kzalloc(sizeof(*i2s), GFP_KERNEL);
429
430	if (!i2s)
431	return -ENOMEM;
432
433	i2s->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
434	if (!i2s->mem) {
435	ret = -ENOENT;
436	goto err_free;
437	}
438
439	i2s->mem = request_mem_region(i2s->mem->start, resource_size(i2s->mem),
440	pdev->name);
441	if (!i2s->mem) {
442	ret = -EBUSY;
443	goto err_free;
444	}
445
446	i2s->base = ioremap_nocache(i2s->mem->start, resource_size(i2s->mem));
447	if (!i2s->base) {
448	ret = -EBUSY;
449	goto err_release_mem_region;
450	}
451
452	i2s->phys_base = i2s->mem->start;
453
454	i2s->clk_aic = clk_get(&pdev->dev, "aic");
455	if (IS_ERR(i2s->clk_aic)) {
456	ret = PTR_ERR(i2s->clk_aic);
457	goto err_iounmap;
458	}
459
460	i2s->clk_i2s = clk_get(&pdev->dev, "i2s");
461	if (IS_ERR(i2s->clk_i2s)) {
462	ret = PTR_ERR(i2s->clk_i2s);
463	goto err_clk_put_aic;
464	}
465
466	clk_enable(i2s->clk_aic);
467
468	jz4740_i2c_init_pcm_config(i2s);
469
470	jz4740_i2s_dai.private_data = i2s;
471	ret = snd_soc_register_dai(&jz4740_i2s_dai);
472
473	if (ret) {
474	dev_err(&pdev->dev, "Failed to register DAI\n");
475	goto err_clk_put_i2s;
476	}
477
478	platform_set_drvdata(pdev, i2s);
479
480	return 0;
481
482	err_clk_put_i2s:
483	clk_disable(i2s->clk_aic);
484	clk_put(i2s->clk_i2s);
485	err_clk_put_aic:
486	clk_put(i2s->clk_aic);
487	err_iounmap:
488	iounmap(i2s->base);
489	err_release_mem_region:
490	release_mem_region(i2s->mem->start, resource_size(i2s->mem));
491	err_free:
492	kfree(i2s);
493
494	return ret;
495	}
496
497	static int __devexit jz4740_i2s_dev_remove(struct platform_device *pdev)
498	{
499	struct jz4740_i2s *i2s = platform_get_drvdata(pdev);
500
501	snd_soc_unregister_dai(&jz4740_i2s_dai);
502
503	clk_disable(i2s->clk_aic);
504	clk_put(i2s->clk_i2s);
505	clk_put(i2s->clk_aic);
506
507	iounmap(i2s->base);
508	release_mem_region(i2s->mem->start, resource_size(i2s->mem));
509
510	platform_set_drvdata(pdev, NULL);
511	kfree(i2s);
512
513	return 0;
514	}
515
516	static struct platform_driver jz4740_i2s_driver = {
517	.probe = jz4740_i2s_dev_probe,
518	.remove = __devexit_p(jz4740_i2s_dev_remove),
519	.driver = {
520	.name = "jz4740-i2s",
521	.owner = THIS_MODULE,
522	},
523	};
524
525	static int __init jz4740_i2s_init(void)
526	{
527	return platform_driver_register(&jz4740_i2s_driver);
528	}
529	module_init(jz4740_i2s_init);
530
531	static void __exit jz4740_i2s_exit(void)
532	{
533	platform_driver_unregister(&jz4740_i2s_driver);
534	}
535	module_exit(jz4740_i2s_exit);
536
537	MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
538	MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
539	MODULE_LICENSE("GPL");
540	MODULE_ALIAS("platform:jz4740-i2s");