[deliverable/linux.git] / sound / soc / jz4740 / jz4740-i2s.c

/*
 *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under  the terms of the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <linux/clk.h>
#include <linux/delay.h>

#include <linux/dma-mapping.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/dmaengine_pcm.h>

#include "jz4740-i2s.h"

#define JZ4740_DMA_TYPE_AIC_TRANSMIT 24
#define JZ4740_DMA_TYPE_AIC_RECEIVE 25

#define JZ_REG_AIC_CONF		0x00
#define JZ_REG_AIC_CTRL		0x04
#define JZ_REG_AIC_I2S_FMT	0x10
#define JZ_REG_AIC_FIFO_STATUS	0x14
#define JZ_REG_AIC_I2S_STATUS	0x1c
#define JZ_REG_AIC_CLK_DIV	0x30
#define JZ_REG_AIC_FIFO		0x34

#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf <<  8)
#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
#define JZ_AIC_CONF_I2S BIT(4)
#define JZ_AIC_CONF_RESET BIT(3)
#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
#define JZ_AIC_CONF_ENABLE BIT(0)

#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8

#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
#define JZ_AIC_CTRL_FLUSH		BIT(8)
#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)

#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET  16

#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
#define JZ_AIC_I2S_FMT_MSB BIT(0)

#define JZ_AIC_I2S_STATUS_BUSY BIT(2)

#define JZ_AIC_CLK_DIV_MASK 0xf
#define I2SDIV_DV_SHIFT 8
#define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT)

struct jz4740_i2s {
	struct resource *mem;
	void __iomem *base;
	dma_addr_t phys_base;

	struct clk *clk_aic;
	struct clk *clk_i2s;

	struct snd_dmaengine_dai_dma_data playback_dma_data;
	struct snd_dmaengine_dai_dma_data capture_dma_data;
};

static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
	unsigned int reg)
{
	return readl(i2s->base + reg);
}

static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
	unsigned int reg, uint32_t value)
{
	writel(value, i2s->base + reg);
}

static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	uint32_t conf, ctrl;

	if (dai->active)
		return 0;

	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
	ctrl |= JZ_AIC_CTRL_FLUSH;
	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);

	clk_prepare_enable(i2s->clk_i2s);

	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	conf |= JZ_AIC_CONF_ENABLE;
	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

	return 0;
}

static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	uint32_t conf;

	if (dai->active)
		return;

	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	conf &= ~JZ_AIC_CONF_ENABLE;
	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

	clk_disable_unprepare(i2s->clk_i2s);
}

static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
	struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	uint32_t ctrl;
	uint32_t mask;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
	else
		mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;

	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		ctrl |= mask;
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		ctrl &= ~mask;
		break;
	default:
		return -EINVAL;
	}

	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);

	return 0;
}

static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	uint32_t format = 0;
	uint32_t conf;

	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);

	conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
		format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
		break;
	case SND_SOC_DAIFMT_CBS_CFM:
		conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_MSB:
		format |= JZ_AIC_I2S_FMT_MSB;
		break;
	case SND_SOC_DAIFMT_I2S:
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		break;
	default:
		return -EINVAL;
	}

	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);

	return 0;
}

static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	unsigned int sample_size;
	uint32_t ctrl, div_reg;
	int div;

	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);

	div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV);
	div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params));

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		sample_size = 0;
		break;
	case SNDRV_PCM_FORMAT_S16:
		sample_size = 1;
		break;
	default:
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
		ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
		if (params_channels(params) == 1)
			ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
		else
			ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
	} else {
		ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
		ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
	}

	div_reg &= ~I2SDIV_DV_MASK;
	div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
	jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg);

	return 0;
}

static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
	unsigned int freq, int dir)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	struct clk *parent;
	int ret = 0;

	switch (clk_id) {
	case JZ4740_I2S_CLKSRC_EXT:
		parent = clk_get(NULL, "ext");
		clk_set_parent(i2s->clk_i2s, parent);
		break;
	case JZ4740_I2S_CLKSRC_PLL:
		parent = clk_get(NULL, "pll half");
		clk_set_parent(i2s->clk_i2s, parent);
		ret = clk_set_rate(i2s->clk_i2s, freq);
		break;
	default:
		return -EINVAL;
	}
	clk_put(parent);

	return ret;
}

static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	uint32_t conf;

	if (dai->active) {
		conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
		conf &= ~JZ_AIC_CONF_ENABLE;
		jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

		clk_disable_unprepare(i2s->clk_i2s);
	}

	clk_disable_unprepare(i2s->clk_aic);

	return 0;
}

static int jz4740_i2s_resume(struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	uint32_t conf;

	clk_prepare_enable(i2s->clk_aic);

	if (dai->active) {
		clk_prepare_enable(i2s->clk_i2s);

		conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
		conf |= JZ_AIC_CONF_ENABLE;
		jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	}

	return 0;
}

static void jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
{
	struct snd_dmaengine_dai_dma_data *dma_data;

	/* Playback */
	dma_data = &i2s->playback_dma_data;
	dma_data->maxburst = 16;
	dma_data->slave_id = JZ4740_DMA_TYPE_AIC_TRANSMIT;
	dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;

	/* Capture */
	dma_data = &i2s->capture_dma_data;
	dma_data->maxburst = 16;
	dma_data->slave_id = JZ4740_DMA_TYPE_AIC_RECEIVE;
	dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
}

static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	uint32_t conf;

	clk_prepare_enable(i2s->clk_aic);

	jz4740_i2c_init_pcm_config(i2s);
	snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
		&i2s->capture_dma_data);

	conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
		(8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
		JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
		JZ_AIC_CONF_I2S |
		JZ_AIC_CONF_INTERNAL_CODEC;

	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

	return 0;
}

static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	clk_disable_unprepare(i2s->clk_aic);
	return 0;
}

static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
	.startup = jz4740_i2s_startup,
	.shutdown = jz4740_i2s_shutdown,
	.trigger = jz4740_i2s_trigger,
	.hw_params = jz4740_i2s_hw_params,
	.set_fmt = jz4740_i2s_set_fmt,
	.set_sysclk = jz4740_i2s_set_sysclk,
};

#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
		SNDRV_PCM_FMTBIT_S16_LE)

static struct snd_soc_dai_driver jz4740_i2s_dai = {
	.probe = jz4740_i2s_dai_probe,
	.remove = jz4740_i2s_dai_remove,
	.playback = {
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = JZ4740_I2S_FMTS,
	},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = JZ4740_I2S_FMTS,
	},
	.symmetric_rates = 1,
	.ops = &jz4740_i2s_dai_ops,
	.suspend = jz4740_i2s_suspend,
	.resume = jz4740_i2s_resume,
};

static const struct snd_soc_component_driver jz4740_i2s_component = {
	.name		= "jz4740-i2s",
};

#ifdef CONFIG_OF
static const struct of_device_id jz4740_of_matches[] = {
	{ .compatible = "ingenic,jz4740-i2s" },
	{ /* sentinel */ }
};
#endif

static int jz4740_i2s_dev_probe(struct platform_device *pdev)
{
	struct jz4740_i2s *i2s;
	struct resource *mem;
	int ret;

	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
	if (!i2s)
		return -ENOMEM;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	i2s->base = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(i2s->base))
		return PTR_ERR(i2s->base);

	i2s->phys_base = mem->start;

	i2s->clk_aic = devm_clk_get(&pdev->dev, "aic");
	if (IS_ERR(i2s->clk_aic))
		return PTR_ERR(i2s->clk_aic);

	i2s->clk_i2s = devm_clk_get(&pdev->dev, "i2s");
	if (IS_ERR(i2s->clk_i2s))
		return PTR_ERR(i2s->clk_i2s);

	platform_set_drvdata(pdev, i2s);

	ret = devm_snd_soc_register_component(&pdev->dev,
		&jz4740_i2s_component, &jz4740_i2s_dai, 1);
	if (ret)
		return ret;

	return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
		SND_DMAENGINE_PCM_FLAG_COMPAT);
}

static struct platform_driver jz4740_i2s_driver = {
	.probe = jz4740_i2s_dev_probe,
	.driver = {
		.name = "jz4740-i2s",
		.of_match_table = of_match_ptr(jz4740_of_matches)
	},
};

module_platform_driver(jz4740_i2s_driver);

MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:jz4740-i2s");
Commit	Line	Data
11bd3dd1 LPC	1	/*
	2	* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the
	6	* Free Software Foundation; either version 2 of the License, or (at your
	7	* option) any later version.
	8	*
	9	* You should have received a copy of the GNU General Public License along
	10	* with this program; if not, write to the Free Software Foundation, Inc.,
	11	* 675 Mass Ave, Cambridge, MA 02139, USA.
	12	*
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/io.h>
f2610571 ZLK	17	#include <linux/of.h>
f2610571 ZLK	18	#include <linux/of_device.h>
11bd3dd1 LPC	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/slab.h>
	23
	24	#include <linux/clk.h>
	25	#include <linux/delay.h>
	26
	27	#include <linux/dma-mapping.h>
	28
	29	#include <sound/core.h>
	30	#include <sound/pcm.h>
	31	#include <sound/pcm_params.h>
	32	#include <sound/soc.h>
11bd3dd1	33	#include <sound/initval.h>
0406a40a LPC	34	#include <sound/dmaengine_pcm.h>
0406a40a LPC	35
11bd3dd1	36	#include "jz4740-i2s.h"
11bd3dd1	37
0aa2a15a LPC	38	#define JZ4740_DMA_TYPE_AIC_TRANSMIT 24
	39	#define JZ4740_DMA_TYPE_AIC_RECEIVE 25
	40
11bd3dd1 LPC	41	#define JZ_REG_AIC_CONF 0x00
	42	#define JZ_REG_AIC_CTRL 0x04
	43	#define JZ_REG_AIC_I2S_FMT 0x10
	44	#define JZ_REG_AIC_FIFO_STATUS 0x14
	45	#define JZ_REG_AIC_I2S_STATUS 0x1c
	46	#define JZ_REG_AIC_CLK_DIV 0x30
	47	#define JZ_REG_AIC_FIFO 0x34
	48
	49	#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
	50	#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8)
	51	#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
	52	#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
	53	#define JZ_AIC_CONF_I2S BIT(4)
	54	#define JZ_AIC_CONF_RESET BIT(3)
	55	#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
	56	#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
	57	#define JZ_AIC_CONF_ENABLE BIT(0)
	58
	59	#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
	60	#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
	61
	62	#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
	63	#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
	64	#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
	65	#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
	66	#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
	67	#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
	68	#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
	69	#define JZ_AIC_CTRL_FLUSH BIT(8)
	70	#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
	71	#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
	72	#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
	73	#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
	74	#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
	75	#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
	76	#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
	77
	78	#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
	79	#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16
	80
	81	#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
	82	#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
	83	#define JZ_AIC_I2S_FMT_MSB BIT(0)
	84
	85	#define JZ_AIC_I2S_STATUS_BUSY BIT(2)
	86
	87	#define JZ_AIC_CLK_DIV_MASK 0xf
26b0aad8 ZLK	88	#define I2SDIV_DV_SHIFT 8
26b0aad8 ZLK	89	#define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT)
11bd3dd1 LPC	90
	91	struct jz4740_i2s {
	92	struct resource *mem;
	93	void __iomem *base;
	94	dma_addr_t phys_base;
	95
	96	struct clk *clk_aic;
	97	struct clk *clk_i2s;
	98
0406a40a LPC	99	struct snd_dmaengine_dai_dma_data playback_dma_data;
0406a40a LPC	100	struct snd_dmaengine_dai_dma_data capture_dma_data;
11bd3dd1 LPC	101	};
	102
	103	static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
	104	unsigned int reg)
	105	{
	106	return readl(i2s->base + reg);
	107	}
	108
	109	static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
	110	unsigned int reg, uint32_t value)
	111	{
	112	writel(value, i2s->base + reg);
	113	}
	114
11bd3dd1 LPC	115	static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
	116	struct snd_soc_dai *dai)
	117	{
f0fba2ad	118	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	119	uint32_t conf, ctrl;
	120
	121	if (dai->active)
	122	return 0;
	123
	124	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
	125	ctrl \|= JZ_AIC_CTRL_FLUSH;
	126	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
	127
010187fb	128	clk_prepare_enable(i2s->clk_i2s);
11bd3dd1 LPC	129
	130	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	131	conf \|= JZ_AIC_CONF_ENABLE;
	132	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	133
	134	return 0;
	135	}
	136
	137	static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
	138	struct snd_soc_dai *dai)
	139	{
f0fba2ad	140	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	141	uint32_t conf;
11bd3dd1 LPC	142
005967a1	143	if (dai->active)
11bd3dd1 LPC	144	return;
	145
	146	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	147	conf &= ~JZ_AIC_CONF_ENABLE;
	148	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	149
010187fb	150	clk_disable_unprepare(i2s->clk_i2s);
11bd3dd1 LPC	151	}
	152
	153	static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
	154	struct snd_soc_dai *dai)
	155	{
f0fba2ad	156	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	157
	158	uint32_t ctrl;
	159	uint32_t mask;
	160
	161	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	162	mask = JZ_AIC_CTRL_ENABLE_PLAYBACK \| JZ_AIC_CTRL_ENABLE_TX_DMA;
	163	else
	164	mask = JZ_AIC_CTRL_ENABLE_CAPTURE \| JZ_AIC_CTRL_ENABLE_RX_DMA;
	165
	166	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
	167
	168	switch (cmd) {
	169	case SNDRV_PCM_TRIGGER_START:
	170	case SNDRV_PCM_TRIGGER_RESUME:
	171	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	172	ctrl \|= mask;
	173	break;
	174	case SNDRV_PCM_TRIGGER_STOP:
	175	case SNDRV_PCM_TRIGGER_SUSPEND:
	176	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	177	ctrl &= ~mask;
	178	break;
	179	default:
	180	return -EINVAL;
	181	}
	182
	183	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
	184
	185	return 0;
	186	}
	187
	188	static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
	189	{
f0fba2ad	190	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	191
	192	uint32_t format = 0;
	193	uint32_t conf;
	194
	195	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	196
	197	conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER \| JZ_AIC_CONF_SYNC_CLK_MASTER);
	198
	199	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	200	case SND_SOC_DAIFMT_CBS_CFS:
	201	conf \|= JZ_AIC_CONF_BIT_CLK_MASTER \| JZ_AIC_CONF_SYNC_CLK_MASTER;
	202	format \|= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
	203	break;
	204	case SND_SOC_DAIFMT_CBM_CFS:
	205	conf \|= JZ_AIC_CONF_SYNC_CLK_MASTER;
	206	break;
	207	case SND_SOC_DAIFMT_CBS_CFM:
	208	conf \|= JZ_AIC_CONF_BIT_CLK_MASTER;
	209	break;
	210	case SND_SOC_DAIFMT_CBM_CFM:
	211	break;
	212	default:
	213	return -EINVAL;
	214	}
	215
	216	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	217	case SND_SOC_DAIFMT_MSB:
	218	format \|= JZ_AIC_I2S_FMT_MSB;
	219	break;
	220	case SND_SOC_DAIFMT_I2S:
	221	break;
	222	default:
	223	return -EINVAL;
	224	}
	225
	226	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	227	case SND_SOC_DAIFMT_NB_NF:
	228	break;
	229	default:
	230	return -EINVAL;
	231	}
	232
	233	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	234	jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
	235
	236	return 0;
	237	}
	238
	239	static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
	240	struct snd_pcm_hw_params params, struct snd_soc_dai dai)
	241	{
f0fba2ad	242	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1	243	unsigned int sample_size;
26b0aad8 ZLK	244	uint32_t ctrl, div_reg;
26b0aad8 ZLK	245	int div;
11bd3dd1 LPC	246
	247	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
	248
26b0aad8 ZLK	249	div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV);
	250	div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params));
	251
11bd3dd1 LPC	252	switch (params_format(params)) {
	253	case SNDRV_PCM_FORMAT_S8:
	254	sample_size = 0;
11bd3dd1 LPC	255	break;
	256	case SNDRV_PCM_FORMAT_S16:
	257	sample_size = 1;
11bd3dd1 LPC	258	break;
	259	default:
	260	return -EINVAL;
	261	}
	262
	263	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	264	ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
	265	ctrl \|= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
	266	if (params_channels(params) == 1)
	267	ctrl \|= JZ_AIC_CTRL_MONO_TO_STEREO;
	268	else
	269	ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
11bd3dd1 LPC	270	} else {
	271	ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
	272	ctrl \|= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
11bd3dd1 LPC	273	}
11bd3dd1 LPC	274
26b0aad8 ZLK	275	div_reg &= ~I2SDIV_DV_MASK;
26b0aad8 ZLK	276	div_reg \|= (div - 1) << I2SDIV_DV_SHIFT;
11bd3dd1	277	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
26b0aad8	278	jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg);
11bd3dd1	279
11bd3dd1 LPC	280	return 0;
	281	}
	282
	283	static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
	284	unsigned int freq, int dir)
	285	{
f0fba2ad	286	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	287	struct clk *parent;
	288	int ret = 0;
	289
	290	switch (clk_id) {
	291	case JZ4740_I2S_CLKSRC_EXT:
	292	parent = clk_get(NULL, "ext");
	293	clk_set_parent(i2s->clk_i2s, parent);
	294	break;
	295	case JZ4740_I2S_CLKSRC_PLL:
	296	parent = clk_get(NULL, "pll half");
	297	clk_set_parent(i2s->clk_i2s, parent);
	298	ret = clk_set_rate(i2s->clk_i2s, freq);
	299	break;
	300	default:
	301	return -EINVAL;
	302	}
	303	clk_put(parent);
	304
	305	return ret;
	306	}
	307
	308	static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
	309	{
f0fba2ad	310	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	311	uint32_t conf;
	312
	313	if (dai->active) {
	314	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	315	conf &= ~JZ_AIC_CONF_ENABLE;
	316	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	317
010187fb	318	clk_disable_unprepare(i2s->clk_i2s);
11bd3dd1 LPC	319	}
11bd3dd1 LPC	320
010187fb	321	clk_disable_unprepare(i2s->clk_aic);
11bd3dd1 LPC	322
	323	return 0;
	324	}
	325
	326	static int jz4740_i2s_resume(struct snd_soc_dai *dai)
	327	{
f0fba2ad	328	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	329	uint32_t conf;
11bd3dd1 LPC	330
010187fb	331	clk_prepare_enable(i2s->clk_aic);
11bd3dd1 LPC	332
11bd3dd1 LPC	333	if (dai->active) {
010187fb	334	clk_prepare_enable(i2s->clk_i2s);
11bd3dd1 LPC	335
	336	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	337	conf \|= JZ_AIC_CONF_ENABLE;
	338	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	339	}
	340
	341	return 0;
	342	}
	343
f0fba2ad	344	static void jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
11bd3dd1	345	{
0406a40a	346	struct snd_dmaengine_dai_dma_data *dma_data;
f0fba2ad LG	347
f0fba2ad LG	348	/* Playback */
0406a40a LPC	349	dma_data = &i2s->playback_dma_data;
	350	dma_data->maxburst = 16;
	351	dma_data->slave_id = JZ4740_DMA_TYPE_AIC_TRANSMIT;
	352	dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
f0fba2ad LG	353
f0fba2ad LG	354	/* Capture */
0406a40a LPC	355	dma_data = &i2s->capture_dma_data;
	356	dma_data->maxburst = 16;
	357	dma_data->slave_id = JZ4740_DMA_TYPE_AIC_RECEIVE;
	358	dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
f0fba2ad LG	359	}
	360
	361	static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
	362	{
	363	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	364	uint32_t conf;
11bd3dd1 LPC	365
010187fb	366	clk_prepare_enable(i2s->clk_aic);
f0fba2ad LG	367
f0fba2ad LG	368	jz4740_i2c_init_pcm_config(i2s);
0406a40a LPC	369	snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
0406a40a LPC	370	&i2s->capture_dma_data);
f0fba2ad	371
11bd3dd1 LPC	372	conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) \|
	373	(8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) \|
	374	JZ_AIC_CONF_OVERFLOW_PLAY_LAST \|
	375	JZ_AIC_CONF_I2S \|
	376	JZ_AIC_CONF_INTERNAL_CODEC;
	377
	378	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
	379	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	380
	381	return 0;
	382	}
	383
f0fba2ad LG	384	static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
	385	{
	386	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	387
010187fb	388	clk_disable_unprepare(i2s->clk_aic);
f0fba2ad LG	389	return 0;
	390	}
	391
85e7652d	392	static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
11bd3dd1 LPC	393	.startup = jz4740_i2s_startup,
	394	.shutdown = jz4740_i2s_shutdown,
	395	.trigger = jz4740_i2s_trigger,
	396	.hw_params = jz4740_i2s_hw_params,
	397	.set_fmt = jz4740_i2s_set_fmt,
	398	.set_sysclk = jz4740_i2s_set_sysclk,
	399	};
	400
	401	#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 \| \
	402	SNDRV_PCM_FMTBIT_S16_LE)
	403
f0fba2ad LG	404	static struct snd_soc_dai_driver jz4740_i2s_dai = {
	405	.probe = jz4740_i2s_dai_probe,
	406	.remove = jz4740_i2s_dai_remove,
11bd3dd1 LPC	407	.playback = {
	408	.channels_min = 1,
	409	.channels_max = 2,
	410	.rates = SNDRV_PCM_RATE_8000_48000,
	411	.formats = JZ4740_I2S_FMTS,
	412	},
	413	.capture = {
	414	.channels_min = 2,
	415	.channels_max = 2,
	416	.rates = SNDRV_PCM_RATE_8000_48000,
	417	.formats = JZ4740_I2S_FMTS,
	418	},
	419	.symmetric_rates = 1,
	420	.ops = &jz4740_i2s_dai_ops,
	421	.suspend = jz4740_i2s_suspend,
	422	.resume = jz4740_i2s_resume,
	423	};
11bd3dd1	424
29cc15cf KM	425	static const struct snd_soc_component_driver jz4740_i2s_component = {
	426	.name = "jz4740-i2s",
	427	};
	428
f2610571 ZLK	429	#ifdef CONFIG_OF
	430	static const struct of_device_id jz4740_of_matches[] = {
	431	{ .compatible = "ingenic,jz4740-i2s" },
	432	{ /* sentinel */ }
	433	};
	434	#endif
	435
d6a29e3d	436	static int jz4740_i2s_dev_probe(struct platform_device *pdev)
11bd3dd1 LPC	437	{
11bd3dd1 LPC	438	struct jz4740_i2s *i2s;
b84c9ce8	439	struct resource *mem;
11bd3dd1 LPC	440	int ret;
11bd3dd1 LPC	441
b84c9ce8	442	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
11bd3dd1 LPC	443	if (!i2s)
	444	return -ENOMEM;
	445
b84c9ce8 LPC	446	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	447	i2s->base = devm_ioremap_resource(&pdev->dev, mem);
	448	if (IS_ERR(i2s->base))
	449	return PTR_ERR(i2s->base);
11bd3dd1	450
b84c9ce8	451	i2s->phys_base = mem->start;
11bd3dd1	452
b84c9ce8 LPC	453	i2s->clk_aic = devm_clk_get(&pdev->dev, "aic");
	454	if (IS_ERR(i2s->clk_aic))
	455	return PTR_ERR(i2s->clk_aic);
11bd3dd1	456
b84c9ce8 LPC	457	i2s->clk_i2s = devm_clk_get(&pdev->dev, "i2s");
	458	if (IS_ERR(i2s->clk_i2s))
	459	return PTR_ERR(i2s->clk_i2s);
11bd3dd1	460
f0fba2ad	461	platform_set_drvdata(pdev, i2s);
11bd3dd1	462
0406a40a	463	ret = devm_snd_soc_register_component(&pdev->dev,
b84c9ce8	464	&jz4740_i2s_component, &jz4740_i2s_dai, 1);
0406a40a LPC	465	if (ret)
	466	return ret;
	467
	468	return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
	469	SND_DMAENGINE_PCM_FLAG_COMPAT);
11bd3dd1 LPC	470	}
	471
	472	static struct platform_driver jz4740_i2s_driver = {
	473	.probe = jz4740_i2s_dev_probe,
11bd3dd1 LPC	474	.driver = {
11bd3dd1 LPC	475	.name = "jz4740-i2s",
f2610571	476	.of_match_table = of_match_ptr(jz4740_of_matches)
11bd3dd1 LPC	477	},
	478	};
	479
c32986e6	480	module_platform_driver(jz4740_i2s_driver);
11bd3dd1 LPC	481
	482	MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
	483	MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
	484	MODULE_LICENSE("GPL");
	485	MODULE_ALIAS("platform:jz4740-i2s");