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Merge tag 'asoc-v4.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / sound / soc / mediatek / mtk-afe-pcm.c
CommitLineData
ee0bcaff
KC		 1/*
2 * Mediatek ALSA SoC AFE platform driver
3 *
4 * Copyright (c) 2015 MediaTek Inc.
5 * Author: Koro Chen <koro.chen@mediatek.com>
6 * Sascha Hauer <s.hauer@pengutronix.de>
7 * Hidalgo Huang <hidalgo.huang@mediatek.com>
8 * Ir Lian <ir.lian@mediatek.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 and
12 * only version 2 as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/delay.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
fcde5a7e 24#include <linux/dma-mapping.h>
ee0bcaff
KC		 25#include <linux/pm_runtime.h>
26#include <sound/soc.h>
27#include "mtk-afe-common.h"
28
29/*****************************************************************************
30 * R E G I S T E R D E F I N I T I O N
31 *****************************************************************************/
32#define AUDIO_TOP_CON0 0x0000
33#define AUDIO_TOP_CON1 0x0004
34#define AFE_DAC_CON0 0x0010
35#define AFE_DAC_CON1 0x0014
36#define AFE_I2S_CON1 0x0034
37#define AFE_I2S_CON2 0x0038
38#define AFE_CONN_24BIT 0x006c
fcde5a7e 39#define AFE_MEMIF_MSB 0x00cc
ee0bcaff
KC		 40
41#define AFE_CONN1 0x0024
42#define AFE_CONN2 0x0028
84f3a524 43#define AFE_CONN3 0x002c
ee0bcaff
KC		 44#define AFE_CONN7 0x0460
45#define AFE_CONN8 0x0464
46#define AFE_HDMI_CONN0 0x0390
47
48/* Memory interface */
49#define AFE_DL1_BASE 0x0040
50#define AFE_DL1_CUR 0x0044
775b07de 51#define AFE_DL1_END 0x0048
ee0bcaff
KC		 52#define AFE_DL2_BASE 0x0050
53#define AFE_DL2_CUR 0x0054
54#define AFE_AWB_BASE 0x0070
55#define AFE_AWB_CUR 0x007c
56#define AFE_VUL_BASE 0x0080
57#define AFE_VUL_CUR 0x008c
775b07de 58#define AFE_VUL_END 0x0088
ee0bcaff
KC		 59#define AFE_DAI_BASE 0x0090
60#define AFE_DAI_CUR 0x009c
61#define AFE_MOD_PCM_BASE 0x0330
62#define AFE_MOD_PCM_CUR 0x033c
63#define AFE_HDMI_OUT_BASE 0x0374
64#define AFE_HDMI_OUT_CUR 0x0378
775b07de 65#define AFE_HDMI_OUT_END 0x037c
ee0bcaff 66
84f3a524 67#define AFE_ADDA_TOP_CON0 0x0120
ee0bcaff
KC		 68#define AFE_ADDA2_TOP_CON0 0x0600
69
70#define AFE_HDMI_OUT_CON0 0x0370
71
72#define AFE_IRQ_MCU_CON 0x03a0
73#define AFE_IRQ_STATUS 0x03a4
74#define AFE_IRQ_CLR 0x03a8
75#define AFE_IRQ_CNT1 0x03ac
76#define AFE_IRQ_CNT2 0x03b0
77#define AFE_IRQ_MCU_EN 0x03b4
78#define AFE_IRQ_CNT5 0x03bc
79#define AFE_IRQ_CNT7 0x03dc
80
81#define AFE_TDM_CON1 0x0548
82#define AFE_TDM_CON2 0x054c
83
84#define AFE_BASE_END_OFFSET 8
85#define AFE_IRQ_STATUS_BITS 0xff
86
87/* AUDIO_TOP_CON0 (0x0000) */
88#define AUD_TCON0_PDN_SPDF (0x1 << 21)
89#define AUD_TCON0_PDN_HDMI (0x1 << 20)
90#define AUD_TCON0_PDN_24M (0x1 << 9)
91#define AUD_TCON0_PDN_22M (0x1 << 8)
92#define AUD_TCON0_PDN_AFE (0x1 << 2)
93
94/* AFE_I2S_CON1 (0x0034) */
95#define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12)
96#define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8)
97#define AFE_I2S_CON1_FORMAT_I2S (0x1 << 3)
98#define AFE_I2S_CON1_EN (0x1 << 0)
99
100/* AFE_I2S_CON2 (0x0038) */
101#define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12)
102#define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8)
103#define AFE_I2S_CON2_FORMAT_I2S (0x1 << 3)
104#define AFE_I2S_CON2_EN (0x1 << 0)
105
106/* AFE_CONN_24BIT (0x006c) */
107#define AFE_CONN_24BIT_O04 (0x1 << 4)
108#define AFE_CONN_24BIT_O03 (0x1 << 3)
109
110/* AFE_HDMI_CONN0 (0x0390) */
111#define AFE_HDMI_CONN0_O37_I37 (0x7 << 21)
112#define AFE_HDMI_CONN0_O36_I36 (0x6 << 18)
113#define AFE_HDMI_CONN0_O35_I33 (0x3 << 15)
114#define AFE_HDMI_CONN0_O34_I32 (0x2 << 12)
115#define AFE_HDMI_CONN0_O33_I35 (0x5 << 9)
116#define AFE_HDMI_CONN0_O32_I34 (0x4 << 6)
117#define AFE_HDMI_CONN0_O31_I31 (0x1 << 3)
118#define AFE_HDMI_CONN0_O30_I30 (0x0 << 0)
119
120/* AFE_TDM_CON1 (0x0548) */
121#define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24)
122#define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12)
123#define AFE_TDM_CON1_WLEN_32BIT (0x2 << 8)
124#define AFE_TDM_CON1_MSB_ALIGNED (0x1 << 4)
125#define AFE_TDM_CON1_1_BCK_DELAY (0x1 << 3)
27becea0 126#define AFE_TDM_CON1_LRCK_INV (0x1 << 2)
ee0bcaff
KC		 127#define AFE_TDM_CON1_BCK_INV (0x1 << 1)
128#define AFE_TDM_CON1_EN (0x1 << 0)
129
130enum afe_tdm_ch_start {
131 AFE_TDM_CH_START_O30_O31 = 0,
132 AFE_TDM_CH_START_O32_O33,
133 AFE_TDM_CH_START_O34_O35,
134 AFE_TDM_CH_START_O36_O37,
135 AFE_TDM_CH_ZERO,
136};
137
775b07de
KC		 138static const unsigned int mtk_afe_backup_list[] = {
139 AUDIO_TOP_CON0,
140 AFE_CONN1,
141 AFE_CONN2,
142 AFE_CONN7,
143 AFE_CONN8,
144 AFE_DAC_CON1,
145 AFE_DL1_BASE,
146 AFE_DL1_END,
147 AFE_VUL_BASE,
148 AFE_VUL_END,
149 AFE_HDMI_OUT_BASE,
150 AFE_HDMI_OUT_END,
151 AFE_HDMI_CONN0,
152 AFE_DAC_CON0,
153};
154
155struct mtk_afe {
156 /* address for ioremap audio hardware register */
157 void __iomem *base_addr;
158 struct device *dev;
159 struct regmap *regmap;
160 struct mtk_afe_memif memif[MTK_AFE_MEMIF_NUM];
161 struct clk *clocks[MTK_CLK_NUM];
162 unsigned int backup_regs[ARRAY_SIZE(mtk_afe_backup_list)];
163 bool suspended;
164};
165
ee0bcaff
KC		 166static const struct snd_pcm_hardware mtk_afe_hardware = {
167 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
168 SNDRV_PCM_INFO_MMAP_VALID),
169 .buffer_bytes_max = 256 * 1024,
170 .period_bytes_min = 512,
171 .period_bytes_max = 128 * 1024,
172 .periods_min = 2,
173 .periods_max = 256,
174 .fifo_size = 0,
175};
176
177static snd_pcm_uframes_t mtk_afe_pcm_pointer
178 (struct snd_pcm_substream *substream)
179{
180 struct snd_soc_pcm_runtime *rtd = substream->private_data;
181 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
182 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
8d6f88ce
KC		 183 unsigned int hw_ptr;
184 int ret;
185
186 ret = regmap_read(afe->regmap, memif->data->reg_ofs_cur, &hw_ptr);
187 if (ret || hw_ptr == 0) {
188 dev_err(afe->dev, "%s hw_ptr err\n", __func__);
189 hw_ptr = memif->phys_buf_addr;
190 }
ee0bcaff 191
8d6f88ce
KC		 192 return bytes_to_frames(substream->runtime,
193 hw_ptr - memif->phys_buf_addr);
ee0bcaff
KC		 194}
195
196static const struct snd_pcm_ops mtk_afe_pcm_ops = {
197 .ioctl = snd_pcm_lib_ioctl,
198 .pointer = mtk_afe_pcm_pointer,
199};
200
201static int mtk_afe_pcm_new(struct snd_soc_pcm_runtime *rtd)
202{
203 size_t size;
204 struct snd_card *card = rtd->card->snd_card;
205 struct snd_pcm *pcm = rtd->pcm;
206
207 size = mtk_afe_hardware.buffer_bytes_max;
208
209 return snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
210 card->dev, size, size);
211}
212
213static void mtk_afe_pcm_free(struct snd_pcm *pcm)
214{
215 snd_pcm_lib_preallocate_free_for_all(pcm);
216}
217
218static const struct snd_soc_platform_driver mtk_afe_pcm_platform = {
219 .ops = &mtk_afe_pcm_ops,
220 .pcm_new = mtk_afe_pcm_new,
221 .pcm_free = mtk_afe_pcm_free,
222};
223
224struct mtk_afe_rate {
225 unsigned int rate;
226 unsigned int regvalue;
227};
228
229static const struct mtk_afe_rate mtk_afe_i2s_rates[] = {
230 { .rate = 8000, .regvalue = 0 },
231 { .rate = 11025, .regvalue = 1 },
232 { .rate = 12000, .regvalue = 2 },
233 { .rate = 16000, .regvalue = 4 },
234 { .rate = 22050, .regvalue = 5 },
235 { .rate = 24000, .regvalue = 6 },
236 { .rate = 32000, .regvalue = 8 },
237 { .rate = 44100, .regvalue = 9 },
238 { .rate = 48000, .regvalue = 10 },
239 { .rate = 88000, .regvalue = 11 },
240 { .rate = 96000, .regvalue = 12 },
241 { .rate = 174000, .regvalue = 13 },
242 { .rate = 192000, .regvalue = 14 },
243};
244
245static int mtk_afe_i2s_fs(unsigned int sample_rate)
246{
247 int i;
248
249 for (i = 0; i < ARRAY_SIZE(mtk_afe_i2s_rates); i++)
250 if (mtk_afe_i2s_rates[i].rate == sample_rate)
251 return mtk_afe_i2s_rates[i].regvalue;
252
253 return -EINVAL;
254}
255
256static int mtk_afe_set_i2s(struct mtk_afe *afe, unsigned int rate)
257{
258 unsigned int val;
259 int fs = mtk_afe_i2s_fs(rate);
260
261 if (fs < 0)
262 return -EINVAL;
263
264 /* from external ADC */
84f3a524 265 regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x1);
ee0bcaff
KC		 266 regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1);
267
268 /* set input */
269 val = AFE_I2S_CON2_LOW_JITTER_CLK |
270 AFE_I2S_CON2_RATE(fs) |
271 AFE_I2S_CON2_FORMAT_I2S;
272
273 regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val);
274
275 /* set output */
276 val = AFE_I2S_CON1_LOW_JITTER_CLK |
277 AFE_I2S_CON1_RATE(fs) |
278 AFE_I2S_CON1_FORMAT_I2S;
279
280 regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val);
281 return 0;
282}
283
284static void mtk_afe_set_i2s_enable(struct mtk_afe *afe, bool enable)
285{
286 unsigned int val;
287
288 regmap_read(afe->regmap, AFE_I2S_CON2, &val);
289 if (!!(val & AFE_I2S_CON2_EN) == enable)
4d7cb66c 290 return;
ee0bcaff
KC		 291
292 /* input */
293 regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable);
294
295 /* output */
296 regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable);
ee0bcaff
KC		 297}
298
299static int mtk_afe_dais_enable_clks(struct mtk_afe *afe,
300 struct clk *m_ck, struct clk *b_ck)
301{
302 int ret;
303
304 if (m_ck) {
305 ret = clk_prepare_enable(m_ck);
306 if (ret) {
307 dev_err(afe->dev, "Failed to enable m_ck\n");
308 return ret;
309 }
ee0bcaff
KC		 310 }
311
312 if (b_ck) {
313 ret = clk_prepare_enable(b_ck);
314 if (ret) {
315 dev_err(afe->dev, "Failed to enable b_ck\n");
316 return ret;
317 }
318 }
319 return 0;
320}
321
322static int mtk_afe_dais_set_clks(struct mtk_afe *afe,
323 struct clk *m_ck, unsigned int mck_rate,
324 struct clk *b_ck, unsigned int bck_rate)
325{
326 int ret;
327
328 if (m_ck) {
329 ret = clk_set_rate(m_ck, mck_rate);
330 if (ret) {
331 dev_err(afe->dev, "Failed to set m_ck rate\n");
332 return ret;
333 }
334 }
335
336 if (b_ck) {
337 ret = clk_set_rate(b_ck, bck_rate);
338 if (ret) {
339 dev_err(afe->dev, "Failed to set b_ck rate\n");
340 return ret;
341 }
342 }
343 return 0;
344}
345
346static void mtk_afe_dais_disable_clks(struct mtk_afe *afe,
347 struct clk *m_ck, struct clk *b_ck)
348{
b45e68df 349 if (m_ck)
ee0bcaff 350 clk_disable_unprepare(m_ck);
ee0bcaff
KC		 351 if (b_ck)
352 clk_disable_unprepare(b_ck);
353}
354
355static int mtk_afe_i2s_startup(struct snd_pcm_substream *substream,
356 struct snd_soc_dai *dai)
357{
358 struct snd_soc_pcm_runtime *rtd = substream->private_data;
359 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
360
361 if (dai->active)
362 return 0;
363
364 mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
4d7cb66c 365 mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S2_M], NULL);
b45e68df
KC		 366 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
367 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);
ee0bcaff
KC		 368 return 0;
369}
370
371static void mtk_afe_i2s_shutdown(struct snd_pcm_substream *substream,
372 struct snd_soc_dai *dai)
373{
374 struct snd_soc_pcm_runtime *rtd = substream->private_data;
375 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
376
377 if (dai->active)
378 return;
379
380 mtk_afe_set_i2s_enable(afe, false);
b45e68df
KC		 381 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
382 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,
383 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);
ee0bcaff 384 mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
4d7cb66c 385 mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S2_M], NULL);
ee0bcaff
KC		 386}
387
388static int mtk_afe_i2s_prepare(struct snd_pcm_substream *substream,
389 struct snd_soc_dai *dai)
390{
391 struct snd_soc_pcm_runtime *rtd = substream->private_data;
392 struct snd_pcm_runtime * const runtime = substream->runtime;
393 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
394 int ret;
395
396 mtk_afe_dais_set_clks(afe,
397 afe->clocks[MTK_CLK_I2S1_M], runtime->rate * 256,
398 NULL, 0);
4d7cb66c
PL		 399 mtk_afe_dais_set_clks(afe,
400 afe->clocks[MTK_CLK_I2S2_M], runtime->rate * 256,
401 NULL, 0);
ee0bcaff
KC		 402 /* config I2S */
403 ret = mtk_afe_set_i2s(afe, substream->runtime->rate);
404 if (ret)
405 return ret;
406
407 mtk_afe_set_i2s_enable(afe, true);
408
409 return 0;
410}
411
412static int mtk_afe_hdmi_startup(struct snd_pcm_substream *substream,
413 struct snd_soc_dai *dai)
414{
415 struct snd_soc_pcm_runtime *rtd = substream->private_data;
416 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
417
418 if (dai->active)
419 return 0;
420
421 mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S3_M],
422 afe->clocks[MTK_CLK_I2S3_B]);
423 return 0;
424}
425
426static void mtk_afe_hdmi_shutdown(struct snd_pcm_substream *substream,
427 struct snd_soc_dai *dai)
428{
429 struct snd_soc_pcm_runtime *rtd = substream->private_data;
430 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
431
432 if (dai->active)
433 return;
434
435 mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S3_M],
436 afe->clocks[MTK_CLK_I2S3_B]);
ee0bcaff
KC		 437}
438
439static int mtk_afe_hdmi_prepare(struct snd_pcm_substream *substream,
440 struct snd_soc_dai *dai)
441{
442 struct snd_soc_pcm_runtime *rtd = substream->private_data;
443 struct snd_pcm_runtime * const runtime = substream->runtime;
444 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
445 unsigned int val;
446
447 mtk_afe_dais_set_clks(afe,
448 afe->clocks[MTK_CLK_I2S3_M], runtime->rate * 128,
449 afe->clocks[MTK_CLK_I2S3_B],
450 runtime->rate * runtime->channels * 32);
451
452 val = AFE_TDM_CON1_BCK_INV |
27becea0 453 AFE_TDM_CON1_LRCK_INV |
ee0bcaff
KC		 454 AFE_TDM_CON1_1_BCK_DELAY |
455 AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */
456 AFE_TDM_CON1_WLEN_32BIT |
457 AFE_TDM_CON1_32_BCK_CYCLES |
458 AFE_TDM_CON1_LRCK_WIDTH(32);
459 regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val);
460
461 /* set tdm2 config */
462 switch (runtime->channels) {
463 case 1:
464 case 2:
465 val = AFE_TDM_CH_START_O30_O31;
466 val |= (AFE_TDM_CH_ZERO << 4);
467 val |= (AFE_TDM_CH_ZERO << 8);
468 val |= (AFE_TDM_CH_ZERO << 12);
469 break;
470 case 3:
471 case 4:
472 val = AFE_TDM_CH_START_O30_O31;
473 val |= (AFE_TDM_CH_START_O32_O33 << 4);
474 val |= (AFE_TDM_CH_ZERO << 8);
475 val |= (AFE_TDM_CH_ZERO << 12);
476 break;
477 case 5:
478 case 6:
479 val = AFE_TDM_CH_START_O30_O31;
480 val |= (AFE_TDM_CH_START_O32_O33 << 4);
481 val |= (AFE_TDM_CH_START_O34_O35 << 8);
482 val |= (AFE_TDM_CH_ZERO << 12);
483 break;
484 case 7:
485 case 8:
486 val = AFE_TDM_CH_START_O30_O31;
487 val |= (AFE_TDM_CH_START_O32_O33 << 4);
488 val |= (AFE_TDM_CH_START_O34_O35 << 8);
489 val |= (AFE_TDM_CH_START_O36_O37 << 12);
490 break;
491 default:
492 val = 0;
493 }
494 regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val);
495
496 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
497 0x000000f0, runtime->channels << 4);
498 return 0;
499}
500
501static int mtk_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd,
502 struct snd_soc_dai *dai)
503{
504 struct snd_soc_pcm_runtime *rtd = substream->private_data;
505 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
506
507 dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name);
508
509 switch (cmd) {
510 case SNDRV_PCM_TRIGGER_START:
511 case SNDRV_PCM_TRIGGER_RESUME:
512 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
513 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0);
514
515 /* set connections: O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */
516 regmap_write(afe->regmap, AFE_HDMI_CONN0,
517 AFE_HDMI_CONN0_O30_I30 | AFE_HDMI_CONN0_O31_I31 |
518 AFE_HDMI_CONN0_O32_I34 | AFE_HDMI_CONN0_O33_I35 |
519 AFE_HDMI_CONN0_O34_I32 | AFE_HDMI_CONN0_O35_I33 |
520 AFE_HDMI_CONN0_O36_I36 | AFE_HDMI_CONN0_O37_I37);
521
522 /* enable Out control */
523 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1);
524
525 /* enable tdm */
526 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1);
527
528 return 0;
529 case SNDRV_PCM_TRIGGER_STOP:
530 case SNDRV_PCM_TRIGGER_SUSPEND:
531 /* disable tdm */
532 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0);
533
534 /* disable Out control */
535 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0);
536
537 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
538 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF,
539 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF);
540
541 return 0;
542 default:
543 return -EINVAL;
544 }
545}
546
547static int mtk_afe_dais_startup(struct snd_pcm_substream *substream,
548 struct snd_soc_dai *dai)
549{
550 struct snd_soc_pcm_runtime *rtd = substream->private_data;
551 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
552 struct snd_pcm_runtime *runtime = substream->runtime;
553 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
554 int ret;
555
556 memif->substream = substream;
557
558 snd_soc_set_runtime_hwparams(substream, &mtk_afe_hardware);
e4fba9b5
KC		 559
560 /*
561 * Capture cannot use ping-pong buffer since hw_ptr at IRQ may be
562 * smaller than period_size due to AFE's internal buffer.
563 * This easily leads to overrun when avail_min is period_size.
564 * One more period can hold the possible unread buffer.
565 */
566 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
567 ret = snd_pcm_hw_constraint_minmax(runtime,
568 SNDRV_PCM_HW_PARAM_PERIODS,
569 3,
570 mtk_afe_hardware.periods_max);
571 if (ret < 0) {
572 dev_err(afe->dev, "hw_constraint_minmax failed\n");
573 return ret;
574 }
575 }
ee0bcaff
KC		 576 ret = snd_pcm_hw_constraint_integer(runtime,
577 SNDRV_PCM_HW_PARAM_PERIODS);
578 if (ret < 0)
579 dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
580 return ret;
581}
582
583static void mtk_afe_dais_shutdown(struct snd_pcm_substream *substream,
584 struct snd_soc_dai *dai)
585{
586 struct snd_soc_pcm_runtime *rtd = substream->private_data;
587 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
588 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
589
590 memif->substream = NULL;
591}
592
593static int mtk_afe_dais_hw_params(struct snd_pcm_substream *substream,
594 struct snd_pcm_hw_params *params,
595 struct snd_soc_dai *dai)
596{
597 struct snd_soc_pcm_runtime *rtd = substream->private_data;
598 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
599 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
fcde5a7e 600 int msb_at_bit33 = 0;
ee0bcaff
KC		 601 int ret;
602
603 dev_dbg(afe->dev,
604 "%s period = %u, rate= %u, channels=%u\n",
605 __func__, params_period_size(params), params_rate(params),
606 params_channels(params));
607
608 ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
609 if (ret < 0)
610 return ret;
611
fcde5a7e
PL		 612 msb_at_bit33 = upper_32_bits(substream->runtime->dma_addr) ? 1 : 0;
613 memif->phys_buf_addr = lower_32_bits(substream->runtime->dma_addr);
ee0bcaff 614 memif->buffer_size = substream->runtime->dma_bytes;
ee0bcaff
KC		 615
616 /* start */
617 regmap_write(afe->regmap,
618 memif->data->reg_ofs_base, memif->phys_buf_addr);
619 /* end */
620 regmap_write(afe->regmap,
621 memif->data->reg_ofs_base + AFE_BASE_END_OFFSET,
622 memif->phys_buf_addr + memif->buffer_size - 1);
623
fcde5a7e
PL		 624 /* set MSB to 33-bit */
625 regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
626 1 << memif->data->msb_shift,
627 msb_at_bit33 << memif->data->msb_shift);
628
ee0bcaff
KC		 629 /* set channel */
630 if (memif->data->mono_shift >= 0) {
631 unsigned int mono = (params_channels(params) == 1) ? 1 : 0;
632
633 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
634 1 << memif->data->mono_shift,
635 mono << memif->data->mono_shift);
636 }
637
638 /* set rate */
639 if (memif->data->fs_shift < 0)
640 return 0;
641 if (memif->data->id == MTK_AFE_MEMIF_DAI ||
642 memif->data->id == MTK_AFE_MEMIF_MOD_DAI) {
643 unsigned int val;
644
645 switch (params_rate(params)) {
646 case 8000:
647 val = 0;
648 break;
649 case 16000:
650 val = 1;
651 break;
652 case 32000:
653 val = 2;
654 break;
655 default:
656 return -EINVAL;
657 }
658
659 if (memif->data->id == MTK_AFE_MEMIF_DAI)
660 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
661 0x3 << memif->data->fs_shift,
662 val << memif->data->fs_shift);
663 else
664 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
665 0x3 << memif->data->fs_shift,
666 val << memif->data->fs_shift);
667
668 } else {
669 int fs = mtk_afe_i2s_fs(params_rate(params));
670
671 if (fs < 0)
672 return -EINVAL;
673
674 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
675 0xf << memif->data->fs_shift,
676 fs << memif->data->fs_shift);
677 }
678
679 return 0;
680}
681
682static int mtk_afe_dais_hw_free(struct snd_pcm_substream *substream,
683 struct snd_soc_dai *dai)
684{
685 return snd_pcm_lib_free_pages(substream);
686}
687
ee0bcaff
KC		 688static int mtk_afe_dais_trigger(struct snd_pcm_substream *substream, int cmd,
689 struct snd_soc_dai *dai)
690{
691 struct snd_soc_pcm_runtime *rtd = substream->private_data;
692 struct snd_pcm_runtime * const runtime = substream->runtime;
693 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
694 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
695 unsigned int counter = runtime->period_size;
696
697 dev_info(afe->dev, "%s %s cmd=%d\n", __func__, memif->data->name, cmd);
698
699 switch (cmd) {
700 case SNDRV_PCM_TRIGGER_START:
701 case SNDRV_PCM_TRIGGER_RESUME:
702 if (memif->data->enable_shift >= 0)
703 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
704 1 << memif->data->enable_shift,
705 1 << memif->data->enable_shift);
706
707 /* set irq counter */
708 regmap_update_bits(afe->regmap,
709 memif->data->irq_reg_cnt,
710 0x3ffff << memif->data->irq_cnt_shift,
711 counter << memif->data->irq_cnt_shift);
712
713 /* set irq fs */
714 if (memif->data->irq_fs_shift >= 0) {
715 int fs = mtk_afe_i2s_fs(runtime->rate);
716
717 if (fs < 0)
718 return -EINVAL;
719
720 regmap_update_bits(afe->regmap,
721 AFE_IRQ_MCU_CON,
722 0xf << memif->data->irq_fs_shift,
723 fs << memif->data->irq_fs_shift);
724 }
725 /* enable interrupt */
726 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CON,
727 1 << memif->data->irq_en_shift,
728 1 << memif->data->irq_en_shift);
729
730 return 0;
731 case SNDRV_PCM_TRIGGER_STOP:
732 case SNDRV_PCM_TRIGGER_SUSPEND:
733 if (memif->data->enable_shift >= 0)
734 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
735 1 << memif->data->enable_shift, 0);
736 /* disable interrupt */
737 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CON,
738 1 << memif->data->irq_en_shift,
739 0 << memif->data->irq_en_shift);
740 /* and clear pending IRQ */
741 regmap_write(afe->regmap, AFE_IRQ_CLR,
742 1 << memif->data->irq_clr_shift);
ee0bcaff
KC		 743 return 0;
744 default:
745 return -EINVAL;
746 }
747}
748
749/* FE DAIs */
750static const struct snd_soc_dai_ops mtk_afe_dai_ops = {
751 .startup = mtk_afe_dais_startup,
752 .shutdown = mtk_afe_dais_shutdown,
753 .hw_params = mtk_afe_dais_hw_params,
754 .hw_free = mtk_afe_dais_hw_free,
ee0bcaff
KC		 755 .trigger = mtk_afe_dais_trigger,
756};
757
758/* BE DAIs */
759static const struct snd_soc_dai_ops mtk_afe_i2s_ops = {
760 .startup = mtk_afe_i2s_startup,
761 .shutdown = mtk_afe_i2s_shutdown,
762 .prepare = mtk_afe_i2s_prepare,
763};
764
765static const struct snd_soc_dai_ops mtk_afe_hdmi_ops = {
766 .startup = mtk_afe_hdmi_startup,
767 .shutdown = mtk_afe_hdmi_shutdown,
768 .prepare = mtk_afe_hdmi_prepare,
769 .trigger = mtk_afe_hdmi_trigger,
770
771};
772
775b07de
KC		 773static int mtk_afe_runtime_suspend(struct device *dev);
774static int mtk_afe_runtime_resume(struct device *dev);
775
776static int mtk_afe_dai_suspend(struct snd_soc_dai *dai)
777{
778 struct mtk_afe *afe = snd_soc_dai_get_drvdata(dai);
779 int i;
780
781 dev_dbg(afe->dev, "%s\n", __func__);
782 if (pm_runtime_status_suspended(afe->dev) || afe->suspended)
783 return 0;
784
785 for (i = 0; i < ARRAY_SIZE(mtk_afe_backup_list); i++)
786 regmap_read(afe->regmap, mtk_afe_backup_list[i],
787 &afe->backup_regs[i]);
788
789 afe->suspended = true;
790 mtk_afe_runtime_suspend(afe->dev);
791 return 0;
792}
793
794static int mtk_afe_dai_resume(struct snd_soc_dai *dai)
795{
796 struct mtk_afe *afe = snd_soc_dai_get_drvdata(dai);
797 int i = 0;
798
799 dev_dbg(afe->dev, "%s\n", __func__);
800 if (pm_runtime_status_suspended(afe->dev) || !afe->suspended)
801 return 0;
802
803 mtk_afe_runtime_resume(afe->dev);
804
805 for (i = 0; i < ARRAY_SIZE(mtk_afe_backup_list); i++)
806 regmap_write(afe->regmap, mtk_afe_backup_list[i],
807 afe->backup_regs[i]);
808
809 afe->suspended = false;
810 return 0;
811}
812
ee0bcaff
KC		 813static struct snd_soc_dai_driver mtk_afe_pcm_dais[] = {
814 /* FE DAIs: memory intefaces to CPU */
815 {
816 .name = "DL1", /* downlink 1 */
817 .id = MTK_AFE_MEMIF_DL1,
775b07de
KC		 818 .suspend = mtk_afe_dai_suspend,
819 .resume = mtk_afe_dai_resume,
ee0bcaff
KC		 820 .playback = {
821 .stream_name = "DL1",
822 .channels_min = 1,
823 .channels_max = 2,
824 .rates = SNDRV_PCM_RATE_8000_48000,
825 .formats = SNDRV_PCM_FMTBIT_S16_LE,
826 },
827 .ops = &mtk_afe_dai_ops,
828 }, {
829 .name = "VUL", /* voice uplink */
830 .id = MTK_AFE_MEMIF_VUL,
775b07de
KC		 831 .suspend = mtk_afe_dai_suspend,
832 .resume = mtk_afe_dai_resume,
ee0bcaff
KC		 833 .capture = {
834 .stream_name = "VUL",
835 .channels_min = 1,
836 .channels_max = 2,
837 .rates = SNDRV_PCM_RATE_8000_48000,
838 .formats = SNDRV_PCM_FMTBIT_S16_LE,
839 },
840 .ops = &mtk_afe_dai_ops,
841 }, {
842 /* BE DAIs */
843 .name = "I2S",
844 .id = MTK_AFE_IO_I2S,
845 .playback = {
846 .stream_name = "I2S Playback",
847 .channels_min = 1,
848 .channels_max = 2,
849 .rates = SNDRV_PCM_RATE_8000_48000,
850 .formats = SNDRV_PCM_FMTBIT_S16_LE,
851 },
852 .capture = {
853 .stream_name = "I2S Capture",
854 .channels_min = 1,
855 .channels_max = 2,
856 .rates = SNDRV_PCM_RATE_8000_48000,
857 .formats = SNDRV_PCM_FMTBIT_S16_LE,
858 },
859 .ops = &mtk_afe_i2s_ops,
860 .symmetric_rates = 1,
861 },
862};
863
864static struct snd_soc_dai_driver mtk_afe_hdmi_dais[] = {
865 /* FE DAIs */
866 {
867 .name = "HDMI",
868 .id = MTK_AFE_MEMIF_HDMI,
775b07de
KC		 869 .suspend = mtk_afe_dai_suspend,
870 .resume = mtk_afe_dai_resume,
ee0bcaff
KC		 871 .playback = {
872 .stream_name = "HDMI",
873 .channels_min = 2,
874 .channels_max = 8,
875 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
876 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
877 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
878 SNDRV_PCM_RATE_192000,
879 .formats = SNDRV_PCM_FMTBIT_S16_LE,
880 },
881 .ops = &mtk_afe_dai_ops,
882 }, {
883 /* BE DAIs */
884 .name = "HDMIO",
885 .id = MTK_AFE_IO_HDMI,
886 .playback = {
887 .stream_name = "HDMIO Playback",
888 .channels_min = 2,
889 .channels_max = 8,
890 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
891 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
892 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
893 SNDRV_PCM_RATE_192000,
894 .formats = SNDRV_PCM_FMTBIT_S16_LE,
895 },
896 .ops = &mtk_afe_hdmi_ops,
897 },
898};
899
900static const struct snd_kcontrol_new mtk_afe_o03_mix[] = {
901 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0),
902};
903
904static const struct snd_kcontrol_new mtk_afe_o04_mix[] = {
905 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0),
906};
907
908static const struct snd_kcontrol_new mtk_afe_o09_mix[] = {
84f3a524 909 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 0, 1, 0),
ee0bcaff
KC		 910 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0),
911};
912
913static const struct snd_kcontrol_new mtk_afe_o10_mix[] = {
84f3a524 914 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN3, 3, 1, 0),
ee0bcaff
KC		 915 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0),
916};
917
918static const struct snd_soc_dapm_widget mtk_afe_pcm_widgets[] = {
ee0bcaff 919 /* inter-connections */
84f3a524
KC		 920 SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
921 SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0),
ee0bcaff
KC		 922 SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
923 SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
924 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
925 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
926
927 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
928 mtk_afe_o03_mix, ARRAY_SIZE(mtk_afe_o03_mix)),
929 SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
930 mtk_afe_o04_mix, ARRAY_SIZE(mtk_afe_o04_mix)),
931 SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
932 mtk_afe_o09_mix, ARRAY_SIZE(mtk_afe_o09_mix)),
933 SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
934 mtk_afe_o10_mix, ARRAY_SIZE(mtk_afe_o10_mix)),
935};
936
937static const struct snd_soc_dapm_route mtk_afe_pcm_routes[] = {
938 {"I05", NULL, "DL1"},
939 {"I06", NULL, "DL1"},
940 {"I2S Playback", NULL, "O03"},
941 {"I2S Playback", NULL, "O04"},
942 {"VUL", NULL, "O09"},
943 {"VUL", NULL, "O10"},
84f3a524
KC		 944 {"I03", NULL, "I2S Capture"},
945 {"I04", NULL, "I2S Capture"},
ee0bcaff
KC		 946 {"I17", NULL, "I2S Capture"},
947 {"I18", NULL, "I2S Capture"},
948 { "O03", "I05 Switch", "I05" },
949 { "O04", "I06 Switch", "I06" },
950 { "O09", "I17 Switch", "I17" },
84f3a524 951 { "O09", "I03 Switch", "I03" },
ee0bcaff 952 { "O10", "I18 Switch", "I18" },
84f3a524 953 { "O10", "I04 Switch", "I04" },
ee0bcaff
KC		 954};
955
ee0bcaff
KC		 956static const struct snd_soc_dapm_route mtk_afe_hdmi_routes[] = {
957 {"HDMIO Playback", NULL, "HDMI"},
958};
959
960static const struct snd_soc_component_driver mtk_afe_pcm_dai_component = {
961 .name = "mtk-afe-pcm-dai",
962 .dapm_widgets = mtk_afe_pcm_widgets,
963 .num_dapm_widgets = ARRAY_SIZE(mtk_afe_pcm_widgets),
964 .dapm_routes = mtk_afe_pcm_routes,
965 .num_dapm_routes = ARRAY_SIZE(mtk_afe_pcm_routes),
966};
967
968static const struct snd_soc_component_driver mtk_afe_hdmi_dai_component = {
969 .name = "mtk-afe-hdmi-dai",
ee0bcaff
KC		 970 .dapm_routes = mtk_afe_hdmi_routes,
971 .num_dapm_routes = ARRAY_SIZE(mtk_afe_hdmi_routes),
972};
973
974static const char *aud_clks[MTK_CLK_NUM] = {
975 [MTK_CLK_INFRASYS_AUD] = "infra_sys_audio_clk",
976 [MTK_CLK_TOP_PDN_AUD] = "top_pdn_audio",
977 [MTK_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus",
978 [MTK_CLK_I2S0_M] = "i2s0_m",
979 [MTK_CLK_I2S1_M] = "i2s1_m",
980 [MTK_CLK_I2S2_M] = "i2s2_m",
981 [MTK_CLK_I2S3_M] = "i2s3_m",
982 [MTK_CLK_I2S3_B] = "i2s3_b",
983 [MTK_CLK_BCK0] = "bck0",
984 [MTK_CLK_BCK1] = "bck1",
985};
986
987static const struct mtk_afe_memif_data memif_data[MTK_AFE_MEMIF_NUM] = {
988 {
989 .name = "DL1",
990 .id = MTK_AFE_MEMIF_DL1,
991 .reg_ofs_base = AFE_DL1_BASE,
992 .reg_ofs_cur = AFE_DL1_CUR,
993 .fs_shift = 0,
994 .mono_shift = 21,
995 .enable_shift = 1,
996 .irq_reg_cnt = AFE_IRQ_CNT1,
997 .irq_cnt_shift = 0,
998 .irq_en_shift = 0,
999 .irq_fs_shift = 4,
1000 .irq_clr_shift = 0,
fcde5a7e 1001 .msb_shift = 0,
ee0bcaff
KC		 1002 }, {
1003 .name = "DL2",
1004 .id = MTK_AFE_MEMIF_DL2,
1005 .reg_ofs_base = AFE_DL2_BASE,
1006 .reg_ofs_cur = AFE_DL2_CUR,
1007 .fs_shift = 4,
1008 .mono_shift = 22,
1009 .enable_shift = 2,
1010 .irq_reg_cnt = AFE_IRQ_CNT1,
1011 .irq_cnt_shift = 20,
1012 .irq_en_shift = 2,
1013 .irq_fs_shift = 16,
1014 .irq_clr_shift = 2,
fcde5a7e 1015 .msb_shift = 1,
ee0bcaff
KC		 1016 }, {
1017 .name = "VUL",
1018 .id = MTK_AFE_MEMIF_VUL,
1019 .reg_ofs_base = AFE_VUL_BASE,
1020 .reg_ofs_cur = AFE_VUL_CUR,
1021 .fs_shift = 16,
1022 .mono_shift = 27,
1023 .enable_shift = 3,
1024 .irq_reg_cnt = AFE_IRQ_CNT2,
1025 .irq_cnt_shift = 0,
1026 .irq_en_shift = 1,
1027 .irq_fs_shift = 8,
1028 .irq_clr_shift = 1,
fcde5a7e 1029 .msb_shift = 6,
ee0bcaff
KC		 1030 }, {
1031 .name = "DAI",
1032 .id = MTK_AFE_MEMIF_DAI,
1033 .reg_ofs_base = AFE_DAI_BASE,
1034 .reg_ofs_cur = AFE_DAI_CUR,
1035 .fs_shift = 24,
1036 .mono_shift = -1,
1037 .enable_shift = 4,
1038 .irq_reg_cnt = AFE_IRQ_CNT2,
1039 .irq_cnt_shift = 20,
1040 .irq_en_shift = 3,
1041 .irq_fs_shift = 20,
1042 .irq_clr_shift = 3,
fcde5a7e 1043 .msb_shift = 5,
ee0bcaff
KC		 1044 }, {
1045 .name = "AWB",
1046 .id = MTK_AFE_MEMIF_AWB,
1047 .reg_ofs_base = AFE_AWB_BASE,
1048 .reg_ofs_cur = AFE_AWB_CUR,
1049 .fs_shift = 12,
1050 .mono_shift = 24,
1051 .enable_shift = 6,
1052 .irq_reg_cnt = AFE_IRQ_CNT7,
1053 .irq_cnt_shift = 0,
1054 .irq_en_shift = 14,
1055 .irq_fs_shift = 24,
1056 .irq_clr_shift = 6,
fcde5a7e 1057 .msb_shift = 3,
ee0bcaff
KC		 1058 }, {
1059 .name = "MOD_DAI",
1060 .id = MTK_AFE_MEMIF_MOD_DAI,
1061 .reg_ofs_base = AFE_MOD_PCM_BASE,
1062 .reg_ofs_cur = AFE_MOD_PCM_CUR,
1063 .fs_shift = 30,
1064 .mono_shift = 30,
1065 .enable_shift = 7,
1066 .irq_reg_cnt = AFE_IRQ_CNT2,
1067 .irq_cnt_shift = 20,
1068 .irq_en_shift = 3,
1069 .irq_fs_shift = 20,
1070 .irq_clr_shift = 3,
fcde5a7e 1071 .msb_shift = 4,
ee0bcaff
KC		 1072 }, {
1073 .name = "HDMI",
1074 .id = MTK_AFE_MEMIF_HDMI,
1075 .reg_ofs_base = AFE_HDMI_OUT_BASE,
1076 .reg_ofs_cur = AFE_HDMI_OUT_CUR,
1077 .fs_shift = -1,
1078 .mono_shift = -1,
1079 .enable_shift = -1,
1080 .irq_reg_cnt = AFE_IRQ_CNT5,
1081 .irq_cnt_shift = 0,
1082 .irq_en_shift = 12,
1083 .irq_fs_shift = -1,
1084 .irq_clr_shift = 4,
fcde5a7e 1085 .msb_shift = 8,
ee0bcaff
KC		 1086 },
1087};
1088
1089static const struct regmap_config mtk_afe_regmap_config = {
1090 .reg_bits = 32,
1091 .reg_stride = 4,
1092 .val_bits = 32,
1093 .max_register = AFE_ADDA2_TOP_CON0,
1094 .cache_type = REGCACHE_NONE,
1095};
1096
1097static irqreturn_t mtk_afe_irq_handler(int irq, void *dev_id)
1098{
1099 struct mtk_afe *afe = dev_id;
8d6f88ce 1100 unsigned int reg_value;
ee0bcaff
KC		 1101 int i, ret;
1102
1103 ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &reg_value);
1104 if (ret) {
1105 dev_err(afe->dev, "%s irq status err\n", __func__);
1106 reg_value = AFE_IRQ_STATUS_BITS;
1107 goto err_irq;
1108 }
1109
1110 for (i = 0; i < MTK_AFE_MEMIF_NUM; i++) {
1111 struct mtk_afe_memif *memif = &afe->memif[i];
1112
1113 if (!(reg_value & (1 << memif->data->irq_clr_shift)))
1114 continue;
1115
ee0bcaff
KC		 1116 snd_pcm_period_elapsed(memif->substream);
1117 }
1118
1119err_irq:
1120 /* clear irq */
1121 regmap_write(afe->regmap, AFE_IRQ_CLR, reg_value & AFE_IRQ_STATUS_BITS);
1122
1123 return IRQ_HANDLED;
1124}
1125
1126static int mtk_afe_runtime_suspend(struct device *dev)
1127{
1128 struct mtk_afe *afe = dev_get_drvdata(dev);
1129
c1f2a342
KC		 1130 /* disable AFE */
1131 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0);
1132
ee0bcaff
KC		 1133 /* disable AFE clk */
1134 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
1135 AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE);
1136
1137 clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);
1138 clk_disable_unprepare(afe->clocks[MTK_CLK_BCK1]);
1139 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1140 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1141 clk_disable_unprepare(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1142 return 0;
1143}
1144
1145static int mtk_afe_runtime_resume(struct device *dev)
1146{
1147 struct mtk_afe *afe = dev_get_drvdata(dev);
1148 int ret;
1149
1150 ret = clk_prepare_enable(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1151 if (ret)
1152 return ret;
1153
1154 ret = clk_prepare_enable(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1155 if (ret)
1156 goto err_infra;
1157
1158 ret = clk_prepare_enable(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1159 if (ret)
1160 goto err_top_aud_bus;
1161
1162 ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK0]);
1163 if (ret)
1164 goto err_top_aud;
1165
1166 ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK1]);
1167 if (ret)
1168 goto err_bck0;
1169
1170 /* enable AFE clk */
1171 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0);
1172
1173 /* set O3/O4 16bits */
1174 regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
1175 AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0);
1176
1177 /* unmask all IRQs */
1178 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff);
c1f2a342
KC		 1179
1180 /* enable AFE */
1181 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
ee0bcaff
KC		 1182 return 0;
1183
1184err_bck0:
1185 clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);
1186err_top_aud:
1187 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1188err_top_aud_bus:
1189 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1190err_infra:
1191 clk_disable_unprepare(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1192 return ret;
1193}
1194
1195static int mtk_afe_init_audio_clk(struct mtk_afe *afe)
1196{
1197 size_t i;
1198
1199 for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
1200 afe->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
1201 if (IS_ERR(afe->clocks[i])) {
1202 dev_err(afe->dev, "%s devm_clk_get %s fail\n",
1203 __func__, aud_clks[i]);
1204 return PTR_ERR(afe->clocks[i]);
1205 }
1206 }
1207 clk_set_rate(afe->clocks[MTK_CLK_BCK0], 22579200); /* 22M */
1208 clk_set_rate(afe->clocks[MTK_CLK_BCK1], 24576000); /* 24M */
1209 return 0;
1210}
1211
1212static int mtk_afe_pcm_dev_probe(struct platform_device *pdev)
1213{
1214 int ret, i;
1215 unsigned int irq_id;
1216 struct mtk_afe *afe;
1217 struct resource *res;
1218
fcde5a7e
PL		 1219 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));
1220 if (ret)
1221 return ret;
1222
ee0bcaff
KC		 1223 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1224 if (!afe)
1225 return -ENOMEM;
1226
1227 afe->dev = &pdev->dev;
1228
1229 irq_id = platform_get_irq(pdev, 0);
1230 if (!irq_id) {
1231 dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name);
1232 return -ENXIO;
1233 }
1234 ret = devm_request_irq(afe->dev, irq_id, mtk_afe_irq_handler,
1235 0, "Afe_ISR_Handle", (void *)afe);
1236 if (ret) {
1237 dev_err(afe->dev, "could not request_irq\n");
1238 return ret;
1239 }
1240
1241 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1242 afe->base_addr = devm_ioremap_resource(&pdev->dev, res);
1243 if (IS_ERR(afe->base_addr))
1244 return PTR_ERR(afe->base_addr);
1245
1246 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
1247 &mtk_afe_regmap_config);
1248 if (IS_ERR(afe->regmap))
1249 return PTR_ERR(afe->regmap);
1250
1251 /* initial audio related clock */
1252 ret = mtk_afe_init_audio_clk(afe);
1253 if (ret) {
1254 dev_err(afe->dev, "mtk_afe_init_audio_clk fail\n");
1255 return ret;
1256 }
1257
1258 for (i = 0; i < MTK_AFE_MEMIF_NUM; i++)
1259 afe->memif[i].data = &memif_data[i];
1260
1261 platform_set_drvdata(pdev, afe);
1262
1263 pm_runtime_enable(&pdev->dev);
1264 if (!pm_runtime_enabled(&pdev->dev)) {
1265 ret = mtk_afe_runtime_resume(&pdev->dev);
1266 if (ret)
1267 goto err_pm_disable;
1268 }
1269
1270 ret = snd_soc_register_platform(&pdev->dev, &mtk_afe_pcm_platform);
1271 if (ret)
1272 goto err_pm_disable;
1273
1274 ret = snd_soc_register_component(&pdev->dev,
1275 &mtk_afe_pcm_dai_component,
1276 mtk_afe_pcm_dais,
1277 ARRAY_SIZE(mtk_afe_pcm_dais));
1278 if (ret)
1279 goto err_platform;
1280
1281 ret = snd_soc_register_component(&pdev->dev,
1282 &mtk_afe_hdmi_dai_component,
1283 mtk_afe_hdmi_dais,
1284 ARRAY_SIZE(mtk_afe_hdmi_dais));
1285 if (ret)
1286 goto err_comp;
1287
1288 dev_info(&pdev->dev, "MTK AFE driver initialized.\n");
1289 return 0;
1290
1291err_comp:
1292 snd_soc_unregister_component(&pdev->dev);
1293err_platform:
1294 snd_soc_unregister_platform(&pdev->dev);
1295err_pm_disable:
1296 pm_runtime_disable(&pdev->dev);
1297 return ret;
1298}
1299
1300static int mtk_afe_pcm_dev_remove(struct platform_device *pdev)
1301{
1302 pm_runtime_disable(&pdev->dev);
4623a614
KC		 1303 if (!pm_runtime_status_suspended(&pdev->dev))
1304 mtk_afe_runtime_suspend(&pdev->dev);
ee0bcaff
KC		 1305 snd_soc_unregister_component(&pdev->dev);
1306 snd_soc_unregister_platform(&pdev->dev);
1307 return 0;
1308}
1309
1310static const struct of_device_id mtk_afe_pcm_dt_match[] = {
1311 { .compatible = "mediatek,mt8173-afe-pcm", },
1312 { }
1313};
1314MODULE_DEVICE_TABLE(of, mtk_afe_pcm_dt_match);
1315
1316static const struct dev_pm_ops mtk_afe_pm_ops = {
1317 SET_RUNTIME_PM_OPS(mtk_afe_runtime_suspend, mtk_afe_runtime_resume,
1318 NULL)
1319};
1320
1321static struct platform_driver mtk_afe_pcm_driver = {
1322 .driver = {
1323 .name = "mtk-afe-pcm",
ee0bcaff
KC		 1324 .of_match_table = mtk_afe_pcm_dt_match,
1325 .pm = &mtk_afe_pm_ops,
1326 },
1327 .probe = mtk_afe_pcm_dev_probe,
1328 .remove = mtk_afe_pcm_dev_remove,
1329};
1330
1331module_platform_driver(mtk_afe_pcm_driver);
1332
1333MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver");
1334MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>");
1335MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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