ASoC: mediatek: Use current HW pointer for pointer callback
[deliverable/linux.git] / sound / soc / mediatek / mtk-afe-pcm.c
CommitLineData
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1/*
2 * Mediatek ALSA SoC AFE platform driver
3 *
4 * Copyright (c) 2015 MediaTek Inc.
5 * Author: Koro Chen <koro.chen@mediatek.com>
6 * Sascha Hauer <s.hauer@pengutronix.de>
7 * Hidalgo Huang <hidalgo.huang@mediatek.com>
8 * Ir Lian <ir.lian@mediatek.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 and
12 * only version 2 as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/delay.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/pm_runtime.h>
25#include <sound/soc.h>
26#include "mtk-afe-common.h"
27
28/*****************************************************************************
29 * R E G I S T E R D E F I N I T I O N
30 *****************************************************************************/
31#define AUDIO_TOP_CON0 0x0000
32#define AUDIO_TOP_CON1 0x0004
33#define AFE_DAC_CON0 0x0010
34#define AFE_DAC_CON1 0x0014
35#define AFE_I2S_CON1 0x0034
36#define AFE_I2S_CON2 0x0038
37#define AFE_CONN_24BIT 0x006c
38
39#define AFE_CONN1 0x0024
40#define AFE_CONN2 0x0028
41#define AFE_CONN7 0x0460
42#define AFE_CONN8 0x0464
43#define AFE_HDMI_CONN0 0x0390
44
45/* Memory interface */
46#define AFE_DL1_BASE 0x0040
47#define AFE_DL1_CUR 0x0044
775b07de 48#define AFE_DL1_END 0x0048
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49#define AFE_DL2_BASE 0x0050
50#define AFE_DL2_CUR 0x0054
51#define AFE_AWB_BASE 0x0070
52#define AFE_AWB_CUR 0x007c
53#define AFE_VUL_BASE 0x0080
54#define AFE_VUL_CUR 0x008c
775b07de 55#define AFE_VUL_END 0x0088
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56#define AFE_DAI_BASE 0x0090
57#define AFE_DAI_CUR 0x009c
58#define AFE_MOD_PCM_BASE 0x0330
59#define AFE_MOD_PCM_CUR 0x033c
60#define AFE_HDMI_OUT_BASE 0x0374
61#define AFE_HDMI_OUT_CUR 0x0378
775b07de 62#define AFE_HDMI_OUT_END 0x037c
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63
64#define AFE_ADDA2_TOP_CON0 0x0600
65
66#define AFE_HDMI_OUT_CON0 0x0370
67
68#define AFE_IRQ_MCU_CON 0x03a0
69#define AFE_IRQ_STATUS 0x03a4
70#define AFE_IRQ_CLR 0x03a8
71#define AFE_IRQ_CNT1 0x03ac
72#define AFE_IRQ_CNT2 0x03b0
73#define AFE_IRQ_MCU_EN 0x03b4
74#define AFE_IRQ_CNT5 0x03bc
75#define AFE_IRQ_CNT7 0x03dc
76
77#define AFE_TDM_CON1 0x0548
78#define AFE_TDM_CON2 0x054c
79
80#define AFE_BASE_END_OFFSET 8
81#define AFE_IRQ_STATUS_BITS 0xff
82
83/* AUDIO_TOP_CON0 (0x0000) */
84#define AUD_TCON0_PDN_SPDF (0x1 << 21)
85#define AUD_TCON0_PDN_HDMI (0x1 << 20)
86#define AUD_TCON0_PDN_24M (0x1 << 9)
87#define AUD_TCON0_PDN_22M (0x1 << 8)
88#define AUD_TCON0_PDN_AFE (0x1 << 2)
89
90/* AFE_I2S_CON1 (0x0034) */
91#define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12)
92#define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8)
93#define AFE_I2S_CON1_FORMAT_I2S (0x1 << 3)
94#define AFE_I2S_CON1_EN (0x1 << 0)
95
96/* AFE_I2S_CON2 (0x0038) */
97#define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12)
98#define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8)
99#define AFE_I2S_CON2_FORMAT_I2S (0x1 << 3)
100#define AFE_I2S_CON2_EN (0x1 << 0)
101
102/* AFE_CONN_24BIT (0x006c) */
103#define AFE_CONN_24BIT_O04 (0x1 << 4)
104#define AFE_CONN_24BIT_O03 (0x1 << 3)
105
106/* AFE_HDMI_CONN0 (0x0390) */
107#define AFE_HDMI_CONN0_O37_I37 (0x7 << 21)
108#define AFE_HDMI_CONN0_O36_I36 (0x6 << 18)
109#define AFE_HDMI_CONN0_O35_I33 (0x3 << 15)
110#define AFE_HDMI_CONN0_O34_I32 (0x2 << 12)
111#define AFE_HDMI_CONN0_O33_I35 (0x5 << 9)
112#define AFE_HDMI_CONN0_O32_I34 (0x4 << 6)
113#define AFE_HDMI_CONN0_O31_I31 (0x1 << 3)
114#define AFE_HDMI_CONN0_O30_I30 (0x0 << 0)
115
116/* AFE_TDM_CON1 (0x0548) */
117#define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24)
118#define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12)
119#define AFE_TDM_CON1_WLEN_32BIT (0x2 << 8)
120#define AFE_TDM_CON1_MSB_ALIGNED (0x1 << 4)
121#define AFE_TDM_CON1_1_BCK_DELAY (0x1 << 3)
122#define AFE_TDM_CON1_BCK_INV (0x1 << 1)
123#define AFE_TDM_CON1_EN (0x1 << 0)
124
125enum afe_tdm_ch_start {
126 AFE_TDM_CH_START_O30_O31 = 0,
127 AFE_TDM_CH_START_O32_O33,
128 AFE_TDM_CH_START_O34_O35,
129 AFE_TDM_CH_START_O36_O37,
130 AFE_TDM_CH_ZERO,
131};
132
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133static const unsigned int mtk_afe_backup_list[] = {
134 AUDIO_TOP_CON0,
135 AFE_CONN1,
136 AFE_CONN2,
137 AFE_CONN7,
138 AFE_CONN8,
139 AFE_DAC_CON1,
140 AFE_DL1_BASE,
141 AFE_DL1_END,
142 AFE_VUL_BASE,
143 AFE_VUL_END,
144 AFE_HDMI_OUT_BASE,
145 AFE_HDMI_OUT_END,
146 AFE_HDMI_CONN0,
147 AFE_DAC_CON0,
148};
149
150struct mtk_afe {
151 /* address for ioremap audio hardware register */
152 void __iomem *base_addr;
153 struct device *dev;
154 struct regmap *regmap;
155 struct mtk_afe_memif memif[MTK_AFE_MEMIF_NUM];
156 struct clk *clocks[MTK_CLK_NUM];
157 unsigned int backup_regs[ARRAY_SIZE(mtk_afe_backup_list)];
158 bool suspended;
159};
160
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161static const struct snd_pcm_hardware mtk_afe_hardware = {
162 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
163 SNDRV_PCM_INFO_MMAP_VALID),
164 .buffer_bytes_max = 256 * 1024,
165 .period_bytes_min = 512,
166 .period_bytes_max = 128 * 1024,
167 .periods_min = 2,
168 .periods_max = 256,
169 .fifo_size = 0,
170};
171
172static snd_pcm_uframes_t mtk_afe_pcm_pointer
173 (struct snd_pcm_substream *substream)
174{
175 struct snd_soc_pcm_runtime *rtd = substream->private_data;
176 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
177 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
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178 unsigned int hw_ptr;
179 int ret;
180
181 ret = regmap_read(afe->regmap, memif->data->reg_ofs_cur, &hw_ptr);
182 if (ret || hw_ptr == 0) {
183 dev_err(afe->dev, "%s hw_ptr err\n", __func__);
184 hw_ptr = memif->phys_buf_addr;
185 }
ee0bcaff 186
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187 return bytes_to_frames(substream->runtime,
188 hw_ptr - memif->phys_buf_addr);
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189}
190
191static const struct snd_pcm_ops mtk_afe_pcm_ops = {
192 .ioctl = snd_pcm_lib_ioctl,
193 .pointer = mtk_afe_pcm_pointer,
194};
195
196static int mtk_afe_pcm_new(struct snd_soc_pcm_runtime *rtd)
197{
198 size_t size;
199 struct snd_card *card = rtd->card->snd_card;
200 struct snd_pcm *pcm = rtd->pcm;
201
202 size = mtk_afe_hardware.buffer_bytes_max;
203
204 return snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
205 card->dev, size, size);
206}
207
208static void mtk_afe_pcm_free(struct snd_pcm *pcm)
209{
210 snd_pcm_lib_preallocate_free_for_all(pcm);
211}
212
213static const struct snd_soc_platform_driver mtk_afe_pcm_platform = {
214 .ops = &mtk_afe_pcm_ops,
215 .pcm_new = mtk_afe_pcm_new,
216 .pcm_free = mtk_afe_pcm_free,
217};
218
219struct mtk_afe_rate {
220 unsigned int rate;
221 unsigned int regvalue;
222};
223
224static const struct mtk_afe_rate mtk_afe_i2s_rates[] = {
225 { .rate = 8000, .regvalue = 0 },
226 { .rate = 11025, .regvalue = 1 },
227 { .rate = 12000, .regvalue = 2 },
228 { .rate = 16000, .regvalue = 4 },
229 { .rate = 22050, .regvalue = 5 },
230 { .rate = 24000, .regvalue = 6 },
231 { .rate = 32000, .regvalue = 8 },
232 { .rate = 44100, .regvalue = 9 },
233 { .rate = 48000, .regvalue = 10 },
234 { .rate = 88000, .regvalue = 11 },
235 { .rate = 96000, .regvalue = 12 },
236 { .rate = 174000, .regvalue = 13 },
237 { .rate = 192000, .regvalue = 14 },
238};
239
240static int mtk_afe_i2s_fs(unsigned int sample_rate)
241{
242 int i;
243
244 for (i = 0; i < ARRAY_SIZE(mtk_afe_i2s_rates); i++)
245 if (mtk_afe_i2s_rates[i].rate == sample_rate)
246 return mtk_afe_i2s_rates[i].regvalue;
247
248 return -EINVAL;
249}
250
251static int mtk_afe_set_i2s(struct mtk_afe *afe, unsigned int rate)
252{
253 unsigned int val;
254 int fs = mtk_afe_i2s_fs(rate);
255
256 if (fs < 0)
257 return -EINVAL;
258
259 /* from external ADC */
260 regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1);
261
262 /* set input */
263 val = AFE_I2S_CON2_LOW_JITTER_CLK |
264 AFE_I2S_CON2_RATE(fs) |
265 AFE_I2S_CON2_FORMAT_I2S;
266
267 regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val);
268
269 /* set output */
270 val = AFE_I2S_CON1_LOW_JITTER_CLK |
271 AFE_I2S_CON1_RATE(fs) |
272 AFE_I2S_CON1_FORMAT_I2S;
273
274 regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val);
275 return 0;
276}
277
278static void mtk_afe_set_i2s_enable(struct mtk_afe *afe, bool enable)
279{
280 unsigned int val;
281
282 regmap_read(afe->regmap, AFE_I2S_CON2, &val);
283 if (!!(val & AFE_I2S_CON2_EN) == enable)
284 return; /* must skip soft reset */
285
286 /* I2S soft reset begin */
287 regmap_update_bits(afe->regmap, AUDIO_TOP_CON1, 0x4, 0x4);
288
289 /* input */
290 regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable);
291
292 /* output */
293 regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable);
294
295 /* I2S soft reset end */
296 udelay(1);
297 regmap_update_bits(afe->regmap, AUDIO_TOP_CON1, 0x4, 0);
298}
299
300static int mtk_afe_dais_enable_clks(struct mtk_afe *afe,
301 struct clk *m_ck, struct clk *b_ck)
302{
303 int ret;
304
305 if (m_ck) {
306 ret = clk_prepare_enable(m_ck);
307 if (ret) {
308 dev_err(afe->dev, "Failed to enable m_ck\n");
309 return ret;
310 }
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311 }
312
313 if (b_ck) {
314 ret = clk_prepare_enable(b_ck);
315 if (ret) {
316 dev_err(afe->dev, "Failed to enable b_ck\n");
317 return ret;
318 }
319 }
320 return 0;
321}
322
323static int mtk_afe_dais_set_clks(struct mtk_afe *afe,
324 struct clk *m_ck, unsigned int mck_rate,
325 struct clk *b_ck, unsigned int bck_rate)
326{
327 int ret;
328
329 if (m_ck) {
330 ret = clk_set_rate(m_ck, mck_rate);
331 if (ret) {
332 dev_err(afe->dev, "Failed to set m_ck rate\n");
333 return ret;
334 }
335 }
336
337 if (b_ck) {
338 ret = clk_set_rate(b_ck, bck_rate);
339 if (ret) {
340 dev_err(afe->dev, "Failed to set b_ck rate\n");
341 return ret;
342 }
343 }
344 return 0;
345}
346
347static void mtk_afe_dais_disable_clks(struct mtk_afe *afe,
348 struct clk *m_ck, struct clk *b_ck)
349{
b45e68df 350 if (m_ck)
ee0bcaff 351 clk_disable_unprepare(m_ck);
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352 if (b_ck)
353 clk_disable_unprepare(b_ck);
354}
355
356static int mtk_afe_i2s_startup(struct snd_pcm_substream *substream,
357 struct snd_soc_dai *dai)
358{
359 struct snd_soc_pcm_runtime *rtd = substream->private_data;
360 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
361
362 if (dai->active)
363 return 0;
364
365 mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
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366 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
367 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);
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368 return 0;
369}
370
371static void mtk_afe_i2s_shutdown(struct snd_pcm_substream *substream,
372 struct snd_soc_dai *dai)
373{
374 struct snd_soc_pcm_runtime *rtd = substream->private_data;
375 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
376
377 if (dai->active)
378 return;
379
380 mtk_afe_set_i2s_enable(afe, false);
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381 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
382 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,
383 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);
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384 mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
385
386 /* disable AFE */
387 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0);
388}
389
390static int mtk_afe_i2s_prepare(struct snd_pcm_substream *substream,
391 struct snd_soc_dai *dai)
392{
393 struct snd_soc_pcm_runtime *rtd = substream->private_data;
394 struct snd_pcm_runtime * const runtime = substream->runtime;
395 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
396 int ret;
397
398 mtk_afe_dais_set_clks(afe,
399 afe->clocks[MTK_CLK_I2S1_M], runtime->rate * 256,
400 NULL, 0);
401 /* config I2S */
402 ret = mtk_afe_set_i2s(afe, substream->runtime->rate);
403 if (ret)
404 return ret;
405
406 mtk_afe_set_i2s_enable(afe, true);
407
408 return 0;
409}
410
411static int mtk_afe_hdmi_startup(struct snd_pcm_substream *substream,
412 struct snd_soc_dai *dai)
413{
414 struct snd_soc_pcm_runtime *rtd = substream->private_data;
415 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
416
417 if (dai->active)
418 return 0;
419
420 mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S3_M],
421 afe->clocks[MTK_CLK_I2S3_B]);
422 return 0;
423}
424
425static void mtk_afe_hdmi_shutdown(struct snd_pcm_substream *substream,
426 struct snd_soc_dai *dai)
427{
428 struct snd_soc_pcm_runtime *rtd = substream->private_data;
429 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
430
431 if (dai->active)
432 return;
433
434 mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S3_M],
435 afe->clocks[MTK_CLK_I2S3_B]);
436
437 /* disable AFE */
438 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0);
439}
440
441static int mtk_afe_hdmi_prepare(struct snd_pcm_substream *substream,
442 struct snd_soc_dai *dai)
443{
444 struct snd_soc_pcm_runtime *rtd = substream->private_data;
445 struct snd_pcm_runtime * const runtime = substream->runtime;
446 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
447 unsigned int val;
448
449 mtk_afe_dais_set_clks(afe,
450 afe->clocks[MTK_CLK_I2S3_M], runtime->rate * 128,
451 afe->clocks[MTK_CLK_I2S3_B],
452 runtime->rate * runtime->channels * 32);
453
454 val = AFE_TDM_CON1_BCK_INV |
455 AFE_TDM_CON1_1_BCK_DELAY |
456 AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */
457 AFE_TDM_CON1_WLEN_32BIT |
458 AFE_TDM_CON1_32_BCK_CYCLES |
459 AFE_TDM_CON1_LRCK_WIDTH(32);
460 regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val);
461
462 /* set tdm2 config */
463 switch (runtime->channels) {
464 case 1:
465 case 2:
466 val = AFE_TDM_CH_START_O30_O31;
467 val |= (AFE_TDM_CH_ZERO << 4);
468 val |= (AFE_TDM_CH_ZERO << 8);
469 val |= (AFE_TDM_CH_ZERO << 12);
470 break;
471 case 3:
472 case 4:
473 val = AFE_TDM_CH_START_O30_O31;
474 val |= (AFE_TDM_CH_START_O32_O33 << 4);
475 val |= (AFE_TDM_CH_ZERO << 8);
476 val |= (AFE_TDM_CH_ZERO << 12);
477 break;
478 case 5:
479 case 6:
480 val = AFE_TDM_CH_START_O30_O31;
481 val |= (AFE_TDM_CH_START_O32_O33 << 4);
482 val |= (AFE_TDM_CH_START_O34_O35 << 8);
483 val |= (AFE_TDM_CH_ZERO << 12);
484 break;
485 case 7:
486 case 8:
487 val = AFE_TDM_CH_START_O30_O31;
488 val |= (AFE_TDM_CH_START_O32_O33 << 4);
489 val |= (AFE_TDM_CH_START_O34_O35 << 8);
490 val |= (AFE_TDM_CH_START_O36_O37 << 12);
491 break;
492 default:
493 val = 0;
494 }
495 regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val);
496
497 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
498 0x000000f0, runtime->channels << 4);
499 return 0;
500}
501
502static int mtk_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd,
503 struct snd_soc_dai *dai)
504{
505 struct snd_soc_pcm_runtime *rtd = substream->private_data;
506 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
507
508 dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name);
509
510 switch (cmd) {
511 case SNDRV_PCM_TRIGGER_START:
512 case SNDRV_PCM_TRIGGER_RESUME:
513 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
514 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0);
515
516 /* set connections: O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */
517 regmap_write(afe->regmap, AFE_HDMI_CONN0,
518 AFE_HDMI_CONN0_O30_I30 | AFE_HDMI_CONN0_O31_I31 |
519 AFE_HDMI_CONN0_O32_I34 | AFE_HDMI_CONN0_O33_I35 |
520 AFE_HDMI_CONN0_O34_I32 | AFE_HDMI_CONN0_O35_I33 |
521 AFE_HDMI_CONN0_O36_I36 | AFE_HDMI_CONN0_O37_I37);
522
523 /* enable Out control */
524 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1);
525
526 /* enable tdm */
527 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1);
528
529 return 0;
530 case SNDRV_PCM_TRIGGER_STOP:
531 case SNDRV_PCM_TRIGGER_SUSPEND:
532 /* disable tdm */
533 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0);
534
535 /* disable Out control */
536 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0);
537
538 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
539 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF,
540 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF);
541
542 return 0;
543 default:
544 return -EINVAL;
545 }
546}
547
548static int mtk_afe_dais_startup(struct snd_pcm_substream *substream,
549 struct snd_soc_dai *dai)
550{
551 struct snd_soc_pcm_runtime *rtd = substream->private_data;
552 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
553 struct snd_pcm_runtime *runtime = substream->runtime;
554 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
555 int ret;
556
557 memif->substream = substream;
558
559 snd_soc_set_runtime_hwparams(substream, &mtk_afe_hardware);
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560
561 /*
562 * Capture cannot use ping-pong buffer since hw_ptr at IRQ may be
563 * smaller than period_size due to AFE's internal buffer.
564 * This easily leads to overrun when avail_min is period_size.
565 * One more period can hold the possible unread buffer.
566 */
567 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
568 ret = snd_pcm_hw_constraint_minmax(runtime,
569 SNDRV_PCM_HW_PARAM_PERIODS,
570 3,
571 mtk_afe_hardware.periods_max);
572 if (ret < 0) {
573 dev_err(afe->dev, "hw_constraint_minmax failed\n");
574 return ret;
575 }
576 }
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577 ret = snd_pcm_hw_constraint_integer(runtime,
578 SNDRV_PCM_HW_PARAM_PERIODS);
579 if (ret < 0)
580 dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
581 return ret;
582}
583
584static void mtk_afe_dais_shutdown(struct snd_pcm_substream *substream,
585 struct snd_soc_dai *dai)
586{
587 struct snd_soc_pcm_runtime *rtd = substream->private_data;
588 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
589 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
590
591 memif->substream = NULL;
592}
593
594static int mtk_afe_dais_hw_params(struct snd_pcm_substream *substream,
595 struct snd_pcm_hw_params *params,
596 struct snd_soc_dai *dai)
597{
598 struct snd_soc_pcm_runtime *rtd = substream->private_data;
599 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
600 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
601 int ret;
602
603 dev_dbg(afe->dev,
604 "%s period = %u, rate= %u, channels=%u\n",
605 __func__, params_period_size(params), params_rate(params),
606 params_channels(params));
607
608 ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
609 if (ret < 0)
610 return ret;
611
612 memif->phys_buf_addr = substream->runtime->dma_addr;
613 memif->buffer_size = substream->runtime->dma_bytes;
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614
615 /* start */
616 regmap_write(afe->regmap,
617 memif->data->reg_ofs_base, memif->phys_buf_addr);
618 /* end */
619 regmap_write(afe->regmap,
620 memif->data->reg_ofs_base + AFE_BASE_END_OFFSET,
621 memif->phys_buf_addr + memif->buffer_size - 1);
622
623 /* set channel */
624 if (memif->data->mono_shift >= 0) {
625 unsigned int mono = (params_channels(params) == 1) ? 1 : 0;
626
627 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
628 1 << memif->data->mono_shift,
629 mono << memif->data->mono_shift);
630 }
631
632 /* set rate */
633 if (memif->data->fs_shift < 0)
634 return 0;
635 if (memif->data->id == MTK_AFE_MEMIF_DAI ||
636 memif->data->id == MTK_AFE_MEMIF_MOD_DAI) {
637 unsigned int val;
638
639 switch (params_rate(params)) {
640 case 8000:
641 val = 0;
642 break;
643 case 16000:
644 val = 1;
645 break;
646 case 32000:
647 val = 2;
648 break;
649 default:
650 return -EINVAL;
651 }
652
653 if (memif->data->id == MTK_AFE_MEMIF_DAI)
654 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
655 0x3 << memif->data->fs_shift,
656 val << memif->data->fs_shift);
657 else
658 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
659 0x3 << memif->data->fs_shift,
660 val << memif->data->fs_shift);
661
662 } else {
663 int fs = mtk_afe_i2s_fs(params_rate(params));
664
665 if (fs < 0)
666 return -EINVAL;
667
668 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
669 0xf << memif->data->fs_shift,
670 fs << memif->data->fs_shift);
671 }
672
673 return 0;
674}
675
676static int mtk_afe_dais_hw_free(struct snd_pcm_substream *substream,
677 struct snd_soc_dai *dai)
678{
679 return snd_pcm_lib_free_pages(substream);
680}
681
682static int mtk_afe_dais_prepare(struct snd_pcm_substream *substream,
683 struct snd_soc_dai *dai)
684{
685 struct snd_soc_pcm_runtime *rtd = substream->private_data;
686 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
687
688 /* enable AFE */
689 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
690 return 0;
691}
692
693static int mtk_afe_dais_trigger(struct snd_pcm_substream *substream, int cmd,
694 struct snd_soc_dai *dai)
695{
696 struct snd_soc_pcm_runtime *rtd = substream->private_data;
697 struct snd_pcm_runtime * const runtime = substream->runtime;
698 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
699 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
700 unsigned int counter = runtime->period_size;
701
702 dev_info(afe->dev, "%s %s cmd=%d\n", __func__, memif->data->name, cmd);
703
704 switch (cmd) {
705 case SNDRV_PCM_TRIGGER_START:
706 case SNDRV_PCM_TRIGGER_RESUME:
707 if (memif->data->enable_shift >= 0)
708 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
709 1 << memif->data->enable_shift,
710 1 << memif->data->enable_shift);
711
712 /* set irq counter */
713 regmap_update_bits(afe->regmap,
714 memif->data->irq_reg_cnt,
715 0x3ffff << memif->data->irq_cnt_shift,
716 counter << memif->data->irq_cnt_shift);
717
718 /* set irq fs */
719 if (memif->data->irq_fs_shift >= 0) {
720 int fs = mtk_afe_i2s_fs(runtime->rate);
721
722 if (fs < 0)
723 return -EINVAL;
724
725 regmap_update_bits(afe->regmap,
726 AFE_IRQ_MCU_CON,
727 0xf << memif->data->irq_fs_shift,
728 fs << memif->data->irq_fs_shift);
729 }
730 /* enable interrupt */
731 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CON,
732 1 << memif->data->irq_en_shift,
733 1 << memif->data->irq_en_shift);
734
735 return 0;
736 case SNDRV_PCM_TRIGGER_STOP:
737 case SNDRV_PCM_TRIGGER_SUSPEND:
738 if (memif->data->enable_shift >= 0)
739 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
740 1 << memif->data->enable_shift, 0);
741 /* disable interrupt */
742 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CON,
743 1 << memif->data->irq_en_shift,
744 0 << memif->data->irq_en_shift);
745 /* and clear pending IRQ */
746 regmap_write(afe->regmap, AFE_IRQ_CLR,
747 1 << memif->data->irq_clr_shift);
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748 return 0;
749 default:
750 return -EINVAL;
751 }
752}
753
754/* FE DAIs */
755static const struct snd_soc_dai_ops mtk_afe_dai_ops = {
756 .startup = mtk_afe_dais_startup,
757 .shutdown = mtk_afe_dais_shutdown,
758 .hw_params = mtk_afe_dais_hw_params,
759 .hw_free = mtk_afe_dais_hw_free,
760 .prepare = mtk_afe_dais_prepare,
761 .trigger = mtk_afe_dais_trigger,
762};
763
764/* BE DAIs */
765static const struct snd_soc_dai_ops mtk_afe_i2s_ops = {
766 .startup = mtk_afe_i2s_startup,
767 .shutdown = mtk_afe_i2s_shutdown,
768 .prepare = mtk_afe_i2s_prepare,
769};
770
771static const struct snd_soc_dai_ops mtk_afe_hdmi_ops = {
772 .startup = mtk_afe_hdmi_startup,
773 .shutdown = mtk_afe_hdmi_shutdown,
774 .prepare = mtk_afe_hdmi_prepare,
775 .trigger = mtk_afe_hdmi_trigger,
776
777};
778
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779static int mtk_afe_runtime_suspend(struct device *dev);
780static int mtk_afe_runtime_resume(struct device *dev);
781
782static int mtk_afe_dai_suspend(struct snd_soc_dai *dai)
783{
784 struct mtk_afe *afe = snd_soc_dai_get_drvdata(dai);
785 int i;
786
787 dev_dbg(afe->dev, "%s\n", __func__);
788 if (pm_runtime_status_suspended(afe->dev) || afe->suspended)
789 return 0;
790
791 for (i = 0; i < ARRAY_SIZE(mtk_afe_backup_list); i++)
792 regmap_read(afe->regmap, mtk_afe_backup_list[i],
793 &afe->backup_regs[i]);
794
795 afe->suspended = true;
796 mtk_afe_runtime_suspend(afe->dev);
797 return 0;
798}
799
800static int mtk_afe_dai_resume(struct snd_soc_dai *dai)
801{
802 struct mtk_afe *afe = snd_soc_dai_get_drvdata(dai);
803 int i = 0;
804
805 dev_dbg(afe->dev, "%s\n", __func__);
806 if (pm_runtime_status_suspended(afe->dev) || !afe->suspended)
807 return 0;
808
809 mtk_afe_runtime_resume(afe->dev);
810
811 for (i = 0; i < ARRAY_SIZE(mtk_afe_backup_list); i++)
812 regmap_write(afe->regmap, mtk_afe_backup_list[i],
813 afe->backup_regs[i]);
814
815 afe->suspended = false;
816 return 0;
817}
818
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819static struct snd_soc_dai_driver mtk_afe_pcm_dais[] = {
820 /* FE DAIs: memory intefaces to CPU */
821 {
822 .name = "DL1", /* downlink 1 */
823 .id = MTK_AFE_MEMIF_DL1,
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824 .suspend = mtk_afe_dai_suspend,
825 .resume = mtk_afe_dai_resume,
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826 .playback = {
827 .stream_name = "DL1",
828 .channels_min = 1,
829 .channels_max = 2,
830 .rates = SNDRV_PCM_RATE_8000_48000,
831 .formats = SNDRV_PCM_FMTBIT_S16_LE,
832 },
833 .ops = &mtk_afe_dai_ops,
834 }, {
835 .name = "VUL", /* voice uplink */
836 .id = MTK_AFE_MEMIF_VUL,
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837 .suspend = mtk_afe_dai_suspend,
838 .resume = mtk_afe_dai_resume,
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839 .capture = {
840 .stream_name = "VUL",
841 .channels_min = 1,
842 .channels_max = 2,
843 .rates = SNDRV_PCM_RATE_8000_48000,
844 .formats = SNDRV_PCM_FMTBIT_S16_LE,
845 },
846 .ops = &mtk_afe_dai_ops,
847 }, {
848 /* BE DAIs */
849 .name = "I2S",
850 .id = MTK_AFE_IO_I2S,
851 .playback = {
852 .stream_name = "I2S Playback",
853 .channels_min = 1,
854 .channels_max = 2,
855 .rates = SNDRV_PCM_RATE_8000_48000,
856 .formats = SNDRV_PCM_FMTBIT_S16_LE,
857 },
858 .capture = {
859 .stream_name = "I2S Capture",
860 .channels_min = 1,
861 .channels_max = 2,
862 .rates = SNDRV_PCM_RATE_8000_48000,
863 .formats = SNDRV_PCM_FMTBIT_S16_LE,
864 },
865 .ops = &mtk_afe_i2s_ops,
866 .symmetric_rates = 1,
867 },
868};
869
870static struct snd_soc_dai_driver mtk_afe_hdmi_dais[] = {
871 /* FE DAIs */
872 {
873 .name = "HDMI",
874 .id = MTK_AFE_MEMIF_HDMI,
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875 .suspend = mtk_afe_dai_suspend,
876 .resume = mtk_afe_dai_resume,
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877 .playback = {
878 .stream_name = "HDMI",
879 .channels_min = 2,
880 .channels_max = 8,
881 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
882 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
883 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
884 SNDRV_PCM_RATE_192000,
885 .formats = SNDRV_PCM_FMTBIT_S16_LE,
886 },
887 .ops = &mtk_afe_dai_ops,
888 }, {
889 /* BE DAIs */
890 .name = "HDMIO",
891 .id = MTK_AFE_IO_HDMI,
892 .playback = {
893 .stream_name = "HDMIO Playback",
894 .channels_min = 2,
895 .channels_max = 8,
896 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
897 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
898 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
899 SNDRV_PCM_RATE_192000,
900 .formats = SNDRV_PCM_FMTBIT_S16_LE,
901 },
902 .ops = &mtk_afe_hdmi_ops,
903 },
904};
905
906static const struct snd_kcontrol_new mtk_afe_o03_mix[] = {
907 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0),
908};
909
910static const struct snd_kcontrol_new mtk_afe_o04_mix[] = {
911 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0),
912};
913
914static const struct snd_kcontrol_new mtk_afe_o09_mix[] = {
915 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0),
916};
917
918static const struct snd_kcontrol_new mtk_afe_o10_mix[] = {
919 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0),
920};
921
922static const struct snd_soc_dapm_widget mtk_afe_pcm_widgets[] = {
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923 /* inter-connections */
924 SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
925 SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
926 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
927 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
928
929 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
930 mtk_afe_o03_mix, ARRAY_SIZE(mtk_afe_o03_mix)),
931 SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
932 mtk_afe_o04_mix, ARRAY_SIZE(mtk_afe_o04_mix)),
933 SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
934 mtk_afe_o09_mix, ARRAY_SIZE(mtk_afe_o09_mix)),
935 SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
936 mtk_afe_o10_mix, ARRAY_SIZE(mtk_afe_o10_mix)),
937};
938
939static const struct snd_soc_dapm_route mtk_afe_pcm_routes[] = {
940 {"I05", NULL, "DL1"},
941 {"I06", NULL, "DL1"},
942 {"I2S Playback", NULL, "O03"},
943 {"I2S Playback", NULL, "O04"},
944 {"VUL", NULL, "O09"},
945 {"VUL", NULL, "O10"},
946 {"I17", NULL, "I2S Capture"},
947 {"I18", NULL, "I2S Capture"},
948 { "O03", "I05 Switch", "I05" },
949 { "O04", "I06 Switch", "I06" },
950 { "O09", "I17 Switch", "I17" },
951 { "O10", "I18 Switch", "I18" },
952};
953
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954static const struct snd_soc_dapm_route mtk_afe_hdmi_routes[] = {
955 {"HDMIO Playback", NULL, "HDMI"},
956};
957
958static const struct snd_soc_component_driver mtk_afe_pcm_dai_component = {
959 .name = "mtk-afe-pcm-dai",
960 .dapm_widgets = mtk_afe_pcm_widgets,
961 .num_dapm_widgets = ARRAY_SIZE(mtk_afe_pcm_widgets),
962 .dapm_routes = mtk_afe_pcm_routes,
963 .num_dapm_routes = ARRAY_SIZE(mtk_afe_pcm_routes),
964};
965
966static const struct snd_soc_component_driver mtk_afe_hdmi_dai_component = {
967 .name = "mtk-afe-hdmi-dai",
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968 .dapm_routes = mtk_afe_hdmi_routes,
969 .num_dapm_routes = ARRAY_SIZE(mtk_afe_hdmi_routes),
970};
971
972static const char *aud_clks[MTK_CLK_NUM] = {
973 [MTK_CLK_INFRASYS_AUD] = "infra_sys_audio_clk",
974 [MTK_CLK_TOP_PDN_AUD] = "top_pdn_audio",
975 [MTK_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus",
976 [MTK_CLK_I2S0_M] = "i2s0_m",
977 [MTK_CLK_I2S1_M] = "i2s1_m",
978 [MTK_CLK_I2S2_M] = "i2s2_m",
979 [MTK_CLK_I2S3_M] = "i2s3_m",
980 [MTK_CLK_I2S3_B] = "i2s3_b",
981 [MTK_CLK_BCK0] = "bck0",
982 [MTK_CLK_BCK1] = "bck1",
983};
984
985static const struct mtk_afe_memif_data memif_data[MTK_AFE_MEMIF_NUM] = {
986 {
987 .name = "DL1",
988 .id = MTK_AFE_MEMIF_DL1,
989 .reg_ofs_base = AFE_DL1_BASE,
990 .reg_ofs_cur = AFE_DL1_CUR,
991 .fs_shift = 0,
992 .mono_shift = 21,
993 .enable_shift = 1,
994 .irq_reg_cnt = AFE_IRQ_CNT1,
995 .irq_cnt_shift = 0,
996 .irq_en_shift = 0,
997 .irq_fs_shift = 4,
998 .irq_clr_shift = 0,
999 }, {
1000 .name = "DL2",
1001 .id = MTK_AFE_MEMIF_DL2,
1002 .reg_ofs_base = AFE_DL2_BASE,
1003 .reg_ofs_cur = AFE_DL2_CUR,
1004 .fs_shift = 4,
1005 .mono_shift = 22,
1006 .enable_shift = 2,
1007 .irq_reg_cnt = AFE_IRQ_CNT1,
1008 .irq_cnt_shift = 20,
1009 .irq_en_shift = 2,
1010 .irq_fs_shift = 16,
1011 .irq_clr_shift = 2,
1012 }, {
1013 .name = "VUL",
1014 .id = MTK_AFE_MEMIF_VUL,
1015 .reg_ofs_base = AFE_VUL_BASE,
1016 .reg_ofs_cur = AFE_VUL_CUR,
1017 .fs_shift = 16,
1018 .mono_shift = 27,
1019 .enable_shift = 3,
1020 .irq_reg_cnt = AFE_IRQ_CNT2,
1021 .irq_cnt_shift = 0,
1022 .irq_en_shift = 1,
1023 .irq_fs_shift = 8,
1024 .irq_clr_shift = 1,
1025 }, {
1026 .name = "DAI",
1027 .id = MTK_AFE_MEMIF_DAI,
1028 .reg_ofs_base = AFE_DAI_BASE,
1029 .reg_ofs_cur = AFE_DAI_CUR,
1030 .fs_shift = 24,
1031 .mono_shift = -1,
1032 .enable_shift = 4,
1033 .irq_reg_cnt = AFE_IRQ_CNT2,
1034 .irq_cnt_shift = 20,
1035 .irq_en_shift = 3,
1036 .irq_fs_shift = 20,
1037 .irq_clr_shift = 3,
1038 }, {
1039 .name = "AWB",
1040 .id = MTK_AFE_MEMIF_AWB,
1041 .reg_ofs_base = AFE_AWB_BASE,
1042 .reg_ofs_cur = AFE_AWB_CUR,
1043 .fs_shift = 12,
1044 .mono_shift = 24,
1045 .enable_shift = 6,
1046 .irq_reg_cnt = AFE_IRQ_CNT7,
1047 .irq_cnt_shift = 0,
1048 .irq_en_shift = 14,
1049 .irq_fs_shift = 24,
1050 .irq_clr_shift = 6,
1051 }, {
1052 .name = "MOD_DAI",
1053 .id = MTK_AFE_MEMIF_MOD_DAI,
1054 .reg_ofs_base = AFE_MOD_PCM_BASE,
1055 .reg_ofs_cur = AFE_MOD_PCM_CUR,
1056 .fs_shift = 30,
1057 .mono_shift = 30,
1058 .enable_shift = 7,
1059 .irq_reg_cnt = AFE_IRQ_CNT2,
1060 .irq_cnt_shift = 20,
1061 .irq_en_shift = 3,
1062 .irq_fs_shift = 20,
1063 .irq_clr_shift = 3,
1064 }, {
1065 .name = "HDMI",
1066 .id = MTK_AFE_MEMIF_HDMI,
1067 .reg_ofs_base = AFE_HDMI_OUT_BASE,
1068 .reg_ofs_cur = AFE_HDMI_OUT_CUR,
1069 .fs_shift = -1,
1070 .mono_shift = -1,
1071 .enable_shift = -1,
1072 .irq_reg_cnt = AFE_IRQ_CNT5,
1073 .irq_cnt_shift = 0,
1074 .irq_en_shift = 12,
1075 .irq_fs_shift = -1,
1076 .irq_clr_shift = 4,
1077 },
1078};
1079
1080static const struct regmap_config mtk_afe_regmap_config = {
1081 .reg_bits = 32,
1082 .reg_stride = 4,
1083 .val_bits = 32,
1084 .max_register = AFE_ADDA2_TOP_CON0,
1085 .cache_type = REGCACHE_NONE,
1086};
1087
1088static irqreturn_t mtk_afe_irq_handler(int irq, void *dev_id)
1089{
1090 struct mtk_afe *afe = dev_id;
8d6f88ce 1091 unsigned int reg_value;
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1092 int i, ret;
1093
1094 ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &reg_value);
1095 if (ret) {
1096 dev_err(afe->dev, "%s irq status err\n", __func__);
1097 reg_value = AFE_IRQ_STATUS_BITS;
1098 goto err_irq;
1099 }
1100
1101 for (i = 0; i < MTK_AFE_MEMIF_NUM; i++) {
1102 struct mtk_afe_memif *memif = &afe->memif[i];
1103
1104 if (!(reg_value & (1 << memif->data->irq_clr_shift)))
1105 continue;
1106
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1107 snd_pcm_period_elapsed(memif->substream);
1108 }
1109
1110err_irq:
1111 /* clear irq */
1112 regmap_write(afe->regmap, AFE_IRQ_CLR, reg_value & AFE_IRQ_STATUS_BITS);
1113
1114 return IRQ_HANDLED;
1115}
1116
1117static int mtk_afe_runtime_suspend(struct device *dev)
1118{
1119 struct mtk_afe *afe = dev_get_drvdata(dev);
1120
1121 /* disable AFE clk */
1122 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
1123 AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE);
1124
1125 clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);
1126 clk_disable_unprepare(afe->clocks[MTK_CLK_BCK1]);
1127 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1128 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1129 clk_disable_unprepare(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1130 return 0;
1131}
1132
1133static int mtk_afe_runtime_resume(struct device *dev)
1134{
1135 struct mtk_afe *afe = dev_get_drvdata(dev);
1136 int ret;
1137
1138 ret = clk_prepare_enable(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1139 if (ret)
1140 return ret;
1141
1142 ret = clk_prepare_enable(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1143 if (ret)
1144 goto err_infra;
1145
1146 ret = clk_prepare_enable(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1147 if (ret)
1148 goto err_top_aud_bus;
1149
1150 ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK0]);
1151 if (ret)
1152 goto err_top_aud;
1153
1154 ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK1]);
1155 if (ret)
1156 goto err_bck0;
1157
1158 /* enable AFE clk */
1159 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0);
1160
1161 /* set O3/O4 16bits */
1162 regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
1163 AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0);
1164
1165 /* unmask all IRQs */
1166 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff);
1167 return 0;
1168
1169err_bck0:
1170 clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);
1171err_top_aud:
1172 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1173err_top_aud_bus:
1174 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1175err_infra:
1176 clk_disable_unprepare(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1177 return ret;
1178}
1179
1180static int mtk_afe_init_audio_clk(struct mtk_afe *afe)
1181{
1182 size_t i;
1183
1184 for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
1185 afe->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
1186 if (IS_ERR(afe->clocks[i])) {
1187 dev_err(afe->dev, "%s devm_clk_get %s fail\n",
1188 __func__, aud_clks[i]);
1189 return PTR_ERR(afe->clocks[i]);
1190 }
1191 }
1192 clk_set_rate(afe->clocks[MTK_CLK_BCK0], 22579200); /* 22M */
1193 clk_set_rate(afe->clocks[MTK_CLK_BCK1], 24576000); /* 24M */
1194 return 0;
1195}
1196
1197static int mtk_afe_pcm_dev_probe(struct platform_device *pdev)
1198{
1199 int ret, i;
1200 unsigned int irq_id;
1201 struct mtk_afe *afe;
1202 struct resource *res;
1203
1204 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1205 if (!afe)
1206 return -ENOMEM;
1207
1208 afe->dev = &pdev->dev;
1209
1210 irq_id = platform_get_irq(pdev, 0);
1211 if (!irq_id) {
1212 dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name);
1213 return -ENXIO;
1214 }
1215 ret = devm_request_irq(afe->dev, irq_id, mtk_afe_irq_handler,
1216 0, "Afe_ISR_Handle", (void *)afe);
1217 if (ret) {
1218 dev_err(afe->dev, "could not request_irq\n");
1219 return ret;
1220 }
1221
1222 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1223 afe->base_addr = devm_ioremap_resource(&pdev->dev, res);
1224 if (IS_ERR(afe->base_addr))
1225 return PTR_ERR(afe->base_addr);
1226
1227 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
1228 &mtk_afe_regmap_config);
1229 if (IS_ERR(afe->regmap))
1230 return PTR_ERR(afe->regmap);
1231
1232 /* initial audio related clock */
1233 ret = mtk_afe_init_audio_clk(afe);
1234 if (ret) {
1235 dev_err(afe->dev, "mtk_afe_init_audio_clk fail\n");
1236 return ret;
1237 }
1238
1239 for (i = 0; i < MTK_AFE_MEMIF_NUM; i++)
1240 afe->memif[i].data = &memif_data[i];
1241
1242 platform_set_drvdata(pdev, afe);
1243
1244 pm_runtime_enable(&pdev->dev);
1245 if (!pm_runtime_enabled(&pdev->dev)) {
1246 ret = mtk_afe_runtime_resume(&pdev->dev);
1247 if (ret)
1248 goto err_pm_disable;
1249 }
1250
1251 ret = snd_soc_register_platform(&pdev->dev, &mtk_afe_pcm_platform);
1252 if (ret)
1253 goto err_pm_disable;
1254
1255 ret = snd_soc_register_component(&pdev->dev,
1256 &mtk_afe_pcm_dai_component,
1257 mtk_afe_pcm_dais,
1258 ARRAY_SIZE(mtk_afe_pcm_dais));
1259 if (ret)
1260 goto err_platform;
1261
1262 ret = snd_soc_register_component(&pdev->dev,
1263 &mtk_afe_hdmi_dai_component,
1264 mtk_afe_hdmi_dais,
1265 ARRAY_SIZE(mtk_afe_hdmi_dais));
1266 if (ret)
1267 goto err_comp;
1268
1269 dev_info(&pdev->dev, "MTK AFE driver initialized.\n");
1270 return 0;
1271
1272err_comp:
1273 snd_soc_unregister_component(&pdev->dev);
1274err_platform:
1275 snd_soc_unregister_platform(&pdev->dev);
1276err_pm_disable:
1277 pm_runtime_disable(&pdev->dev);
1278 return ret;
1279}
1280
1281static int mtk_afe_pcm_dev_remove(struct platform_device *pdev)
1282{
1283 pm_runtime_disable(&pdev->dev);
4623a614
KC
1284 if (!pm_runtime_status_suspended(&pdev->dev))
1285 mtk_afe_runtime_suspend(&pdev->dev);
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KC
1286 snd_soc_unregister_component(&pdev->dev);
1287 snd_soc_unregister_platform(&pdev->dev);
1288 return 0;
1289}
1290
1291static const struct of_device_id mtk_afe_pcm_dt_match[] = {
1292 { .compatible = "mediatek,mt8173-afe-pcm", },
1293 { }
1294};
1295MODULE_DEVICE_TABLE(of, mtk_afe_pcm_dt_match);
1296
1297static const struct dev_pm_ops mtk_afe_pm_ops = {
1298 SET_RUNTIME_PM_OPS(mtk_afe_runtime_suspend, mtk_afe_runtime_resume,
1299 NULL)
1300};
1301
1302static struct platform_driver mtk_afe_pcm_driver = {
1303 .driver = {
1304 .name = "mtk-afe-pcm",
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KC
1305 .of_match_table = mtk_afe_pcm_dt_match,
1306 .pm = &mtk_afe_pm_ops,
1307 },
1308 .probe = mtk_afe_pcm_dev_probe,
1309 .remove = mtk_afe_pcm_dev_remove,
1310};
1311
1312module_platform_driver(mtk_afe_pcm_driver);
1313
1314MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver");
1315MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>");
1316MODULE_LICENSE("GPL v2");
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