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2a24f2ce DA |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/init.h> | |
08641c7c SG |
21 | #include <linux/of.h> |
22 | #include <linux/of_device.h> | |
2a24f2ce DA |
23 | #include <linux/platform_device.h> |
24 | #include <linux/slab.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/delay.h> | |
76067540 | 28 | #include <linux/time.h> |
39468604 | 29 | #include <linux/fsl/mxs-dma.h> |
f755865f | 30 | #include <linux/pinctrl/consumer.h> |
2a24f2ce DA |
31 | #include <sound/core.h> |
32 | #include <sound/pcm.h> | |
33 | #include <sound/pcm_params.h> | |
34 | #include <sound/soc.h> | |
2a24f2ce DA |
35 | #include <asm/mach-types.h> |
36 | #include <mach/hardware.h> | |
37 | #include <mach/mxs.h> | |
38 | ||
39 | #include "mxs-saif.h" | |
40 | ||
41 | static struct mxs_saif *mxs_saif[2]; | |
42 | ||
76067540 DA |
43 | /* |
44 | * SAIF is a little different with other normal SOC DAIs on clock using. | |
45 | * | |
46 | * For MXS, two SAIF modules are instantiated on-chip. | |
47 | * Each SAIF has a set of clock pins and can be operating in master | |
48 | * mode simultaneously if they are connected to different off-chip codecs. | |
49 | * Also, one of the two SAIFs can master or drive the clock pins while the | |
50 | * other SAIF, in slave mode, receives clocking from the master SAIF. | |
51 | * This also means that both SAIFs must operate at the same sample rate. | |
52 | * | |
53 | * We abstract this as each saif has a master, the master could be | |
54 | * himself or other saifs. In the generic saif driver, saif does not need | |
55 | * to know the different clkmux. Saif only needs to know who is his master | |
56 | * and operating his master to generate the proper clock rate for him. | |
57 | * The master id is provided in mach-specific layer according to different | |
58 | * clkmux setting. | |
59 | */ | |
60 | ||
2a24f2ce DA |
61 | static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
62 | int clk_id, unsigned int freq, int dir) | |
63 | { | |
64 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
65 | ||
66 | switch (clk_id) { | |
67 | case MXS_SAIF_MCLK: | |
68 | saif->mclk = freq; | |
69 | break; | |
70 | default: | |
71 | return -EINVAL; | |
72 | } | |
73 | return 0; | |
74 | } | |
75 | ||
76067540 DA |
76 | /* |
77 | * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK | |
78 | * is provided by other SAIF, we provide a interface here to get its master | |
79 | * from its master_id. | |
80 | * Note that the master could be himself. | |
81 | */ | |
82 | static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) | |
83 | { | |
84 | return mxs_saif[saif->master_id]; | |
85 | } | |
86 | ||
2a24f2ce DA |
87 | /* |
88 | * Set SAIF clock and MCLK | |
89 | */ | |
90 | static int mxs_saif_set_clk(struct mxs_saif *saif, | |
91 | unsigned int mclk, | |
92 | unsigned int rate) | |
93 | { | |
94 | u32 scr; | |
95 | int ret; | |
76067540 | 96 | struct mxs_saif *master_saif; |
2a24f2ce | 97 | |
76067540 DA |
98 | dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); |
99 | ||
100 | /* Set master saif to generate proper clock */ | |
101 | master_saif = mxs_saif_get_master(saif); | |
102 | if (!master_saif) | |
103 | return -EINVAL; | |
104 | ||
105 | dev_dbg(saif->dev, "master saif%d\n", master_saif->id); | |
106 | ||
107 | /* Checking if can playback and capture simutaneously */ | |
108 | if (master_saif->ongoing && rate != master_saif->cur_rate) { | |
109 | dev_err(saif->dev, | |
110 | "can not change clock, master saif%d(rate %d) is ongoing\n", | |
111 | master_saif->id, master_saif->cur_rate); | |
112 | return -EINVAL; | |
113 | } | |
114 | ||
115 | scr = __raw_readl(master_saif->base + SAIF_CTRL); | |
2a24f2ce DA |
116 | scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; |
117 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; | |
118 | ||
119 | /* | |
120 | * Set SAIF clock | |
121 | * | |
122 | * The SAIF clock should be either 384*fs or 512*fs. | |
123 | * If MCLK is used, the SAIF clk ratio need to match mclk ratio. | |
124 | * For 32x mclk, set saif clk as 512*fs. | |
125 | * For 48x mclk, set saif clk as 384*fs. | |
126 | * | |
127 | * If MCLK is not used, we just set saif clk to 512*fs. | |
128 | */ | |
6b35f924 FE |
129 | clk_prepare_enable(master_saif->clk); |
130 | ||
76067540 | 131 | if (master_saif->mclk_in_use) { |
2a24f2ce DA |
132 | if (mclk % 32 == 0) { |
133 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; | |
76067540 | 134 | ret = clk_set_rate(master_saif->clk, 512 * rate); |
2a24f2ce DA |
135 | } else if (mclk % 48 == 0) { |
136 | scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; | |
76067540 | 137 | ret = clk_set_rate(master_saif->clk, 384 * rate); |
2a24f2ce DA |
138 | } else { |
139 | /* SAIF MCLK should be either 32x or 48x */ | |
6b35f924 | 140 | clk_disable_unprepare(master_saif->clk); |
2a24f2ce DA |
141 | return -EINVAL; |
142 | } | |
143 | } else { | |
76067540 | 144 | ret = clk_set_rate(master_saif->clk, 512 * rate); |
2a24f2ce DA |
145 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; |
146 | } | |
147 | ||
6b35f924 FE |
148 | clk_disable_unprepare(master_saif->clk); |
149 | ||
2a24f2ce DA |
150 | if (ret) |
151 | return ret; | |
152 | ||
76067540 DA |
153 | master_saif->cur_rate = rate; |
154 | ||
155 | if (!master_saif->mclk_in_use) { | |
156 | __raw_writel(scr, master_saif->base + SAIF_CTRL); | |
2a24f2ce DA |
157 | return 0; |
158 | } | |
159 | ||
160 | /* | |
161 | * Program the over-sample rate for MCLK output | |
162 | * | |
163 | * The available MCLK range is 32x, 48x... 512x. The rate | |
164 | * could be from 8kHz to 192kH. | |
165 | */ | |
166 | switch (mclk / rate) { | |
167 | case 32: | |
168 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); | |
169 | break; | |
170 | case 64: | |
171 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); | |
172 | break; | |
173 | case 128: | |
174 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); | |
175 | break; | |
176 | case 256: | |
177 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); | |
178 | break; | |
179 | case 512: | |
180 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); | |
181 | break; | |
182 | case 48: | |
183 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); | |
184 | break; | |
185 | case 96: | |
186 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); | |
187 | break; | |
188 | case 192: | |
189 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); | |
190 | break; | |
191 | case 384: | |
192 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); | |
193 | break; | |
194 | default: | |
195 | return -EINVAL; | |
196 | } | |
197 | ||
76067540 | 198 | __raw_writel(scr, master_saif->base + SAIF_CTRL); |
2a24f2ce DA |
199 | |
200 | return 0; | |
201 | } | |
202 | ||
203 | /* | |
204 | * Put and disable MCLK. | |
205 | */ | |
206 | int mxs_saif_put_mclk(unsigned int saif_id) | |
207 | { | |
208 | struct mxs_saif *saif = mxs_saif[saif_id]; | |
209 | u32 stat; | |
210 | ||
211 | if (!saif) | |
212 | return -EINVAL; | |
213 | ||
214 | stat = __raw_readl(saif->base + SAIF_STAT); | |
215 | if (stat & BM_SAIF_STAT_BUSY) { | |
216 | dev_err(saif->dev, "error: busy\n"); | |
217 | return -EBUSY; | |
218 | } | |
219 | ||
67939b22 | 220 | clk_disable_unprepare(saif->clk); |
2a24f2ce DA |
221 | |
222 | /* disable MCLK output */ | |
223 | __raw_writel(BM_SAIF_CTRL_CLKGATE, | |
224 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
225 | __raw_writel(BM_SAIF_CTRL_RUN, | |
226 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
227 | ||
228 | saif->mclk_in_use = 0; | |
229 | return 0; | |
230 | } | |
cf7d0f09 | 231 | EXPORT_SYMBOL_GPL(mxs_saif_put_mclk); |
2a24f2ce DA |
232 | |
233 | /* | |
234 | * Get MCLK and set clock rate, then enable it | |
235 | * | |
236 | * This interface is used for codecs who are using MCLK provided | |
237 | * by saif. | |
238 | */ | |
239 | int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, | |
240 | unsigned int rate) | |
241 | { | |
242 | struct mxs_saif *saif = mxs_saif[saif_id]; | |
243 | u32 stat; | |
244 | int ret; | |
76067540 | 245 | struct mxs_saif *master_saif; |
2a24f2ce DA |
246 | |
247 | if (!saif) | |
248 | return -EINVAL; | |
249 | ||
bbe8ff5e DA |
250 | /* Clear Reset */ |
251 | __raw_writel(BM_SAIF_CTRL_SFTRST, | |
252 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
253 | ||
254 | /* FIXME: need clear clk gate for register r/w */ | |
255 | __raw_writel(BM_SAIF_CTRL_CLKGATE, | |
256 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
257 | ||
76067540 DA |
258 | master_saif = mxs_saif_get_master(saif); |
259 | if (saif != master_saif) { | |
260 | dev_err(saif->dev, "can not get mclk from a non-master saif\n"); | |
261 | return -EINVAL; | |
262 | } | |
263 | ||
2a24f2ce DA |
264 | stat = __raw_readl(saif->base + SAIF_STAT); |
265 | if (stat & BM_SAIF_STAT_BUSY) { | |
266 | dev_err(saif->dev, "error: busy\n"); | |
267 | return -EBUSY; | |
268 | } | |
269 | ||
2a24f2ce DA |
270 | saif->mclk_in_use = 1; |
271 | ret = mxs_saif_set_clk(saif, mclk, rate); | |
272 | if (ret) | |
273 | return ret; | |
274 | ||
67939b22 | 275 | ret = clk_prepare_enable(saif->clk); |
2a24f2ce DA |
276 | if (ret) |
277 | return ret; | |
278 | ||
279 | /* enable MCLK output */ | |
2a24f2ce DA |
280 | __raw_writel(BM_SAIF_CTRL_RUN, |
281 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
282 | ||
283 | return 0; | |
284 | } | |
cf7d0f09 | 285 | EXPORT_SYMBOL_GPL(mxs_saif_get_mclk); |
2a24f2ce DA |
286 | |
287 | /* | |
288 | * SAIF DAI format configuration. | |
289 | * Should only be called when port is inactive. | |
290 | */ | |
291 | static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
292 | { | |
293 | u32 scr, stat; | |
294 | u32 scr0; | |
295 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
296 | ||
297 | stat = __raw_readl(saif->base + SAIF_STAT); | |
298 | if (stat & BM_SAIF_STAT_BUSY) { | |
299 | dev_err(cpu_dai->dev, "error: busy\n"); | |
300 | return -EBUSY; | |
301 | } | |
302 | ||
303 | scr0 = __raw_readl(saif->base + SAIF_CTRL); | |
304 | scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ | |
305 | & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; | |
306 | scr = 0; | |
307 | ||
308 | /* DAI mode */ | |
309 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
310 | case SND_SOC_DAIFMT_I2S: | |
311 | /* data frame low 1clk before data */ | |
312 | scr |= BM_SAIF_CTRL_DELAY; | |
313 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
314 | break; | |
315 | case SND_SOC_DAIFMT_LEFT_J: | |
316 | /* data frame high with data */ | |
317 | scr &= ~BM_SAIF_CTRL_DELAY; | |
318 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
319 | scr &= ~BM_SAIF_CTRL_JUSTIFY; | |
320 | break; | |
321 | default: | |
322 | return -EINVAL; | |
323 | } | |
324 | ||
325 | /* DAI clock inversion */ | |
326 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
327 | case SND_SOC_DAIFMT_IB_IF: | |
328 | scr |= BM_SAIF_CTRL_BITCLK_EDGE; | |
329 | scr |= BM_SAIF_CTRL_LRCLK_POLARITY; | |
330 | break; | |
331 | case SND_SOC_DAIFMT_IB_NF: | |
332 | scr |= BM_SAIF_CTRL_BITCLK_EDGE; | |
333 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
334 | break; | |
335 | case SND_SOC_DAIFMT_NB_IF: | |
336 | scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; | |
337 | scr |= BM_SAIF_CTRL_LRCLK_POLARITY; | |
338 | break; | |
339 | case SND_SOC_DAIFMT_NB_NF: | |
340 | scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; | |
341 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
342 | break; | |
343 | } | |
344 | ||
345 | /* | |
346 | * Note: We simply just support master mode since SAIF TX can only | |
347 | * work as master. | |
76067540 DA |
348 | * Here the master is relative to codec side. |
349 | * Saif internally could be slave when working on EXTMASTER mode. | |
350 | * We just hide this to machine driver. | |
2a24f2ce DA |
351 | */ |
352 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
353 | case SND_SOC_DAIFMT_CBS_CFS: | |
76067540 DA |
354 | if (saif->id == saif->master_id) |
355 | scr &= ~BM_SAIF_CTRL_SLAVE_MODE; | |
356 | else | |
357 | scr |= BM_SAIF_CTRL_SLAVE_MODE; | |
358 | ||
2a24f2ce DA |
359 | __raw_writel(scr | scr0, saif->base + SAIF_CTRL); |
360 | break; | |
361 | default: | |
362 | return -EINVAL; | |
363 | } | |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
368 | static int mxs_saif_startup(struct snd_pcm_substream *substream, | |
369 | struct snd_soc_dai *cpu_dai) | |
370 | { | |
371 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
372 | snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param); | |
373 | ||
374 | /* clear error status to 0 for each re-open */ | |
375 | saif->fifo_underrun = 0; | |
376 | saif->fifo_overrun = 0; | |
377 | ||
378 | /* Clear Reset for normal operations */ | |
379 | __raw_writel(BM_SAIF_CTRL_SFTRST, | |
380 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
381 | ||
bbe8ff5e DA |
382 | /* clear clock gate */ |
383 | __raw_writel(BM_SAIF_CTRL_CLKGATE, | |
384 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
385 | ||
2a24f2ce DA |
386 | return 0; |
387 | } | |
388 | ||
389 | /* | |
390 | * Should only be called when port is inactive. | |
391 | * although can be called multiple times by upper layers. | |
392 | */ | |
393 | static int mxs_saif_hw_params(struct snd_pcm_substream *substream, | |
394 | struct snd_pcm_hw_params *params, | |
395 | struct snd_soc_dai *cpu_dai) | |
396 | { | |
397 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
c2e1d907 | 398 | struct mxs_saif *master_saif; |
2a24f2ce DA |
399 | u32 scr, stat; |
400 | int ret; | |
401 | ||
c2e1d907 DA |
402 | master_saif = mxs_saif_get_master(saif); |
403 | if (!master_saif) | |
404 | return -EINVAL; | |
405 | ||
2a24f2ce DA |
406 | /* mclk should already be set */ |
407 | if (!saif->mclk && saif->mclk_in_use) { | |
408 | dev_err(cpu_dai->dev, "set mclk first\n"); | |
409 | return -EINVAL; | |
410 | } | |
411 | ||
412 | stat = __raw_readl(saif->base + SAIF_STAT); | |
413 | if (stat & BM_SAIF_STAT_BUSY) { | |
414 | dev_err(cpu_dai->dev, "error: busy\n"); | |
415 | return -EBUSY; | |
416 | } | |
417 | ||
418 | /* | |
419 | * Set saif clk based on sample rate. | |
420 | * If mclk is used, we also set mclk, if not, saif->mclk is | |
421 | * default 0, means not used. | |
422 | */ | |
423 | ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); | |
424 | if (ret) { | |
425 | dev_err(cpu_dai->dev, "unable to get proper clk\n"); | |
426 | return ret; | |
427 | } | |
428 | ||
c2e1d907 DA |
429 | /* prepare clk in hw_param, enable in trigger */ |
430 | clk_prepare(saif->clk); | |
d0ba4c01 DA |
431 | if (saif != master_saif) { |
432 | /* | |
433 | * Set an initial clock rate for the saif internal logic to work | |
434 | * properly. This is important when working in EXTMASTER mode | |
435 | * that uses the other saif's BITCLK&LRCLK but it still needs a | |
436 | * basic clock which should be fast enough for the internal | |
437 | * logic. | |
438 | */ | |
439 | clk_enable(saif->clk); | |
440 | ret = clk_set_rate(saif->clk, 24000000); | |
441 | clk_disable(saif->clk); | |
442 | if (ret) | |
443 | return ret; | |
444 | ||
c2e1d907 | 445 | clk_prepare(master_saif->clk); |
d0ba4c01 | 446 | } |
c2e1d907 | 447 | |
2a24f2ce DA |
448 | scr = __raw_readl(saif->base + SAIF_CTRL); |
449 | ||
450 | scr &= ~BM_SAIF_CTRL_WORD_LENGTH; | |
451 | scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; | |
452 | switch (params_format(params)) { | |
453 | case SNDRV_PCM_FORMAT_S16_LE: | |
454 | scr |= BF_SAIF_CTRL_WORD_LENGTH(0); | |
455 | break; | |
456 | case SNDRV_PCM_FORMAT_S20_3LE: | |
457 | scr |= BF_SAIF_CTRL_WORD_LENGTH(4); | |
458 | scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; | |
459 | break; | |
460 | case SNDRV_PCM_FORMAT_S24_LE: | |
461 | scr |= BF_SAIF_CTRL_WORD_LENGTH(8); | |
462 | scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; | |
463 | break; | |
464 | default: | |
465 | return -EINVAL; | |
466 | } | |
467 | ||
468 | /* Tx/Rx config */ | |
469 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
470 | /* enable TX mode */ | |
471 | scr &= ~BM_SAIF_CTRL_READ_MODE; | |
472 | } else { | |
473 | /* enable RX mode */ | |
474 | scr |= BM_SAIF_CTRL_READ_MODE; | |
475 | } | |
476 | ||
477 | __raw_writel(scr, saif->base + SAIF_CTRL); | |
478 | return 0; | |
479 | } | |
480 | ||
481 | static int mxs_saif_prepare(struct snd_pcm_substream *substream, | |
482 | struct snd_soc_dai *cpu_dai) | |
483 | { | |
484 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
485 | ||
2a24f2ce DA |
486 | /* enable FIFO error irqs */ |
487 | __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, | |
488 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
493 | static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, | |
494 | struct snd_soc_dai *cpu_dai) | |
495 | { | |
496 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
76067540 DA |
497 | struct mxs_saif *master_saif; |
498 | u32 delay; | |
499 | ||
500 | master_saif = mxs_saif_get_master(saif); | |
501 | if (!master_saif) | |
502 | return -EINVAL; | |
2a24f2ce DA |
503 | |
504 | switch (cmd) { | |
505 | case SNDRV_PCM_TRIGGER_START: | |
506 | case SNDRV_PCM_TRIGGER_RESUME: | |
507 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
508 | dev_dbg(cpu_dai->dev, "start\n"); | |
509 | ||
76067540 DA |
510 | clk_enable(master_saif->clk); |
511 | if (!master_saif->mclk_in_use) | |
512 | __raw_writel(BM_SAIF_CTRL_RUN, | |
513 | master_saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
514 | ||
515 | /* | |
516 | * If the saif's master is not himself, we also need to enable | |
517 | * itself clk for its internal basic logic to work. | |
518 | */ | |
519 | if (saif != master_saif) { | |
520 | clk_enable(saif->clk); | |
2a24f2ce DA |
521 | __raw_writel(BM_SAIF_CTRL_RUN, |
522 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
76067540 | 523 | } |
2a24f2ce DA |
524 | |
525 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
526 | /* | |
f55f1475 FE |
527 | * write data to saif data register to trigger |
528 | * the transfer. | |
529 | * For 24-bit format the 32-bit FIFO register stores | |
530 | * only one channel, so we need to write twice. | |
531 | * This is also safe for the other non 24-bit formats. | |
2a24f2ce DA |
532 | */ |
533 | __raw_writel(0, saif->base + SAIF_DATA); | |
f55f1475 | 534 | __raw_writel(0, saif->base + SAIF_DATA); |
2a24f2ce DA |
535 | } else { |
536 | /* | |
f55f1475 FE |
537 | * read data from saif data register to trigger |
538 | * the receive. | |
539 | * For 24-bit format the 32-bit FIFO register stores | |
540 | * only one channel, so we need to read twice. | |
541 | * This is also safe for the other non 24-bit formats. | |
2a24f2ce DA |
542 | */ |
543 | __raw_readl(saif->base + SAIF_DATA); | |
f55f1475 | 544 | __raw_readl(saif->base + SAIF_DATA); |
2a24f2ce DA |
545 | } |
546 | ||
76067540 DA |
547 | master_saif->ongoing = 1; |
548 | ||
549 | dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", | |
2a24f2ce DA |
550 | __raw_readl(saif->base + SAIF_CTRL), |
551 | __raw_readl(saif->base + SAIF_STAT)); | |
552 | ||
76067540 DA |
553 | dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", |
554 | __raw_readl(master_saif->base + SAIF_CTRL), | |
555 | __raw_readl(master_saif->base + SAIF_STAT)); | |
2a24f2ce DA |
556 | break; |
557 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
558 | case SNDRV_PCM_TRIGGER_STOP: | |
559 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
560 | dev_dbg(cpu_dai->dev, "stop\n"); | |
561 | ||
76067540 DA |
562 | /* wait a while for the current sample to complete */ |
563 | delay = USEC_PER_SEC / master_saif->cur_rate; | |
564 | ||
565 | if (!master_saif->mclk_in_use) { | |
566 | __raw_writel(BM_SAIF_CTRL_RUN, | |
567 | master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
568 | udelay(delay); | |
569 | } | |
570 | clk_disable(master_saif->clk); | |
571 | ||
572 | if (saif != master_saif) { | |
2a24f2ce DA |
573 | __raw_writel(BM_SAIF_CTRL_RUN, |
574 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
76067540 DA |
575 | udelay(delay); |
576 | clk_disable(saif->clk); | |
577 | } | |
578 | ||
579 | master_saif->ongoing = 0; | |
2a24f2ce DA |
580 | |
581 | break; | |
582 | default: | |
583 | return -EINVAL; | |
584 | } | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
589 | #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 | |
590 | #define MXS_SAIF_FORMATS \ | |
591 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
592 | SNDRV_PCM_FMTBIT_S24_LE) | |
593 | ||
85e7652d | 594 | static const struct snd_soc_dai_ops mxs_saif_dai_ops = { |
2a24f2ce DA |
595 | .startup = mxs_saif_startup, |
596 | .trigger = mxs_saif_trigger, | |
597 | .prepare = mxs_saif_prepare, | |
598 | .hw_params = mxs_saif_hw_params, | |
599 | .set_sysclk = mxs_saif_set_dai_sysclk, | |
600 | .set_fmt = mxs_saif_set_dai_fmt, | |
601 | }; | |
602 | ||
603 | static int mxs_saif_dai_probe(struct snd_soc_dai *dai) | |
604 | { | |
605 | struct mxs_saif *saif = dev_get_drvdata(dai->dev); | |
606 | ||
607 | snd_soc_dai_set_drvdata(dai, saif); | |
608 | ||
609 | return 0; | |
610 | } | |
611 | ||
612 | static struct snd_soc_dai_driver mxs_saif_dai = { | |
613 | .name = "mxs-saif", | |
614 | .probe = mxs_saif_dai_probe, | |
615 | .playback = { | |
616 | .channels_min = 2, | |
617 | .channels_max = 2, | |
618 | .rates = MXS_SAIF_RATES, | |
619 | .formats = MXS_SAIF_FORMATS, | |
620 | }, | |
621 | .capture = { | |
622 | .channels_min = 2, | |
623 | .channels_max = 2, | |
624 | .rates = MXS_SAIF_RATES, | |
625 | .formats = MXS_SAIF_FORMATS, | |
626 | }, | |
627 | .ops = &mxs_saif_dai_ops, | |
628 | }; | |
629 | ||
630 | static irqreturn_t mxs_saif_irq(int irq, void *dev_id) | |
631 | { | |
632 | struct mxs_saif *saif = dev_id; | |
633 | unsigned int stat; | |
634 | ||
635 | stat = __raw_readl(saif->base + SAIF_STAT); | |
636 | if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | | |
637 | BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) | |
638 | return IRQ_NONE; | |
639 | ||
640 | if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { | |
641 | dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); | |
642 | __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, | |
643 | saif->base + SAIF_STAT + MXS_CLR_ADDR); | |
644 | } | |
645 | ||
646 | if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { | |
647 | dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); | |
648 | __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, | |
649 | saif->base + SAIF_STAT + MXS_CLR_ADDR); | |
650 | } | |
651 | ||
652 | dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", | |
653 | __raw_readl(saif->base + SAIF_CTRL), | |
654 | __raw_readl(saif->base + SAIF_STAT)); | |
655 | ||
656 | return IRQ_HANDLED; | |
657 | } | |
658 | ||
fd582736 | 659 | static int mxs_saif_probe(struct platform_device *pdev) |
2a24f2ce | 660 | { |
08641c7c | 661 | struct device_node *np = pdev->dev.of_node; |
226d0f22 | 662 | struct resource *iores, *dmares; |
2a24f2ce | 663 | struct mxs_saif *saif; |
f755865f | 664 | struct pinctrl *pinctrl; |
2a24f2ce | 665 | int ret = 0; |
4498a3ca | 666 | struct device_node *master; |
2a24f2ce | 667 | |
4498a3ca | 668 | if (!np) |
0bb98ba2 JL |
669 | return -EINVAL; |
670 | ||
830eb876 | 671 | saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); |
2a24f2ce DA |
672 | if (!saif) |
673 | return -ENOMEM; | |
674 | ||
324a7fb0 FE |
675 | ret = of_alias_get_id(np, "saif"); |
676 | if (ret < 0) | |
677 | return ret; | |
678 | else | |
679 | saif->id = ret; | |
680 | ||
4498a3ca FE |
681 | /* |
682 | * If there is no "fsl,saif-master" phandle, it's a saif | |
683 | * master. Otherwise, it's a slave and its phandle points | |
684 | * to the master. | |
685 | */ | |
686 | master = of_parse_phandle(np, "fsl,saif-master", 0); | |
687 | if (!master) { | |
688 | saif->master_id = saif->id; | |
77882580 | 689 | } else { |
324a7fb0 FE |
690 | ret = of_alias_get_id(master, "saif"); |
691 | if (ret < 0) | |
692 | return ret; | |
693 | else | |
694 | saif->master_id = ret; | |
08641c7c SG |
695 | } |
696 | ||
324a7fb0 | 697 | if (saif->master_id >= ARRAY_SIZE(mxs_saif)) { |
08641c7c SG |
698 | dev_err(&pdev->dev, "get wrong master id\n"); |
699 | return -EINVAL; | |
76067540 | 700 | } |
2a24f2ce | 701 | |
08641c7c SG |
702 | mxs_saif[saif->id] = saif; |
703 | ||
f755865f SG |
704 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
705 | if (IS_ERR(pinctrl)) { | |
706 | ret = PTR_ERR(pinctrl); | |
707 | return ret; | |
708 | } | |
709 | ||
730963f8 | 710 | saif->clk = devm_clk_get(&pdev->dev, NULL); |
2a24f2ce DA |
711 | if (IS_ERR(saif->clk)) { |
712 | ret = PTR_ERR(saif->clk); | |
713 | dev_err(&pdev->dev, "Cannot get the clock: %d\n", | |
714 | ret); | |
830eb876 | 715 | return ret; |
2a24f2ce DA |
716 | } |
717 | ||
226d0f22 | 718 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2a24f2ce | 719 | |
b25b5aa0 TR |
720 | saif->base = devm_ioremap_resource(&pdev->dev, iores); |
721 | if (IS_ERR(saif->base)) | |
722 | return PTR_ERR(saif->base); | |
2a24f2ce | 723 | |
226d0f22 JL |
724 | dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
725 | if (!dmares) { | |
08641c7c SG |
726 | /* |
727 | * TODO: This is a temporary solution and should be changed | |
728 | * to use generic DMA binding later when the helplers get in. | |
729 | */ | |
730 | ret = of_property_read_u32(np, "fsl,saif-dma-channel", | |
731 | &saif->dma_param.chan_num); | |
732 | if (ret) { | |
733 | dev_err(&pdev->dev, "failed to get dma channel\n"); | |
730963f8 | 734 | return ret; |
08641c7c SG |
735 | } |
736 | } else { | |
737 | saif->dma_param.chan_num = dmares->start; | |
2a24f2ce | 738 | } |
2a24f2ce DA |
739 | |
740 | saif->irq = platform_get_irq(pdev, 0); | |
741 | if (saif->irq < 0) { | |
742 | ret = saif->irq; | |
743 | dev_err(&pdev->dev, "failed to get irq resource: %d\n", | |
744 | ret); | |
730963f8 | 745 | return ret; |
2a24f2ce DA |
746 | } |
747 | ||
748 | saif->dev = &pdev->dev; | |
830eb876 JL |
749 | ret = devm_request_irq(&pdev->dev, saif->irq, mxs_saif_irq, 0, |
750 | "mxs-saif", saif); | |
2a24f2ce DA |
751 | if (ret) { |
752 | dev_err(&pdev->dev, "failed to request irq\n"); | |
730963f8 | 753 | return ret; |
2a24f2ce DA |
754 | } |
755 | ||
756 | saif->dma_param.chan_irq = platform_get_irq(pdev, 1); | |
757 | if (saif->dma_param.chan_irq < 0) { | |
758 | ret = saif->dma_param.chan_irq; | |
759 | dev_err(&pdev->dev, "failed to get dma irq resource: %d\n", | |
760 | ret); | |
730963f8 | 761 | return ret; |
2a24f2ce DA |
762 | } |
763 | ||
764 | platform_set_drvdata(pdev, saif); | |
765 | ||
766 | ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai); | |
767 | if (ret) { | |
768 | dev_err(&pdev->dev, "register DAI failed\n"); | |
730963f8 | 769 | return ret; |
2a24f2ce DA |
770 | } |
771 | ||
4da3fe78 | 772 | ret = mxs_pcm_platform_register(&pdev->dev); |
2a24f2ce | 773 | if (ret) { |
4da3fe78 SG |
774 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); |
775 | goto failed_pdev_alloc; | |
2a24f2ce DA |
776 | } |
777 | ||
778 | return 0; | |
779 | ||
2a24f2ce DA |
780 | failed_pdev_alloc: |
781 | snd_soc_unregister_dai(&pdev->dev); | |
2a24f2ce DA |
782 | |
783 | return ret; | |
784 | } | |
785 | ||
fd582736 | 786 | static int mxs_saif_remove(struct platform_device *pdev) |
2a24f2ce | 787 | { |
4da3fe78 | 788 | mxs_pcm_platform_unregister(&pdev->dev); |
2a24f2ce | 789 | snd_soc_unregister_dai(&pdev->dev); |
2a24f2ce DA |
790 | |
791 | return 0; | |
792 | } | |
793 | ||
08641c7c SG |
794 | static const struct of_device_id mxs_saif_dt_ids[] = { |
795 | { .compatible = "fsl,imx28-saif", }, | |
796 | { /* sentinel */ } | |
797 | }; | |
798 | MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); | |
799 | ||
2a24f2ce DA |
800 | static struct platform_driver mxs_saif_driver = { |
801 | .probe = mxs_saif_probe, | |
fd582736 | 802 | .remove = mxs_saif_remove, |
2a24f2ce DA |
803 | |
804 | .driver = { | |
805 | .name = "mxs-saif", | |
806 | .owner = THIS_MODULE, | |
08641c7c | 807 | .of_match_table = mxs_saif_dt_ids, |
2a24f2ce DA |
808 | }, |
809 | }; | |
810 | ||
85aa0960 | 811 | module_platform_driver(mxs_saif_driver); |
2a24f2ce | 812 | |
2a24f2ce DA |
813 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); |
814 | MODULE_DESCRIPTION("MXS ASoC SAIF driver"); | |
815 | MODULE_LICENSE("GPL"); | |
9f4c3f1c | 816 | MODULE_ALIAS("platform:mxs-saif"); |