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2a24f2ce DA |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/init.h> | |
08641c7c SG |
21 | #include <linux/of.h> |
22 | #include <linux/of_device.h> | |
2a24f2ce DA |
23 | #include <linux/platform_device.h> |
24 | #include <linux/slab.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/delay.h> | |
76067540 | 28 | #include <linux/time.h> |
39468604 | 29 | #include <linux/fsl/mxs-dma.h> |
f755865f | 30 | #include <linux/pinctrl/consumer.h> |
2a24f2ce DA |
31 | #include <sound/core.h> |
32 | #include <sound/pcm.h> | |
33 | #include <sound/pcm_params.h> | |
34 | #include <sound/soc.h> | |
76067540 | 35 | #include <sound/saif.h> |
2a24f2ce DA |
36 | #include <asm/mach-types.h> |
37 | #include <mach/hardware.h> | |
38 | #include <mach/mxs.h> | |
39 | ||
40 | #include "mxs-saif.h" | |
41 | ||
42 | static struct mxs_saif *mxs_saif[2]; | |
43 | ||
76067540 DA |
44 | /* |
45 | * SAIF is a little different with other normal SOC DAIs on clock using. | |
46 | * | |
47 | * For MXS, two SAIF modules are instantiated on-chip. | |
48 | * Each SAIF has a set of clock pins and can be operating in master | |
49 | * mode simultaneously if they are connected to different off-chip codecs. | |
50 | * Also, one of the two SAIFs can master or drive the clock pins while the | |
51 | * other SAIF, in slave mode, receives clocking from the master SAIF. | |
52 | * This also means that both SAIFs must operate at the same sample rate. | |
53 | * | |
54 | * We abstract this as each saif has a master, the master could be | |
55 | * himself or other saifs. In the generic saif driver, saif does not need | |
56 | * to know the different clkmux. Saif only needs to know who is his master | |
57 | * and operating his master to generate the proper clock rate for him. | |
58 | * The master id is provided in mach-specific layer according to different | |
59 | * clkmux setting. | |
60 | */ | |
61 | ||
2a24f2ce DA |
62 | static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
63 | int clk_id, unsigned int freq, int dir) | |
64 | { | |
65 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
66 | ||
67 | switch (clk_id) { | |
68 | case MXS_SAIF_MCLK: | |
69 | saif->mclk = freq; | |
70 | break; | |
71 | default: | |
72 | return -EINVAL; | |
73 | } | |
74 | return 0; | |
75 | } | |
76 | ||
76067540 DA |
77 | /* |
78 | * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK | |
79 | * is provided by other SAIF, we provide a interface here to get its master | |
80 | * from its master_id. | |
81 | * Note that the master could be himself. | |
82 | */ | |
83 | static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) | |
84 | { | |
85 | return mxs_saif[saif->master_id]; | |
86 | } | |
87 | ||
2a24f2ce DA |
88 | /* |
89 | * Set SAIF clock and MCLK | |
90 | */ | |
91 | static int mxs_saif_set_clk(struct mxs_saif *saif, | |
92 | unsigned int mclk, | |
93 | unsigned int rate) | |
94 | { | |
95 | u32 scr; | |
96 | int ret; | |
76067540 | 97 | struct mxs_saif *master_saif; |
2a24f2ce | 98 | |
76067540 DA |
99 | dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); |
100 | ||
101 | /* Set master saif to generate proper clock */ | |
102 | master_saif = mxs_saif_get_master(saif); | |
103 | if (!master_saif) | |
104 | return -EINVAL; | |
105 | ||
106 | dev_dbg(saif->dev, "master saif%d\n", master_saif->id); | |
107 | ||
108 | /* Checking if can playback and capture simutaneously */ | |
109 | if (master_saif->ongoing && rate != master_saif->cur_rate) { | |
110 | dev_err(saif->dev, | |
111 | "can not change clock, master saif%d(rate %d) is ongoing\n", | |
112 | master_saif->id, master_saif->cur_rate); | |
113 | return -EINVAL; | |
114 | } | |
115 | ||
116 | scr = __raw_readl(master_saif->base + SAIF_CTRL); | |
2a24f2ce DA |
117 | scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; |
118 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; | |
119 | ||
120 | /* | |
121 | * Set SAIF clock | |
122 | * | |
123 | * The SAIF clock should be either 384*fs or 512*fs. | |
124 | * If MCLK is used, the SAIF clk ratio need to match mclk ratio. | |
125 | * For 32x mclk, set saif clk as 512*fs. | |
126 | * For 48x mclk, set saif clk as 384*fs. | |
127 | * | |
128 | * If MCLK is not used, we just set saif clk to 512*fs. | |
129 | */ | |
6b35f924 FE |
130 | clk_prepare_enable(master_saif->clk); |
131 | ||
76067540 | 132 | if (master_saif->mclk_in_use) { |
2a24f2ce DA |
133 | if (mclk % 32 == 0) { |
134 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; | |
76067540 | 135 | ret = clk_set_rate(master_saif->clk, 512 * rate); |
2a24f2ce DA |
136 | } else if (mclk % 48 == 0) { |
137 | scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; | |
76067540 | 138 | ret = clk_set_rate(master_saif->clk, 384 * rate); |
2a24f2ce DA |
139 | } else { |
140 | /* SAIF MCLK should be either 32x or 48x */ | |
6b35f924 | 141 | clk_disable_unprepare(master_saif->clk); |
2a24f2ce DA |
142 | return -EINVAL; |
143 | } | |
144 | } else { | |
76067540 | 145 | ret = clk_set_rate(master_saif->clk, 512 * rate); |
2a24f2ce DA |
146 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; |
147 | } | |
148 | ||
6b35f924 FE |
149 | clk_disable_unprepare(master_saif->clk); |
150 | ||
2a24f2ce DA |
151 | if (ret) |
152 | return ret; | |
153 | ||
76067540 DA |
154 | master_saif->cur_rate = rate; |
155 | ||
156 | if (!master_saif->mclk_in_use) { | |
157 | __raw_writel(scr, master_saif->base + SAIF_CTRL); | |
2a24f2ce DA |
158 | return 0; |
159 | } | |
160 | ||
161 | /* | |
162 | * Program the over-sample rate for MCLK output | |
163 | * | |
164 | * The available MCLK range is 32x, 48x... 512x. The rate | |
165 | * could be from 8kHz to 192kH. | |
166 | */ | |
167 | switch (mclk / rate) { | |
168 | case 32: | |
169 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); | |
170 | break; | |
171 | case 64: | |
172 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); | |
173 | break; | |
174 | case 128: | |
175 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); | |
176 | break; | |
177 | case 256: | |
178 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); | |
179 | break; | |
180 | case 512: | |
181 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); | |
182 | break; | |
183 | case 48: | |
184 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); | |
185 | break; | |
186 | case 96: | |
187 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); | |
188 | break; | |
189 | case 192: | |
190 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); | |
191 | break; | |
192 | case 384: | |
193 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); | |
194 | break; | |
195 | default: | |
196 | return -EINVAL; | |
197 | } | |
198 | ||
76067540 | 199 | __raw_writel(scr, master_saif->base + SAIF_CTRL); |
2a24f2ce DA |
200 | |
201 | return 0; | |
202 | } | |
203 | ||
204 | /* | |
205 | * Put and disable MCLK. | |
206 | */ | |
207 | int mxs_saif_put_mclk(unsigned int saif_id) | |
208 | { | |
209 | struct mxs_saif *saif = mxs_saif[saif_id]; | |
210 | u32 stat; | |
211 | ||
212 | if (!saif) | |
213 | return -EINVAL; | |
214 | ||
215 | stat = __raw_readl(saif->base + SAIF_STAT); | |
216 | if (stat & BM_SAIF_STAT_BUSY) { | |
217 | dev_err(saif->dev, "error: busy\n"); | |
218 | return -EBUSY; | |
219 | } | |
220 | ||
67939b22 | 221 | clk_disable_unprepare(saif->clk); |
2a24f2ce DA |
222 | |
223 | /* disable MCLK output */ | |
224 | __raw_writel(BM_SAIF_CTRL_CLKGATE, | |
225 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
226 | __raw_writel(BM_SAIF_CTRL_RUN, | |
227 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
228 | ||
229 | saif->mclk_in_use = 0; | |
230 | return 0; | |
231 | } | |
cf7d0f09 | 232 | EXPORT_SYMBOL_GPL(mxs_saif_put_mclk); |
2a24f2ce DA |
233 | |
234 | /* | |
235 | * Get MCLK and set clock rate, then enable it | |
236 | * | |
237 | * This interface is used for codecs who are using MCLK provided | |
238 | * by saif. | |
239 | */ | |
240 | int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, | |
241 | unsigned int rate) | |
242 | { | |
243 | struct mxs_saif *saif = mxs_saif[saif_id]; | |
244 | u32 stat; | |
245 | int ret; | |
76067540 | 246 | struct mxs_saif *master_saif; |
2a24f2ce DA |
247 | |
248 | if (!saif) | |
249 | return -EINVAL; | |
250 | ||
bbe8ff5e DA |
251 | /* Clear Reset */ |
252 | __raw_writel(BM_SAIF_CTRL_SFTRST, | |
253 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
254 | ||
255 | /* FIXME: need clear clk gate for register r/w */ | |
256 | __raw_writel(BM_SAIF_CTRL_CLKGATE, | |
257 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
258 | ||
76067540 DA |
259 | master_saif = mxs_saif_get_master(saif); |
260 | if (saif != master_saif) { | |
261 | dev_err(saif->dev, "can not get mclk from a non-master saif\n"); | |
262 | return -EINVAL; | |
263 | } | |
264 | ||
2a24f2ce DA |
265 | stat = __raw_readl(saif->base + SAIF_STAT); |
266 | if (stat & BM_SAIF_STAT_BUSY) { | |
267 | dev_err(saif->dev, "error: busy\n"); | |
268 | return -EBUSY; | |
269 | } | |
270 | ||
2a24f2ce DA |
271 | saif->mclk_in_use = 1; |
272 | ret = mxs_saif_set_clk(saif, mclk, rate); | |
273 | if (ret) | |
274 | return ret; | |
275 | ||
67939b22 | 276 | ret = clk_prepare_enable(saif->clk); |
2a24f2ce DA |
277 | if (ret) |
278 | return ret; | |
279 | ||
280 | /* enable MCLK output */ | |
2a24f2ce DA |
281 | __raw_writel(BM_SAIF_CTRL_RUN, |
282 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
283 | ||
284 | return 0; | |
285 | } | |
cf7d0f09 | 286 | EXPORT_SYMBOL_GPL(mxs_saif_get_mclk); |
2a24f2ce DA |
287 | |
288 | /* | |
289 | * SAIF DAI format configuration. | |
290 | * Should only be called when port is inactive. | |
291 | */ | |
292 | static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
293 | { | |
294 | u32 scr, stat; | |
295 | u32 scr0; | |
296 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
297 | ||
298 | stat = __raw_readl(saif->base + SAIF_STAT); | |
299 | if (stat & BM_SAIF_STAT_BUSY) { | |
300 | dev_err(cpu_dai->dev, "error: busy\n"); | |
301 | return -EBUSY; | |
302 | } | |
303 | ||
304 | scr0 = __raw_readl(saif->base + SAIF_CTRL); | |
305 | scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ | |
306 | & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; | |
307 | scr = 0; | |
308 | ||
309 | /* DAI mode */ | |
310 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
311 | case SND_SOC_DAIFMT_I2S: | |
312 | /* data frame low 1clk before data */ | |
313 | scr |= BM_SAIF_CTRL_DELAY; | |
314 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
315 | break; | |
316 | case SND_SOC_DAIFMT_LEFT_J: | |
317 | /* data frame high with data */ | |
318 | scr &= ~BM_SAIF_CTRL_DELAY; | |
319 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
320 | scr &= ~BM_SAIF_CTRL_JUSTIFY; | |
321 | break; | |
322 | default: | |
323 | return -EINVAL; | |
324 | } | |
325 | ||
326 | /* DAI clock inversion */ | |
327 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
328 | case SND_SOC_DAIFMT_IB_IF: | |
329 | scr |= BM_SAIF_CTRL_BITCLK_EDGE; | |
330 | scr |= BM_SAIF_CTRL_LRCLK_POLARITY; | |
331 | break; | |
332 | case SND_SOC_DAIFMT_IB_NF: | |
333 | scr |= BM_SAIF_CTRL_BITCLK_EDGE; | |
334 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
335 | break; | |
336 | case SND_SOC_DAIFMT_NB_IF: | |
337 | scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; | |
338 | scr |= BM_SAIF_CTRL_LRCLK_POLARITY; | |
339 | break; | |
340 | case SND_SOC_DAIFMT_NB_NF: | |
341 | scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; | |
342 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
343 | break; | |
344 | } | |
345 | ||
346 | /* | |
347 | * Note: We simply just support master mode since SAIF TX can only | |
348 | * work as master. | |
76067540 DA |
349 | * Here the master is relative to codec side. |
350 | * Saif internally could be slave when working on EXTMASTER mode. | |
351 | * We just hide this to machine driver. | |
2a24f2ce DA |
352 | */ |
353 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
354 | case SND_SOC_DAIFMT_CBS_CFS: | |
76067540 DA |
355 | if (saif->id == saif->master_id) |
356 | scr &= ~BM_SAIF_CTRL_SLAVE_MODE; | |
357 | else | |
358 | scr |= BM_SAIF_CTRL_SLAVE_MODE; | |
359 | ||
2a24f2ce DA |
360 | __raw_writel(scr | scr0, saif->base + SAIF_CTRL); |
361 | break; | |
362 | default: | |
363 | return -EINVAL; | |
364 | } | |
365 | ||
366 | return 0; | |
367 | } | |
368 | ||
369 | static int mxs_saif_startup(struct snd_pcm_substream *substream, | |
370 | struct snd_soc_dai *cpu_dai) | |
371 | { | |
372 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
373 | snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param); | |
374 | ||
375 | /* clear error status to 0 for each re-open */ | |
376 | saif->fifo_underrun = 0; | |
377 | saif->fifo_overrun = 0; | |
378 | ||
379 | /* Clear Reset for normal operations */ | |
380 | __raw_writel(BM_SAIF_CTRL_SFTRST, | |
381 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
382 | ||
bbe8ff5e DA |
383 | /* clear clock gate */ |
384 | __raw_writel(BM_SAIF_CTRL_CLKGATE, | |
385 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
386 | ||
2a24f2ce DA |
387 | return 0; |
388 | } | |
389 | ||
390 | /* | |
391 | * Should only be called when port is inactive. | |
392 | * although can be called multiple times by upper layers. | |
393 | */ | |
394 | static int mxs_saif_hw_params(struct snd_pcm_substream *substream, | |
395 | struct snd_pcm_hw_params *params, | |
396 | struct snd_soc_dai *cpu_dai) | |
397 | { | |
398 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
c2e1d907 | 399 | struct mxs_saif *master_saif; |
2a24f2ce DA |
400 | u32 scr, stat; |
401 | int ret; | |
402 | ||
c2e1d907 DA |
403 | master_saif = mxs_saif_get_master(saif); |
404 | if (!master_saif) | |
405 | return -EINVAL; | |
406 | ||
2a24f2ce DA |
407 | /* mclk should already be set */ |
408 | if (!saif->mclk && saif->mclk_in_use) { | |
409 | dev_err(cpu_dai->dev, "set mclk first\n"); | |
410 | return -EINVAL; | |
411 | } | |
412 | ||
413 | stat = __raw_readl(saif->base + SAIF_STAT); | |
414 | if (stat & BM_SAIF_STAT_BUSY) { | |
415 | dev_err(cpu_dai->dev, "error: busy\n"); | |
416 | return -EBUSY; | |
417 | } | |
418 | ||
419 | /* | |
420 | * Set saif clk based on sample rate. | |
421 | * If mclk is used, we also set mclk, if not, saif->mclk is | |
422 | * default 0, means not used. | |
423 | */ | |
424 | ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); | |
425 | if (ret) { | |
426 | dev_err(cpu_dai->dev, "unable to get proper clk\n"); | |
427 | return ret; | |
428 | } | |
429 | ||
c2e1d907 DA |
430 | /* prepare clk in hw_param, enable in trigger */ |
431 | clk_prepare(saif->clk); | |
d0ba4c01 DA |
432 | if (saif != master_saif) { |
433 | /* | |
434 | * Set an initial clock rate for the saif internal logic to work | |
435 | * properly. This is important when working in EXTMASTER mode | |
436 | * that uses the other saif's BITCLK&LRCLK but it still needs a | |
437 | * basic clock which should be fast enough for the internal | |
438 | * logic. | |
439 | */ | |
440 | clk_enable(saif->clk); | |
441 | ret = clk_set_rate(saif->clk, 24000000); | |
442 | clk_disable(saif->clk); | |
443 | if (ret) | |
444 | return ret; | |
445 | ||
c2e1d907 | 446 | clk_prepare(master_saif->clk); |
d0ba4c01 | 447 | } |
c2e1d907 | 448 | |
2a24f2ce DA |
449 | scr = __raw_readl(saif->base + SAIF_CTRL); |
450 | ||
451 | scr &= ~BM_SAIF_CTRL_WORD_LENGTH; | |
452 | scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; | |
453 | switch (params_format(params)) { | |
454 | case SNDRV_PCM_FORMAT_S16_LE: | |
455 | scr |= BF_SAIF_CTRL_WORD_LENGTH(0); | |
456 | break; | |
457 | case SNDRV_PCM_FORMAT_S20_3LE: | |
458 | scr |= BF_SAIF_CTRL_WORD_LENGTH(4); | |
459 | scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; | |
460 | break; | |
461 | case SNDRV_PCM_FORMAT_S24_LE: | |
462 | scr |= BF_SAIF_CTRL_WORD_LENGTH(8); | |
463 | scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; | |
464 | break; | |
465 | default: | |
466 | return -EINVAL; | |
467 | } | |
468 | ||
469 | /* Tx/Rx config */ | |
470 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
471 | /* enable TX mode */ | |
472 | scr &= ~BM_SAIF_CTRL_READ_MODE; | |
473 | } else { | |
474 | /* enable RX mode */ | |
475 | scr |= BM_SAIF_CTRL_READ_MODE; | |
476 | } | |
477 | ||
478 | __raw_writel(scr, saif->base + SAIF_CTRL); | |
479 | return 0; | |
480 | } | |
481 | ||
482 | static int mxs_saif_prepare(struct snd_pcm_substream *substream, | |
483 | struct snd_soc_dai *cpu_dai) | |
484 | { | |
485 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
486 | ||
2a24f2ce DA |
487 | /* enable FIFO error irqs */ |
488 | __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, | |
489 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
490 | ||
491 | return 0; | |
492 | } | |
493 | ||
494 | static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, | |
495 | struct snd_soc_dai *cpu_dai) | |
496 | { | |
497 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
76067540 DA |
498 | struct mxs_saif *master_saif; |
499 | u32 delay; | |
500 | ||
501 | master_saif = mxs_saif_get_master(saif); | |
502 | if (!master_saif) | |
503 | return -EINVAL; | |
2a24f2ce DA |
504 | |
505 | switch (cmd) { | |
506 | case SNDRV_PCM_TRIGGER_START: | |
507 | case SNDRV_PCM_TRIGGER_RESUME: | |
508 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
509 | dev_dbg(cpu_dai->dev, "start\n"); | |
510 | ||
76067540 DA |
511 | clk_enable(master_saif->clk); |
512 | if (!master_saif->mclk_in_use) | |
513 | __raw_writel(BM_SAIF_CTRL_RUN, | |
514 | master_saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
515 | ||
516 | /* | |
517 | * If the saif's master is not himself, we also need to enable | |
518 | * itself clk for its internal basic logic to work. | |
519 | */ | |
520 | if (saif != master_saif) { | |
521 | clk_enable(saif->clk); | |
2a24f2ce DA |
522 | __raw_writel(BM_SAIF_CTRL_RUN, |
523 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
76067540 | 524 | } |
2a24f2ce DA |
525 | |
526 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
527 | /* | |
f55f1475 FE |
528 | * write data to saif data register to trigger |
529 | * the transfer. | |
530 | * For 24-bit format the 32-bit FIFO register stores | |
531 | * only one channel, so we need to write twice. | |
532 | * This is also safe for the other non 24-bit formats. | |
2a24f2ce DA |
533 | */ |
534 | __raw_writel(0, saif->base + SAIF_DATA); | |
f55f1475 | 535 | __raw_writel(0, saif->base + SAIF_DATA); |
2a24f2ce DA |
536 | } else { |
537 | /* | |
f55f1475 FE |
538 | * read data from saif data register to trigger |
539 | * the receive. | |
540 | * For 24-bit format the 32-bit FIFO register stores | |
541 | * only one channel, so we need to read twice. | |
542 | * This is also safe for the other non 24-bit formats. | |
2a24f2ce DA |
543 | */ |
544 | __raw_readl(saif->base + SAIF_DATA); | |
f55f1475 | 545 | __raw_readl(saif->base + SAIF_DATA); |
2a24f2ce DA |
546 | } |
547 | ||
76067540 DA |
548 | master_saif->ongoing = 1; |
549 | ||
550 | dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", | |
2a24f2ce DA |
551 | __raw_readl(saif->base + SAIF_CTRL), |
552 | __raw_readl(saif->base + SAIF_STAT)); | |
553 | ||
76067540 DA |
554 | dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", |
555 | __raw_readl(master_saif->base + SAIF_CTRL), | |
556 | __raw_readl(master_saif->base + SAIF_STAT)); | |
2a24f2ce DA |
557 | break; |
558 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
559 | case SNDRV_PCM_TRIGGER_STOP: | |
560 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
561 | dev_dbg(cpu_dai->dev, "stop\n"); | |
562 | ||
76067540 DA |
563 | /* wait a while for the current sample to complete */ |
564 | delay = USEC_PER_SEC / master_saif->cur_rate; | |
565 | ||
566 | if (!master_saif->mclk_in_use) { | |
567 | __raw_writel(BM_SAIF_CTRL_RUN, | |
568 | master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
569 | udelay(delay); | |
570 | } | |
571 | clk_disable(master_saif->clk); | |
572 | ||
573 | if (saif != master_saif) { | |
2a24f2ce DA |
574 | __raw_writel(BM_SAIF_CTRL_RUN, |
575 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
76067540 DA |
576 | udelay(delay); |
577 | clk_disable(saif->clk); | |
578 | } | |
579 | ||
580 | master_saif->ongoing = 0; | |
2a24f2ce DA |
581 | |
582 | break; | |
583 | default: | |
584 | return -EINVAL; | |
585 | } | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 | |
591 | #define MXS_SAIF_FORMATS \ | |
592 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
593 | SNDRV_PCM_FMTBIT_S24_LE) | |
594 | ||
85e7652d | 595 | static const struct snd_soc_dai_ops mxs_saif_dai_ops = { |
2a24f2ce DA |
596 | .startup = mxs_saif_startup, |
597 | .trigger = mxs_saif_trigger, | |
598 | .prepare = mxs_saif_prepare, | |
599 | .hw_params = mxs_saif_hw_params, | |
600 | .set_sysclk = mxs_saif_set_dai_sysclk, | |
601 | .set_fmt = mxs_saif_set_dai_fmt, | |
602 | }; | |
603 | ||
604 | static int mxs_saif_dai_probe(struct snd_soc_dai *dai) | |
605 | { | |
606 | struct mxs_saif *saif = dev_get_drvdata(dai->dev); | |
607 | ||
608 | snd_soc_dai_set_drvdata(dai, saif); | |
609 | ||
610 | return 0; | |
611 | } | |
612 | ||
613 | static struct snd_soc_dai_driver mxs_saif_dai = { | |
614 | .name = "mxs-saif", | |
615 | .probe = mxs_saif_dai_probe, | |
616 | .playback = { | |
617 | .channels_min = 2, | |
618 | .channels_max = 2, | |
619 | .rates = MXS_SAIF_RATES, | |
620 | .formats = MXS_SAIF_FORMATS, | |
621 | }, | |
622 | .capture = { | |
623 | .channels_min = 2, | |
624 | .channels_max = 2, | |
625 | .rates = MXS_SAIF_RATES, | |
626 | .formats = MXS_SAIF_FORMATS, | |
627 | }, | |
628 | .ops = &mxs_saif_dai_ops, | |
629 | }; | |
630 | ||
631 | static irqreturn_t mxs_saif_irq(int irq, void *dev_id) | |
632 | { | |
633 | struct mxs_saif *saif = dev_id; | |
634 | unsigned int stat; | |
635 | ||
636 | stat = __raw_readl(saif->base + SAIF_STAT); | |
637 | if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | | |
638 | BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) | |
639 | return IRQ_NONE; | |
640 | ||
641 | if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { | |
642 | dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); | |
643 | __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, | |
644 | saif->base + SAIF_STAT + MXS_CLR_ADDR); | |
645 | } | |
646 | ||
647 | if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { | |
648 | dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); | |
649 | __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, | |
650 | saif->base + SAIF_STAT + MXS_CLR_ADDR); | |
651 | } | |
652 | ||
653 | dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", | |
654 | __raw_readl(saif->base + SAIF_CTRL), | |
655 | __raw_readl(saif->base + SAIF_STAT)); | |
656 | ||
657 | return IRQ_HANDLED; | |
658 | } | |
659 | ||
fd582736 | 660 | static int mxs_saif_probe(struct platform_device *pdev) |
2a24f2ce | 661 | { |
08641c7c | 662 | struct device_node *np = pdev->dev.of_node; |
226d0f22 | 663 | struct resource *iores, *dmares; |
2a24f2ce | 664 | struct mxs_saif *saif; |
76067540 | 665 | struct mxs_saif_platform_data *pdata; |
f755865f | 666 | struct pinctrl *pinctrl; |
2a24f2ce DA |
667 | int ret = 0; |
668 | ||
08641c7c SG |
669 | |
670 | if (!np && pdev->id >= ARRAY_SIZE(mxs_saif)) | |
0bb98ba2 JL |
671 | return -EINVAL; |
672 | ||
830eb876 | 673 | saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); |
2a24f2ce DA |
674 | if (!saif) |
675 | return -ENOMEM; | |
676 | ||
08641c7c SG |
677 | if (np) { |
678 | struct device_node *master; | |
679 | saif->id = of_alias_get_id(np, "saif"); | |
680 | if (saif->id < 0) | |
681 | return saif->id; | |
682 | /* | |
683 | * If there is no "fsl,saif-master" phandle, it's a saif | |
684 | * master. Otherwise, it's a slave and its phandle points | |
685 | * to the master. | |
686 | */ | |
687 | master = of_parse_phandle(np, "fsl,saif-master", 0); | |
688 | if (!master) { | |
689 | saif->master_id = saif->id; | |
690 | } else { | |
691 | saif->master_id = of_alias_get_id(master, "saif"); | |
692 | if (saif->master_id < 0) | |
693 | return saif->master_id; | |
77882580 DA |
694 | } |
695 | } else { | |
08641c7c SG |
696 | saif->id = pdev->id; |
697 | pdata = pdev->dev.platform_data; | |
698 | if (pdata && !pdata->master_mode) | |
699 | saif->master_id = pdata->master_id; | |
700 | else | |
701 | saif->master_id = saif->id; | |
702 | } | |
703 | ||
704 | if (saif->master_id < 0 || saif->master_id >= ARRAY_SIZE(mxs_saif)) { | |
705 | dev_err(&pdev->dev, "get wrong master id\n"); | |
706 | return -EINVAL; | |
76067540 | 707 | } |
2a24f2ce | 708 | |
08641c7c SG |
709 | mxs_saif[saif->id] = saif; |
710 | ||
f755865f SG |
711 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
712 | if (IS_ERR(pinctrl)) { | |
713 | ret = PTR_ERR(pinctrl); | |
714 | return ret; | |
715 | } | |
716 | ||
730963f8 | 717 | saif->clk = devm_clk_get(&pdev->dev, NULL); |
2a24f2ce DA |
718 | if (IS_ERR(saif->clk)) { |
719 | ret = PTR_ERR(saif->clk); | |
720 | dev_err(&pdev->dev, "Cannot get the clock: %d\n", | |
721 | ret); | |
830eb876 | 722 | return ret; |
2a24f2ce DA |
723 | } |
724 | ||
226d0f22 | 725 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2a24f2ce | 726 | |
b25b5aa0 TR |
727 | saif->base = devm_ioremap_resource(&pdev->dev, iores); |
728 | if (IS_ERR(saif->base)) | |
729 | return PTR_ERR(saif->base); | |
2a24f2ce | 730 | |
226d0f22 JL |
731 | dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
732 | if (!dmares) { | |
08641c7c SG |
733 | /* |
734 | * TODO: This is a temporary solution and should be changed | |
735 | * to use generic DMA binding later when the helplers get in. | |
736 | */ | |
737 | ret = of_property_read_u32(np, "fsl,saif-dma-channel", | |
738 | &saif->dma_param.chan_num); | |
739 | if (ret) { | |
740 | dev_err(&pdev->dev, "failed to get dma channel\n"); | |
730963f8 | 741 | return ret; |
08641c7c SG |
742 | } |
743 | } else { | |
744 | saif->dma_param.chan_num = dmares->start; | |
2a24f2ce | 745 | } |
2a24f2ce DA |
746 | |
747 | saif->irq = platform_get_irq(pdev, 0); | |
748 | if (saif->irq < 0) { | |
749 | ret = saif->irq; | |
750 | dev_err(&pdev->dev, "failed to get irq resource: %d\n", | |
751 | ret); | |
730963f8 | 752 | return ret; |
2a24f2ce DA |
753 | } |
754 | ||
755 | saif->dev = &pdev->dev; | |
830eb876 JL |
756 | ret = devm_request_irq(&pdev->dev, saif->irq, mxs_saif_irq, 0, |
757 | "mxs-saif", saif); | |
2a24f2ce DA |
758 | if (ret) { |
759 | dev_err(&pdev->dev, "failed to request irq\n"); | |
730963f8 | 760 | return ret; |
2a24f2ce DA |
761 | } |
762 | ||
763 | saif->dma_param.chan_irq = platform_get_irq(pdev, 1); | |
764 | if (saif->dma_param.chan_irq < 0) { | |
765 | ret = saif->dma_param.chan_irq; | |
766 | dev_err(&pdev->dev, "failed to get dma irq resource: %d\n", | |
767 | ret); | |
730963f8 | 768 | return ret; |
2a24f2ce DA |
769 | } |
770 | ||
771 | platform_set_drvdata(pdev, saif); | |
772 | ||
773 | ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai); | |
774 | if (ret) { | |
775 | dev_err(&pdev->dev, "register DAI failed\n"); | |
730963f8 | 776 | return ret; |
2a24f2ce DA |
777 | } |
778 | ||
4da3fe78 | 779 | ret = mxs_pcm_platform_register(&pdev->dev); |
2a24f2ce | 780 | if (ret) { |
4da3fe78 SG |
781 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); |
782 | goto failed_pdev_alloc; | |
2a24f2ce DA |
783 | } |
784 | ||
785 | return 0; | |
786 | ||
2a24f2ce DA |
787 | failed_pdev_alloc: |
788 | snd_soc_unregister_dai(&pdev->dev); | |
2a24f2ce DA |
789 | |
790 | return ret; | |
791 | } | |
792 | ||
fd582736 | 793 | static int mxs_saif_remove(struct platform_device *pdev) |
2a24f2ce | 794 | { |
4da3fe78 | 795 | mxs_pcm_platform_unregister(&pdev->dev); |
2a24f2ce | 796 | snd_soc_unregister_dai(&pdev->dev); |
2a24f2ce DA |
797 | |
798 | return 0; | |
799 | } | |
800 | ||
08641c7c SG |
801 | static const struct of_device_id mxs_saif_dt_ids[] = { |
802 | { .compatible = "fsl,imx28-saif", }, | |
803 | { /* sentinel */ } | |
804 | }; | |
805 | MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); | |
806 | ||
2a24f2ce DA |
807 | static struct platform_driver mxs_saif_driver = { |
808 | .probe = mxs_saif_probe, | |
fd582736 | 809 | .remove = mxs_saif_remove, |
2a24f2ce DA |
810 | |
811 | .driver = { | |
812 | .name = "mxs-saif", | |
813 | .owner = THIS_MODULE, | |
08641c7c | 814 | .of_match_table = mxs_saif_dt_ids, |
2a24f2ce DA |
815 | }, |
816 | }; | |
817 | ||
85aa0960 | 818 | module_platform_driver(mxs_saif_driver); |
2a24f2ce | 819 | |
2a24f2ce DA |
820 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); |
821 | MODULE_DESCRIPTION("MXS ASoC SAIF driver"); | |
822 | MODULE_LICENSE("GPL"); | |
9f4c3f1c | 823 | MODULE_ALIAS("platform:mxs-saif"); |