[deliverable/linux.git] / sound / soc / nuc900 / nuc900-ac97.c

/*
 * Copyright (c) 2009-2010 Nuvoton technology corporation.
 *
 * Wan ZongShun <mcuos.com@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation;version 2 of the License.
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/suspend.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <linux/clk.h>

#include <mach/mfp.h>

#include "nuc900-audio.h"

static DEFINE_MUTEX(ac97_mutex);
struct nuc900_audio *nuc900_ac97_data;

static int nuc900_checkready(void)
{
	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;

	if (!(AUDIO_READ(nuc900_audio->mmio + ACTL_ACIS0) & CODEC_READY))
		return -EPERM;

	return 0;
}

/* AC97 controller reads codec register */
static unsigned short nuc900_ac97_read(struct snd_ac97 *ac97,
					unsigned short reg)
{
	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;
	unsigned long timeout = 0x10000, val;

	mutex_lock(&ac97_mutex);

	val = nuc900_checkready();
	if (val) {
		dev_err(nuc900_audio->dev, "AC97 codec is not ready\n");
		goto out;
	}

	/* set the R_WB bit and write register index */
	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS1, R_WB | reg);

	/* set the valid frame bit and valid slots */
	val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0);
	val |= (VALID_FRAME | SLOT1_VALID);
	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, val);

	udelay(100);

	/* polling the AC_R_FINISH */
	while (!(AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON) & AC_R_FINISH)
								&& timeout--)
		mdelay(1);

	if (!timeout) {
		dev_err(nuc900_audio->dev, "AC97 read register time out !\n");
		val = -EPERM;
		goto out;
	}

	val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0) ;
	val &= ~SLOT1_VALID;
	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, val);

	if (AUDIO_READ(nuc900_audio->mmio + ACTL_ACIS1) >> 2 != reg) {
		dev_err(nuc900_audio->dev,
				"R_INDEX of REG_ACTL_ACIS1 not match!\n");
	}

	udelay(100);
	val = (AUDIO_READ(nuc900_audio->mmio + ACTL_ACIS2) & 0xFFFF);

out:
	mutex_unlock(&ac97_mutex);
	return val;
}

/* AC97 controller writes to codec register */
static void nuc900_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
				unsigned short val)
{
	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;
	unsigned long tmp, timeout = 0x10000;

	mutex_lock(&ac97_mutex);

	tmp = nuc900_checkready();
	if (tmp)
		dev_err(nuc900_audio->dev, "AC97 codec is not ready\n");

	/* clear the R_WB bit and write register index */
	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS1, reg);

	/* write register value */
	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS2, val);

	/* set the valid frame bit and valid slots */
	tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0);
	tmp |= SLOT1_VALID | SLOT2_VALID | VALID_FRAME;
	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, tmp);

	udelay(100);

	/* polling the AC_W_FINISH */
	while ((AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON) & AC_W_FINISH)
								&& timeout--)
		mdelay(1);

	if (!timeout)
		dev_err(nuc900_audio->dev, "AC97 write register time out !\n");

	tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0);
	tmp &= ~(SLOT1_VALID | SLOT2_VALID);
	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, tmp);

	mutex_unlock(&ac97_mutex);

}

static void nuc900_ac97_warm_reset(struct snd_ac97 *ac97)
{
	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;
	unsigned long val;

	mutex_lock(&ac97_mutex);

	/* warm reset AC 97 */
	val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON);
	val |= AC_W_RES;
	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACCON, val);

	udelay(100);

	val = nuc900_checkready();
	if (val)
		dev_err(nuc900_audio->dev, "AC97 codec is not ready\n");

	mutex_unlock(&ac97_mutex);
}

static void nuc900_ac97_cold_reset(struct snd_ac97 *ac97)
{
	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;
	unsigned long val;

	mutex_lock(&ac97_mutex);

	/* reset Audio Controller */
	val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET);
	val |= ACTL_RESET_BIT;
	AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val);

	val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET);
	val &= (~ACTL_RESET_BIT);
	AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val);

	/* reset AC-link interface */

	val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET);
	val |= AC_RESET;
	AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val);

	val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET);
	val &= ~AC_RESET;
	AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val);

	/* cold reset AC 97 */
	val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON);
	val |= AC_C_RES;
	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACCON, val);

	val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON);
	val &= (~AC_C_RES);
	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACCON, val);

	udelay(100);

	mutex_unlock(&ac97_mutex);

}

/* AC97 controller operations */
static struct snd_ac97_bus_ops nuc900_ac97_ops = {
	.read		= nuc900_ac97_read,
	.write		= nuc900_ac97_write,
	.reset		= nuc900_ac97_cold_reset,
	.warm_reset	= nuc900_ac97_warm_reset,
};

static int nuc900_ac97_trigger(struct snd_pcm_substream *substream,
				int cmd, struct snd_soc_dai *dai)
{
	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;
	int ret;
	unsigned long val, tmp;

	ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
		val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET);
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
			tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0);
			tmp |= (SLOT3_VALID | SLOT4_VALID | VALID_FRAME);
			AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, tmp);

			tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_PSR);
			tmp |= (P_DMA_END_IRQ | P_DMA_MIDDLE_IRQ);
			AUDIO_WRITE(nuc900_audio->mmio + ACTL_PSR, tmp);
			val |= AC_PLAY;
		} else {
			tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_RSR);
			tmp |= (R_DMA_END_IRQ | R_DMA_MIDDLE_IRQ);

			AUDIO_WRITE(nuc900_audio->mmio + ACTL_RSR, tmp);
			val |= AC_RECORD;
		}

		AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val);

		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
		val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET);
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
			tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0);
			tmp &= ~(SLOT3_VALID | SLOT4_VALID);
			AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, tmp);

			AUDIO_WRITE(nuc900_audio->mmio + ACTL_PSR, RESET_PRSR);
			val &= ~AC_PLAY;
		} else {
			AUDIO_WRITE(nuc900_audio->mmio + ACTL_RSR, RESET_PRSR);
			val &= ~AC_RECORD;
		}

		AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val);

		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static int nuc900_ac97_probe(struct snd_soc_dai *dai)
{
	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;
	unsigned long val;

	mutex_lock(&ac97_mutex);

	/* enable unit clock */
	clk_enable(nuc900_audio->clk);

	/* enable audio controller and AC-link interface */
	val = AUDIO_READ(nuc900_audio->mmio + ACTL_CON);
	val |= (IIS_AC_PIN_SEL | ACLINK_EN);
	AUDIO_WRITE(nuc900_audio->mmio + ACTL_CON, val);

	mutex_unlock(&ac97_mutex);

	return 0;
}

static int nuc900_ac97_remove(struct snd_soc_dai *dai)
{
	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;

	clk_disable(nuc900_audio->clk);
	return 0;
}

static const struct snd_soc_dai_ops nuc900_ac97_dai_ops = {
	.trigger	= nuc900_ac97_trigger,
};

static struct snd_soc_dai_driver nuc900_ac97_dai = {
	.probe			= nuc900_ac97_probe,
	.remove			= nuc900_ac97_remove,
	.ac97_control		= 1,
	.playback = {
		.rates		= SNDRV_PCM_RATE_8000_48000,
		.formats	= SNDRV_PCM_FMTBIT_S16_LE,
		.channels_min	= 1,
		.channels_max	= 2,
	},
	.capture = {
		.rates		= SNDRV_PCM_RATE_8000_48000,
		.formats	= SNDRV_PCM_FMTBIT_S16_LE,
		.channels_min	= 1,
		.channels_max	= 2,
	},
	.ops = &nuc900_ac97_dai_ops,
};

static const struct snd_soc_component_driver nuc900_ac97_component = {
	.name		= "nuc900-ac97",
};

static int nuc900_ac97_drvprobe(struct platform_device *pdev)
{
	struct nuc900_audio *nuc900_audio;
	int ret;

	if (nuc900_ac97_data)
		return -EBUSY;

	nuc900_audio = devm_kzalloc(&pdev->dev, sizeof(struct nuc900_audio),
				    GFP_KERNEL);
	if (!nuc900_audio)
		return -ENOMEM;

	spin_lock_init(&nuc900_audio->lock);

	nuc900_audio->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	nuc900_audio->mmio = devm_ioremap_resource(&pdev->dev,
						   nuc900_audio->res);
	if (IS_ERR(nuc900_audio->mmio))
		return PTR_ERR(nuc900_audio->mmio);

	nuc900_audio->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(nuc900_audio->clk)) {
		ret = PTR_ERR(nuc900_audio->clk);
		goto out;
	}

	nuc900_audio->irq_num = platform_get_irq(pdev, 0);
	if (!nuc900_audio->irq_num) {
		ret = -EBUSY;
		goto out;
	}

	nuc900_ac97_data = nuc900_audio;

	ret = snd_soc_set_ac97_ops(&nuc900_ac97_ops);
	if (ret)
		goto out;

	ret = snd_soc_register_component(&pdev->dev, &nuc900_ac97_component,
					 &nuc900_ac97_dai, 1);
	if (ret)
		goto out;

	/* enbale ac97 multifunction pin */
	mfp_set_groupg(nuc900_audio->dev, NULL);

	return 0;

out:
	snd_soc_set_ac97_ops(NULL);
	return ret;
}

static int nuc900_ac97_drvremove(struct platform_device *pdev)
{
	snd_soc_unregister_component(&pdev->dev);

	nuc900_ac97_data = NULL;
	snd_soc_set_ac97_ops(NULL);

	return 0;
}

static struct platform_driver nuc900_ac97_driver = {
	.driver	= {
		.name	= "nuc900-ac97",
		.owner	= THIS_MODULE,
	},
	.probe		= nuc900_ac97_drvprobe,
	.remove		= nuc900_ac97_drvremove,
};

module_platform_driver(nuc900_ac97_driver);

MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
MODULE_DESCRIPTION("NUC900 AC97 SoC driver!");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:nuc900-ac97");
Commit	Line	Data
1082e270 WZ	1	/*
	2	* Copyright (c) 2009-2010 Nuvoton technology corporation.
	3	*
	4	* Wan ZongShun <mcuos.com@gmail.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation;version 2 of the License.
	9	*
	10	*/
	11
	12	#include <linux/init.h>
	13	#include <linux/module.h>
	14	#include <linux/slab.h>
	15	#include <linux/device.h>
	16	#include <linux/delay.h>
	17	#include <linux/mutex.h>
	18	#include <linux/suspend.h>
	19	#include <sound/core.h>
	20	#include <sound/pcm.h>
	21	#include <sound/initval.h>
	22	#include <sound/soc.h>
1082e270 WZ	23	#include <linux/clk.h>
	24
	25	#include <mach/mfp.h>
	26
0dc3b442	27	#include "nuc900-audio.h"
1082e270 WZ	28
	29	static DEFINE_MUTEX(ac97_mutex);
	30	struct nuc900_audio *nuc900_ac97_data;
	31
	32	static int nuc900_checkready(void)
	33	{
	34	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;
	35
	36	if (!(AUDIO_READ(nuc900_audio->mmio + ACTL_ACIS0) & CODEC_READY))
	37	return -EPERM;
	38
	39	return 0;
	40	}
	41
	42	/* AC97 controller reads codec register */
	43	static unsigned short nuc900_ac97_read(struct snd_ac97 *ac97,
	44	unsigned short reg)
	45	{
	46	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;
	47	unsigned long timeout = 0x10000, val;
	48
	49	mutex_lock(&ac97_mutex);
	50
	51	val = nuc900_checkready();
3f90e502	52	if (val) {
1082e270 WZ	53	dev_err(nuc900_audio->dev, "AC97 codec is not ready\n");
	54	goto out;
	55	}
	56
	57	/* set the R_WB bit and write register index */
	58	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS1, R_WB \| reg);
	59
	60	/* set the valid frame bit and valid slots */
	61	val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0);
	62	val \|= (VALID_FRAME \| SLOT1_VALID);
	63	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, val);
	64
	65	udelay(100);
	66
	67	/* polling the AC_R_FINISH */
8dfb0c78 WZ	68	while (!(AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON) & AC_R_FINISH)
8dfb0c78 WZ	69	&& timeout--)
1082e270 WZ	70	mdelay(1);
	71
	72	if (!timeout) {
	73	dev_err(nuc900_audio->dev, "AC97 read register time out !\n");
	74	val = -EPERM;
	75	goto out;
	76	}
	77
	78	val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0) ;
	79	val &= ~SLOT1_VALID;
	80	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, val);
	81
	82	if (AUDIO_READ(nuc900_audio->mmio + ACTL_ACIS1) >> 2 != reg) {
	83	dev_err(nuc900_audio->dev,
	84	"R_INDEX of REG_ACTL_ACIS1 not match!\n");
	85	}
	86
	87	udelay(100);
	88	val = (AUDIO_READ(nuc900_audio->mmio + ACTL_ACIS2) & 0xFFFF);
	89
	90	out:
	91	mutex_unlock(&ac97_mutex);
	92	return val;
	93	}
	94
	95	/* AC97 controller writes to codec register */
	96	static void nuc900_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
	97	unsigned short val)
	98	{
	99	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;
	100	unsigned long tmp, timeout = 0x10000;
	101
	102	mutex_lock(&ac97_mutex);
	103
	104	tmp = nuc900_checkready();
3f90e502	105	if (tmp)
1082e270 WZ	106	dev_err(nuc900_audio->dev, "AC97 codec is not ready\n");
	107
	108	/* clear the R_WB bit and write register index */
	109	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS1, reg);
	110
	111	/* write register value */
	112	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS2, val);
	113
	114	/* set the valid frame bit and valid slots */
	115	tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0);
	116	tmp \|= SLOT1_VALID \| SLOT2_VALID \| VALID_FRAME;
	117	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, tmp);
	118
	119	udelay(100);
	120
	121	/* polling the AC_W_FINISH */
8dfb0c78 WZ	122	while ((AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON) & AC_W_FINISH)
8dfb0c78 WZ	123	&& timeout--)
1082e270 WZ	124	mdelay(1);
	125
	126	if (!timeout)
	127	dev_err(nuc900_audio->dev, "AC97 write register time out !\n");
	128
	129	tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0);
	130	tmp &= ~(SLOT1_VALID \| SLOT2_VALID);
	131	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, tmp);
	132
	133	mutex_unlock(&ac97_mutex);
	134
	135	}
	136
	137	static void nuc900_ac97_warm_reset(struct snd_ac97 *ac97)
	138	{
	139	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;
	140	unsigned long val;
	141
	142	mutex_lock(&ac97_mutex);
	143
	144	/* warm reset AC 97 */
	145	val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON);
	146	val \|= AC_W_RES;
	147	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACCON, val);
	148
08a0b717	149	udelay(100);
1082e270 WZ	150
1082e270 WZ	151	val = nuc900_checkready();
3f90e502	152	if (val)
1082e270 WZ	153	dev_err(nuc900_audio->dev, "AC97 codec is not ready\n");
	154
	155	mutex_unlock(&ac97_mutex);
	156	}
	157
	158	static void nuc900_ac97_cold_reset(struct snd_ac97 *ac97)
	159	{
	160	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;
	161	unsigned long val;
	162
	163	mutex_lock(&ac97_mutex);
	164
	165	/* reset Audio Controller */
	166	val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET);
	167	val \|= ACTL_RESET_BIT;
	168	AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val);
	169
1082e270 WZ	170	val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET);
	171	val &= (~ACTL_RESET_BIT);
	172	AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val);
	173
1082e270 WZ	174	/* reset AC-link interface */
	175
	176	val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET);
	177	val \|= AC_RESET;
	178	AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val);
	179
1082e270 WZ	180	val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET);
	181	val &= ~AC_RESET;
	182	AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val);
	183
1082e270 WZ	184	/* cold reset AC 97 */
	185	val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON);
	186	val \|= AC_C_RES;
	187	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACCON, val);
	188
1082e270 WZ	189	val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON);
	190	val &= (~AC_C_RES);
	191	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACCON, val);
	192
08a0b717	193	udelay(100);
1082e270 WZ	194
	195	mutex_unlock(&ac97_mutex);
	196
	197	}
	198
	199	/* AC97 controller operations */
b047e1cc	200	static struct snd_ac97_bus_ops nuc900_ac97_ops = {
1082e270 WZ	201	.read = nuc900_ac97_read,
	202	.write = nuc900_ac97_write,
	203	.reset = nuc900_ac97_cold_reset,
	204	.warm_reset = nuc900_ac97_warm_reset,
b047e1cc	205	};
1082e270 WZ	206
	207	static int nuc900_ac97_trigger(struct snd_pcm_substream *substream,
	208	int cmd, struct snd_soc_dai *dai)
	209	{
	210	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;
018334c0	211	int ret;
1082e270 WZ	212	unsigned long val, tmp;
	213
	214	ret = 0;
	215
	216	switch (cmd) {
	217	case SNDRV_PCM_TRIGGER_START:
	218	case SNDRV_PCM_TRIGGER_RESUME:
	219	val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET);
018334c0	220	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1082e270 WZ	221	tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0);
	222	tmp \|= (SLOT3_VALID \| SLOT4_VALID \| VALID_FRAME);
	223	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, tmp);
	224
	225	tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_PSR);
	226	tmp \|= (P_DMA_END_IRQ \| P_DMA_MIDDLE_IRQ);
	227	AUDIO_WRITE(nuc900_audio->mmio + ACTL_PSR, tmp);
	228	val \|= AC_PLAY;
	229	} else {
	230	tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_RSR);
	231	tmp \|= (R_DMA_END_IRQ \| R_DMA_MIDDLE_IRQ);
	232
	233	AUDIO_WRITE(nuc900_audio->mmio + ACTL_RSR, tmp);
	234	val \|= AC_RECORD;
	235	}
	236
	237	AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val);
	238
	239	break;
	240	case SNDRV_PCM_TRIGGER_STOP:
	241	case SNDRV_PCM_TRIGGER_SUSPEND:
	242	val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET);
018334c0	243	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1082e270 WZ	244	tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0);
	245	tmp &= ~(SLOT3_VALID \| SLOT4_VALID);
	246	AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, tmp);
	247
	248	AUDIO_WRITE(nuc900_audio->mmio + ACTL_PSR, RESET_PRSR);
	249	val &= ~AC_PLAY;
	250	} else {
	251	AUDIO_WRITE(nuc900_audio->mmio + ACTL_RSR, RESET_PRSR);
	252	val &= ~AC_RECORD;
	253	}
	254
	255	AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val);
	256
	257	break;
	258	default:
	259	ret = -EINVAL;
	260	}
	261
	262	return ret;
	263	}
	264
e3edefbd	265	static int nuc900_ac97_probe(struct snd_soc_dai *dai)
1082e270 WZ	266	{
	267	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;
	268	unsigned long val;
	269
	270	mutex_lock(&ac97_mutex);
	271
	272	/* enable unit clock */
	273	clk_enable(nuc900_audio->clk);
	274
	275	/* enable audio controller and AC-link interface */
	276	val = AUDIO_READ(nuc900_audio->mmio + ACTL_CON);
	277	val \|= (IIS_AC_PIN_SEL \| ACLINK_EN);
	278	AUDIO_WRITE(nuc900_audio->mmio + ACTL_CON, val);
	279
	280	mutex_unlock(&ac97_mutex);
	281
	282	return 0;
	283	}
	284
e3edefbd	285	static int nuc900_ac97_remove(struct snd_soc_dai *dai)
1082e270 WZ	286	{
	287	struct nuc900_audio *nuc900_audio = nuc900_ac97_data;
	288
	289	clk_disable(nuc900_audio->clk);
e3edefbd	290	return 0;
1082e270 WZ	291	}
1082e270 WZ	292
85e7652d	293	static const struct snd_soc_dai_ops nuc900_ac97_dai_ops = {
1082e270 WZ	294	.trigger = nuc900_ac97_trigger,
	295	};
	296
f0fba2ad	297	static struct snd_soc_dai_driver nuc900_ac97_dai = {
1082e270 WZ	298	.probe = nuc900_ac97_probe,
	299	.remove = nuc900_ac97_remove,
	300	.ac97_control = 1,
	301	.playback = {
	302	.rates = SNDRV_PCM_RATE_8000_48000,
	303	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	304	.channels_min = 1,
	305	.channels_max = 2,
	306	},
	307	.capture = {
	308	.rates = SNDRV_PCM_RATE_8000_48000,
	309	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	310	.channels_min = 1,
	311	.channels_max = 2,
	312	},
	313	.ops = &nuc900_ac97_dai_ops,
5a8f1d47	314	};
1082e270	315
7fc34cc3 KM	316	static const struct snd_soc_component_driver nuc900_ac97_component = {
	317	.name = "nuc900-ac97",
	318	};
	319
ce69ace5	320	static int nuc900_ac97_drvprobe(struct platform_device *pdev)
1082e270 WZ	321	{
	322	struct nuc900_audio *nuc900_audio;
	323	int ret;
	324
	325	if (nuc900_ac97_data)
	326	return -EBUSY;
	327
ad3ae47b MB	328	nuc900_audio = devm_kzalloc(&pdev->dev, sizeof(struct nuc900_audio),
ad3ae47b MB	329	GFP_KERNEL);
1082e270 WZ	330	if (!nuc900_audio)
	331	return -ENOMEM;
	332
	333	spin_lock_init(&nuc900_audio->lock);
	334
	335	nuc900_audio->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ad3ae47b MB	336	nuc900_audio->mmio = devm_ioremap_resource(&pdev->dev,
	337	nuc900_audio->res);
	338	if (IS_ERR(nuc900_audio->mmio))
	339	return PTR_ERR(nuc900_audio->mmio);
1082e270	340
ad3ae47b	341	nuc900_audio->clk = devm_clk_get(&pdev->dev, NULL);
1082e270 WZ	342	if (IS_ERR(nuc900_audio->clk)) {
1082e270 WZ	343	ret = PTR_ERR(nuc900_audio->clk);
ad3ae47b	344	goto out;
1082e270 WZ	345	}
	346
	347	nuc900_audio->irq_num = platform_get_irq(pdev, 0);
	348	if (!nuc900_audio->irq_num) {
	349	ret = -EBUSY;
ad3ae47b	350	goto out;
1082e270 WZ	351	}
	352
	353	nuc900_ac97_data = nuc900_audio;
	354
b047e1cc MB	355	ret = snd_soc_set_ac97_ops(&nuc900_ac97_ops);
	356	if (ret)
	357	goto out;
	358
7fc34cc3 KM	359	ret = snd_soc_register_component(&pdev->dev, &nuc900_ac97_component,
7fc34cc3 KM	360	&nuc900_ac97_dai, 1);
1082e270	361	if (ret)
ad3ae47b	362	goto out;
1082e270	363
97371fa9	364	/* enbale ac97 multifunction pin */
e37051dc	365	mfp_set_groupg(nuc900_audio->dev, NULL);
1082e270 WZ	366
	367	return 0;
	368
ad3ae47b	369	out:
b047e1cc	370	snd_soc_set_ac97_ops(NULL);
1082e270 WZ	371	return ret;
	372	}
	373
ce69ace5	374	static int nuc900_ac97_drvremove(struct platform_device *pdev)
1082e270	375	{
7fc34cc3	376	snd_soc_unregister_component(&pdev->dev);
1082e270	377
1082e270	378	nuc900_ac97_data = NULL;
b047e1cc	379	snd_soc_set_ac97_ops(NULL);
1082e270 WZ	380
	381	return 0;
	382	}
	383
	384	static struct platform_driver nuc900_ac97_driver = {
	385	.driver = {
f0fba2ad	386	.name = "nuc900-ac97",
1082e270 WZ	387	.owner = THIS_MODULE,
	388	},
	389	.probe = nuc900_ac97_drvprobe,
ce69ace5	390	.remove = nuc900_ac97_drvremove,
1082e270 WZ	391	};
1082e270 WZ	392
d0efa6a2	393	module_platform_driver(nuc900_ac97_driver);
1082e270 WZ	394
	395	MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
	396	MODULE_DESCRIPTION("NUC900 AC97 SoC driver!");
	397	MODULE_LICENSE("GPL");
	398	MODULE_ALIAS("platform:nuc900-ac97");