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Merge tag 'sound-4.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai...
[deliverable/linux.git] / sound / soc / omap / mcbsp.c
CommitLineData
5e1c5ff4 1/*
71e822e9 2 * sound/soc/omap/mcbsp.c
5e1c5ff4
TL		 3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
71e822e9
PU		 7 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
8 * Peter Ujfalusi <peter.ujfalusi@ti.com>
5e1c5ff4
TL		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Multichannel mode not supported.
15 */
16
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/device.h>
bc5d0c89 20#include <linux/platform_device.h>
5e1c5ff4
TL		 21#include <linux/interrupt.h>
22#include <linux/err.h>
f8ce2547 23#include <linux/clk.h>
04fbf6a2 24#include <linux/delay.h>
fb78d808 25#include <linux/io.h>
5a0e3ad6 26#include <linux/slab.h>
f199131a 27#include <linux/pm_runtime.h>
5e1c5ff4 28
2203747c 29#include <linux/platform_data/asoc-ti-mcbsp.h>
5e1c5ff4 30
219f4316
PU		 31#include "mcbsp.h"
32
b0a330dc 33static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
b4b58f58 34{
cdc71514
JN		 35 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
36
37 if (mcbsp->pdata->reg_size == 2) {
38 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
1b488a48 39 writew_relaxed((u16)val, addr);
c8c99699 40 } else {
cdc71514 41 ((u32 *)mcbsp->reg_cache)[reg] = val;
1b488a48 42 writel_relaxed(val, addr);
c8c99699 43 }
b4b58f58
CS		 44}
45
b0a330dc 46static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
b4b58f58 47{
cdc71514
JN		 48 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
49
50 if (mcbsp->pdata->reg_size == 2) {
1b488a48 51 return !from_cache ? readw_relaxed(addr) :
cdc71514 52 ((u16 *)mcbsp->reg_cache)[reg];
c8c99699 53 } else {
1b488a48 54 return !from_cache ? readl_relaxed(addr) :
cdc71514 55 ((u32 *)mcbsp->reg_cache)[reg];
c8c99699 56 }
b4b58f58
CS		 57}
58
b0a330dc 59static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
d912fa92 60{
1b488a48 61 writel_relaxed(val, mcbsp->st_data->io_base_st + reg);
d912fa92
EN		 62}
63
b0a330dc 64static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
d912fa92 65{
1b488a48 66 return readl_relaxed(mcbsp->st_data->io_base_st + reg);
d912fa92 67}
d912fa92 68
8ea3200f 69#define MCBSP_READ(mcbsp, reg) \
c8c99699 70 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
8ea3200f
JK		 71#define MCBSP_WRITE(mcbsp, reg, val) \
72 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
c8c99699
JK		 73#define MCBSP_READ_CACHE(mcbsp, reg) \
74 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
b4b58f58 75
d912fa92
EN		 76#define MCBSP_ST_READ(mcbsp, reg) \
77 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
78#define MCBSP_ST_WRITE(mcbsp, reg, val) \
79 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
80
45656b44 81static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
5e1c5ff4 82{
b4b58f58
CS		 83 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
84 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
8ea3200f 85 MCBSP_READ(mcbsp, DRR2));
b4b58f58 86 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
8ea3200f 87 MCBSP_READ(mcbsp, DRR1));
b4b58f58 88 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
8ea3200f 89 MCBSP_READ(mcbsp, DXR2));
b4b58f58 90 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
8ea3200f 91 MCBSP_READ(mcbsp, DXR1));
b4b58f58 92 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
8ea3200f 93 MCBSP_READ(mcbsp, SPCR2));
b4b58f58 94 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
8ea3200f 95 MCBSP_READ(mcbsp, SPCR1));
b4b58f58 96 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
8ea3200f 97 MCBSP_READ(mcbsp, RCR2));
b4b58f58 98 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
8ea3200f 99 MCBSP_READ(mcbsp, RCR1));
b4b58f58 100 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
8ea3200f 101 MCBSP_READ(mcbsp, XCR2));
b4b58f58 102 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
8ea3200f 103 MCBSP_READ(mcbsp, XCR1));
b4b58f58 104 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
8ea3200f 105 MCBSP_READ(mcbsp, SRGR2));
b4b58f58 106 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
8ea3200f 107 MCBSP_READ(mcbsp, SRGR1));
b4b58f58 108 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
8ea3200f 109 MCBSP_READ(mcbsp, PCR0));
b4b58f58 110 dev_dbg(mcbsp->dev, "***********************\n");
5e1c5ff4
TL		 111}
112
35d210fa
PU		 113static irqreturn_t omap_mcbsp_irq_handler(int irq, void *dev_id)
114{
115 struct omap_mcbsp *mcbsp = dev_id;
116 u16 irqst;
117
118 irqst = MCBSP_READ(mcbsp, IRQST);
119 dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
120
121 if (irqst & RSYNCERREN)
122 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
123 if (irqst & RFSREN)
124 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
125 if (irqst & REOFEN)
126 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
127 if (irqst & RRDYEN)
128 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
129 if (irqst & RUNDFLEN)
130 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
131 if (irqst & ROVFLEN)
132 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
133
134 if (irqst & XSYNCERREN)
135 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
136 if (irqst & XFSXEN)
137 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
138 if (irqst & XEOFEN)
139 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
140 if (irqst & XRDYEN)
141 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
142 if (irqst & XUNDFLEN)
143 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
144 if (irqst & XOVFLEN)
145 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
146 if (irqst & XEMPTYEOFEN)
147 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
148
149 MCBSP_WRITE(mcbsp, IRQST, irqst);
150
151 return IRQ_HANDLED;
152}
153
0cd61b68 154static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
5e1c5ff4 155{
e8f2af17 156 struct omap_mcbsp *mcbsp_tx = dev_id;
d6d834b0 157 u16 irqst_spcr2;
5e1c5ff4 158
8ea3200f 159 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
d6d834b0 160 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
5e1c5ff4 161
d6d834b0
EN		 162 if (irqst_spcr2 & XSYNC_ERR) {
163 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
164 irqst_spcr2);
165 /* Writing zero to XSYNC_ERR clears the IRQ */
0841cb82 166 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
d6d834b0 167 }
fb78d808 168
5e1c5ff4
TL		 169 return IRQ_HANDLED;
170}
171
0cd61b68 172static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
5e1c5ff4 173{
e8f2af17 174 struct omap_mcbsp *mcbsp_rx = dev_id;
d6d834b0
EN		 175 u16 irqst_spcr1;
176
8ea3200f 177 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
d6d834b0
EN		 178 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
179
180 if (irqst_spcr1 & RSYNC_ERR) {
181 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
182 irqst_spcr1);
183 /* Writing zero to RSYNC_ERR clears the IRQ */
0841cb82 184 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
d6d834b0 185 }
fb78d808 186
5e1c5ff4
TL		 187 return IRQ_HANDLED;
188}
189
5e1c5ff4
TL		 190/*
191 * omap_mcbsp_config simply write a config to the
192 * appropriate McBSP.
193 * You either call this function or set the McBSP registers
194 * by yourself before calling omap_mcbsp_start().
195 */
45656b44
PU		 196void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
197 const struct omap_mcbsp_reg_cfg *config)
5e1c5ff4 198{
b4b58f58
CS		 199 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
200 mcbsp->id, mcbsp->phys_base);
5e1c5ff4
TL		 201
202 /* We write the given config */
8ea3200f
JK		 203 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
204 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
205 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
206 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
207 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
208 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
209 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
210 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
211 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
212 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
213 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
88408230 214 if (mcbsp->pdata->has_ccr) {
8ea3200f
JK		 215 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
216 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
3127f8f8 217 }
08905d8a
PU		 218 /* Enable wakeup behavior */
219 if (mcbsp->pdata->has_wakeup)
220 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
35d210fa
PU		 221
222 /* Enable TX/RX sync error interrupts by default */
223 if (mcbsp->irq)
224 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN);
5e1c5ff4 225}
5e1c5ff4 226
9504ba64
KVA		 227/**
228 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
229 * @id - mcbsp id
230 * @stream - indicates the direction of data flow (rx or tx)
231 *
232 * Returns the address of mcbsp data transmit register or data receive register
233 * to be used by DMA for transferring/receiving data based on the value of
234 * @stream for the requested mcbsp given by @id
235 */
b8fb4907
PU		 236static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
237 unsigned int stream)
9504ba64 238{
9504ba64
KVA		 239 int data_reg;
240
cdc71514 241 if (mcbsp->pdata->reg_size == 2) {
9504ba64 242 if (stream)
cdc71514 243 data_reg = OMAP_MCBSP_REG_DRR1;
9504ba64 244 else
cdc71514 245 data_reg = OMAP_MCBSP_REG_DXR1;
9504ba64
KVA		 246 } else {
247 if (stream)
cdc71514 248 data_reg = OMAP_MCBSP_REG_DRR;
9504ba64 249 else
cdc71514 250 data_reg = OMAP_MCBSP_REG_DXR;
9504ba64
KVA		 251 }
252
cdc71514 253 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
9504ba64 254}
9504ba64 255
d912fa92
EN		 256static void omap_st_on(struct omap_mcbsp *mcbsp)
257{
258 unsigned int w;
259
1743d14f
JN		 260 if (mcbsp->pdata->enable_st_clock)
261 mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
d912fa92 262
d4e44f14
PU		 263 /* Disable Sidetone clock auto-gating for normal operation */
264 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
265 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
266
d912fa92
EN		 267 /* Enable McBSP Sidetone */
268 w = MCBSP_READ(mcbsp, SSELCR);
269 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
270
d912fa92
EN		 271 /* Enable Sidetone from Sidetone Core */
272 w = MCBSP_ST_READ(mcbsp, SSELCR);
273 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
274}
275
276static void omap_st_off(struct omap_mcbsp *mcbsp)
277{
278 unsigned int w;
279
280 w = MCBSP_ST_READ(mcbsp, SSELCR);
281 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
282
d912fa92
EN		 283 w = MCBSP_READ(mcbsp, SSELCR);
284 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
285
d4e44f14
PU		 286 /* Enable Sidetone clock auto-gating to reduce power consumption */
287 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
288 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
289
1743d14f
JN		 290 if (mcbsp->pdata->enable_st_clock)
291 mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
d912fa92
EN		 292}
293
294static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
295{
296 u16 val, i;
d912fa92
EN		 297
298 val = MCBSP_ST_READ(mcbsp, SSELCR);
299
300 if (val & ST_COEFFWREN)
301 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
302
303 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
304
305 for (i = 0; i < 128; i++)
306 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
307
308 i = 0;
309
310 val = MCBSP_ST_READ(mcbsp, SSELCR);
311 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
312 val = MCBSP_ST_READ(mcbsp, SSELCR);
313
314 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
315
316 if (i == 1000)
317 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
318}
319
320static void omap_st_chgain(struct omap_mcbsp *mcbsp)
321{
322 u16 w;
323 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 324
325 w = MCBSP_ST_READ(mcbsp, SSELCR);
326
327 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
328 ST_CH1GAIN(st_data->ch1gain));
329}
330
45656b44 331int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain)
d912fa92 332{
e2002ab3 333 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 334 int ret = 0;
335
d912fa92
EN		 336 if (!st_data)
337 return -ENOENT;
338
339 spin_lock_irq(&mcbsp->lock);
340 if (channel == 0)
341 st_data->ch0gain = chgain;
342 else if (channel == 1)
343 st_data->ch1gain = chgain;
344 else
345 ret = -EINVAL;
346
347 if (st_data->enabled)
348 omap_st_chgain(mcbsp);
349 spin_unlock_irq(&mcbsp->lock);
350
351 return ret;
352}
d912fa92 353
45656b44 354int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain)
d912fa92 355{
e2002ab3 356 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 357 int ret = 0;
358
d912fa92
EN		 359 if (!st_data)
360 return -ENOENT;
361
362 spin_lock_irq(&mcbsp->lock);
363 if (channel == 0)
364 *chgain = st_data->ch0gain;
365 else if (channel == 1)
366 *chgain = st_data->ch1gain;
367 else
368 ret = -EINVAL;
369 spin_unlock_irq(&mcbsp->lock);
370
371 return ret;
372}
d912fa92
EN		 373
374static int omap_st_start(struct omap_mcbsp *mcbsp)
375{
376 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
377
58db1dcd 378 if (st_data->enabled && !st_data->running) {
d912fa92
EN		 379 omap_st_fir_write(mcbsp, st_data->taps);
380 omap_st_chgain(mcbsp);
381
382 if (!mcbsp->free) {
383 omap_st_on(mcbsp);
384 st_data->running = 1;
385 }
386 }
387
388 return 0;
389}
390
45656b44 391int omap_st_enable(struct omap_mcbsp *mcbsp)
d912fa92 392{
e2002ab3 393 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 394
395 if (!st_data)
396 return -ENODEV;
397
398 spin_lock_irq(&mcbsp->lock);
399 st_data->enabled = 1;
400 omap_st_start(mcbsp);
401 spin_unlock_irq(&mcbsp->lock);
402
403 return 0;
404}
d912fa92
EN		 405
406static int omap_st_stop(struct omap_mcbsp *mcbsp)
407{
408 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
409
58db1dcd 410 if (st_data->running) {
d912fa92
EN		 411 if (!mcbsp->free) {
412 omap_st_off(mcbsp);
413 st_data->running = 0;
414 }
415 }
416
417 return 0;
418}
419
45656b44 420int omap_st_disable(struct omap_mcbsp *mcbsp)
d912fa92 421{
e2002ab3 422 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 423 int ret = 0;
424
d912fa92
EN		 425 if (!st_data)
426 return -ENODEV;
427
428 spin_lock_irq(&mcbsp->lock);
429 omap_st_stop(mcbsp);
430 st_data->enabled = 0;
431 spin_unlock_irq(&mcbsp->lock);
432
433 return ret;
434}
d912fa92 435
45656b44 436int omap_st_is_enabled(struct omap_mcbsp *mcbsp)
d912fa92 437{
e2002ab3 438 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 439
440 if (!st_data)
441 return -ENODEV;
442
d912fa92
EN		 443 return st_data->enabled;
444}
d912fa92 445
7aa9ff56 446/*
451fd82d
PU		 447 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
448 * The threshold parameter is 1 based, and it is converted (threshold - 1)
449 * for the THRSH2 register.
7aa9ff56 450 */
45656b44 451void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
7aa9ff56 452{
7bba67ab
JN		 453 if (mcbsp->pdata->buffer_size == 0)
454 return;
7aa9ff56 455
451fd82d
PU		 456 if (threshold && threshold <= mcbsp->max_tx_thres)
457 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
7aa9ff56 458}
7aa9ff56
EV		 459
460/*
451fd82d
PU		 461 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
462 * The threshold parameter is 1 based, and it is converted (threshold - 1)
463 * for the THRSH1 register.
7aa9ff56 464 */
45656b44 465void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
7aa9ff56 466{
7bba67ab
JN		 467 if (mcbsp->pdata->buffer_size == 0)
468 return;
7aa9ff56 469
451fd82d
PU		 470 if (threshold && threshold <= mcbsp->max_rx_thres)
471 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
7aa9ff56 472}
a1a56f5f 473
7dc976ed
PU		 474/*
475 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
476 */
45656b44 477u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
7dc976ed 478{
7dc976ed
PU		 479 u16 buffstat;
480
7bba67ab
JN		 481 if (mcbsp->pdata->buffer_size == 0)
482 return 0;
7dc976ed
PU		 483
484 /* Returns the number of free locations in the buffer */
485 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
486
487 /* Number of slots are different in McBSP ports */
f10b8ad1 488 return mcbsp->pdata->buffer_size - buffstat;
7dc976ed 489}
7dc976ed
PU		 490
491/*
492 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
493 * to reach the threshold value (when the DMA will be triggered to read it)
494 */
45656b44 495u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
7dc976ed 496{
7dc976ed
PU		 497 u16 buffstat, threshold;
498
7bba67ab
JN		 499 if (mcbsp->pdata->buffer_size == 0)
500 return 0;
7dc976ed
PU		 501
502 /* Returns the number of used locations in the buffer */
503 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
504 /* RX threshold */
505 threshold = MCBSP_READ(mcbsp, THRSH1);
506
507 /* Return the number of location till we reach the threshold limit */
508 if (threshold <= buffstat)
509 return 0;
510 else
511 return threshold - buffstat;
512}
7dc976ed 513
45656b44 514int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
5e1c5ff4 515{
c8c99699 516 void *reg_cache;
5e1c5ff4
TL		 517 int err;
518
ac6747ca 519 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
c8c99699
JK		 520 if (!reg_cache) {
521 return -ENOMEM;
522 }
523
b4b58f58
CS		 524 spin_lock(&mcbsp->lock);
525 if (!mcbsp->free) {
526 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
527 mcbsp->id);
c8c99699
JK		 528 err = -EBUSY;
529 goto err_kfree;
5e1c5ff4
TL		 530 }
531
6722a723 532 mcbsp->free = false;
c8c99699 533 mcbsp->reg_cache = reg_cache;
b4b58f58 534 spin_unlock(&mcbsp->lock);
5e1c5ff4 535
b820ce4e 536 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
45656b44 537 mcbsp->pdata->ops->request(mcbsp->id - 1);
b820ce4e 538
5a07055a
JN		 539 /*
540 * Make sure that transmitter, receiver and sample-rate generator are
541 * not running before activating IRQs.
542 */
8ea3200f
JK		 543 MCBSP_WRITE(mcbsp, SPCR1, 0);
544 MCBSP_WRITE(mcbsp, SPCR2, 0);
5a07055a 545
35d210fa
PU		 546 if (mcbsp->irq) {
547 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
548 "McBSP", (void *)mcbsp);
549 if (err != 0) {
550 dev_err(mcbsp->dev, "Unable to request IRQ\n");
551 goto err_clk_disable;
552 }
553 } else {
554 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
555 "McBSP TX", (void *)mcbsp);
556 if (err != 0) {
557 dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
558 goto err_clk_disable;
559 }
bafe2721 560
35d210fa
PU		 561 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
562 "McBSP RX", (void *)mcbsp);
120db2cb 563 if (err != 0) {
35d210fa 564 dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
bafe2721 565 goto err_free_irq;
120db2cb 566 }
5e1c5ff4
TL		 567 }
568
5e1c5ff4 569 return 0;
c8c99699 570err_free_irq:
1866b545 571 free_irq(mcbsp->tx_irq, (void *)mcbsp);
c8c99699 572err_clk_disable:
1866b545 573 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
45656b44 574 mcbsp->pdata->ops->free(mcbsp->id - 1);
1866b545 575
1a645884
JN		 576 /* Disable wakeup behavior */
577 if (mcbsp->pdata->has_wakeup)
578 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
1866b545 579
c8c99699 580 spin_lock(&mcbsp->lock);
6722a723 581 mcbsp->free = true;
c8c99699
JK		 582 mcbsp->reg_cache = NULL;
583err_kfree:
584 spin_unlock(&mcbsp->lock);
585 kfree(reg_cache);
1866b545
JK		 586
587 return err;
5e1c5ff4
TL		 588}
589
45656b44 590void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
5e1c5ff4 591{
c8c99699 592 void *reg_cache;
b4b58f58 593
b4b58f58 594 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
45656b44 595 mcbsp->pdata->ops->free(mcbsp->id - 1);
bc5d0c89 596
1a645884
JN		 597 /* Disable wakeup behavior */
598 if (mcbsp->pdata->has_wakeup)
599 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
2122fdc6 600
35d210fa
PU		 601 /* Disable interrupt requests */
602 if (mcbsp->irq)
603 MCBSP_WRITE(mcbsp, IRQEN, 0);
604
605 if (mcbsp->irq) {
606 free_irq(mcbsp->irq, (void *)mcbsp);
607 } else {
bafe2721 608 free_irq(mcbsp->rx_irq, (void *)mcbsp);
35d210fa
PU		 609 free_irq(mcbsp->tx_irq, (void *)mcbsp);
610 }
5e1c5ff4 611
c8c99699 612 reg_cache = mcbsp->reg_cache;
5e1c5ff4 613
e386615c
PU		 614 /*
615 * Select CLKS source from internal source unconditionally before
616 * marking the McBSP port as free.
617 * If the external clock source via MCBSP_CLKS pin has been selected the
618 * system will refuse to enter idle if the CLKS pin source is not reset
619 * back to internal source.
620 */
e650794a 621 if (!mcbsp_omap1())
e386615c
PU		 622 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
623
c8c99699
JK		 624 spin_lock(&mcbsp->lock);
625 if (mcbsp->free)
626 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
627 else
6722a723 628 mcbsp->free = true;
c8c99699 629 mcbsp->reg_cache = NULL;
b4b58f58 630 spin_unlock(&mcbsp->lock);
c8c99699 631
bb66f2dc 632 kfree(reg_cache);
5e1c5ff4
TL		 633}
634
635/*
c12abc01
JN		 636 * Here we start the McBSP, by enabling transmitter, receiver or both.
637 * If no transmitter or receiver is active prior calling, then sample-rate
638 * generator and frame sync are started.
5e1c5ff4 639 */
45656b44 640void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx)
5e1c5ff4 641{
ce3f054b 642 int enable_srg = 0;
5e1c5ff4
TL		 643 u16 w;
644
f821eece 645 if (mcbsp->st_data)
d912fa92
EN		 646 omap_st_start(mcbsp);
647
ce3f054b
PU		 648 /* Only enable SRG, if McBSP is master */
649 w = MCBSP_READ_CACHE(mcbsp, PCR0);
650 if (w & (FSXM | FSRM | CLKXM | CLKRM))
651 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
652 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01 653
ce3f054b 654 if (enable_srg) {
c12abc01 655 /* Start the sample generator */
96fbd745 656 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 657 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
c12abc01 658 }
5e1c5ff4
TL		 659
660 /* Enable transmitter and receiver */
d09a2afc 661 tx &= 1;
96fbd745 662 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 663 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
5e1c5ff4 664
d09a2afc 665 rx &= 1;
96fbd745 666 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 667 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
5e1c5ff4 668
44a6311c
EV		 669 /*
670 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
671 * REVISIT: 100us may give enough time for two CLKSRG, however
672 * due to some unknown PM related, clock gating etc. reason it
673 * is now at 500us.
674 */
675 udelay(500);
5e1c5ff4 676
ce3f054b 677 if (enable_srg) {
c12abc01 678 /* Start frame sync */
96fbd745 679 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 680 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
c12abc01 681 }
5e1c5ff4 682
88408230 683 if (mcbsp->pdata->has_ccr) {
d09a2afc 684 /* Release the transmitter and receiver */
96fbd745 685 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 686 w &= ~(tx ? XDISABLE : 0);
8ea3200f 687 MCBSP_WRITE(mcbsp, XCCR, w);
96fbd745 688 w = MCBSP_READ_CACHE(mcbsp, RCCR);
d09a2afc 689 w &= ~(rx ? RDISABLE : 0);
8ea3200f 690 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc
JN		 691 }
692
5e1c5ff4 693 /* Dump McBSP Regs */
45656b44 694 omap_mcbsp_dump_reg(mcbsp);
5e1c5ff4
TL		 695}
696
45656b44 697void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx)
5e1c5ff4 698{
c12abc01 699 int idle;
5e1c5ff4
TL		 700 u16 w;
701
fb78d808 702 /* Reset transmitter */
d09a2afc 703 tx &= 1;
88408230 704 if (mcbsp->pdata->has_ccr) {
96fbd745 705 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 706 w |= (tx ? XDISABLE : 0);
8ea3200f 707 MCBSP_WRITE(mcbsp, XCCR, w);
d09a2afc 708 }
96fbd745 709 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 710 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
5e1c5ff4
TL		 711
712 /* Reset receiver */
d09a2afc 713 rx &= 1;
88408230 714 if (mcbsp->pdata->has_ccr) {
96fbd745 715 w = MCBSP_READ_CACHE(mcbsp, RCCR);
a93d4ed2 716 w |= (rx ? RDISABLE : 0);
8ea3200f 717 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc 718 }
96fbd745 719 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 720 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
5e1c5ff4 721
96fbd745
JK		 722 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
723 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01
JN		 724
725 if (idle) {
726 /* Reset the sample rate generator */
96fbd745 727 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 728 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
c12abc01 729 }
d912fa92 730
f821eece 731 if (mcbsp->st_data)
d912fa92 732 omap_st_stop(mcbsp);
5e1c5ff4 733}
5e1c5ff4 734
45656b44 735int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
69d042d1 736{
f199131a 737 struct clk *fck_src;
09d28d2c 738 const char *src;
f199131a 739 int r;
09d28d2c 740
09d28d2c 741 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
f199131a 742 src = "pad_fck";
09d28d2c 743 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
f199131a 744 src = "prcm_fck";
09d28d2c
JN		 745 else
746 return -EINVAL;
747
f199131a
PU		 748 fck_src = clk_get(mcbsp->dev, src);
749 if (IS_ERR(fck_src)) {
750 dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
09d28d2c 751 return -EINVAL;
f199131a 752 }
5788c62e 753
f199131a 754 pm_runtime_put_sync(mcbsp->dev);
45656b44 755
f199131a
PU		 756 r = clk_set_parent(mcbsp->fclk, fck_src);
757 if (r) {
758 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
759 src);
760 clk_put(fck_src);
761 return r;
cd1f08c7 762 }
7bc0c4ba 763
f199131a
PU		 764 pm_runtime_get_sync(mcbsp->dev);
765
766 clk_put(fck_src);
767
768 return 0;
769
69d042d1 770}
69d042d1 771
a1a56f5f
EV		 772#define max_thres(m) (mcbsp->pdata->buffer_size)
773#define valid_threshold(m, val) ((val) <= max_thres(m))
774#define THRESHOLD_PROP_BUILDER(prop) \
775static ssize_t prop##_show(struct device *dev, \
776 struct device_attribute *attr, char *buf) \
777{ \
778 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
779 \
780 return sprintf(buf, "%u\n", mcbsp->prop); \
781} \
782 \
783static ssize_t prop##_store(struct device *dev, \
784 struct device_attribute *attr, \
785 const char *buf, size_t size) \
786{ \
787 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
788 unsigned long val; \
789 int status; \
790 \
b785a492 791 status = kstrtoul(buf, 0, &val); \
a1a56f5f
EV		 792 if (status) \
793 return status; \
794 \
795 if (!valid_threshold(mcbsp, val)) \
796 return -EDOM; \
797 \
798 mcbsp->prop = val; \
799 return size; \
800} \
801 \
802static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
803
804THRESHOLD_PROP_BUILDER(max_tx_thres);
805THRESHOLD_PROP_BUILDER(max_rx_thres);
806
9b300509 807static const char *dma_op_modes[] = {
09fa37ac 808 "element", "threshold",
9b300509
JN		 809};
810
98cb20e8
PU		 811static ssize_t dma_op_mode_show(struct device *dev,
812 struct device_attribute *attr, char *buf)
813{
814 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 815 int dma_op_mode, i = 0;
816 ssize_t len = 0;
817 const char * const *s;
98cb20e8 818
98cb20e8 819 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8 820
9b300509
JN		 821 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
822 if (dma_op_mode == i)
823 len += sprintf(buf + len, "[%s] ", *s);
824 else
825 len += sprintf(buf + len, "%s ", *s);
826 }
827 len += sprintf(buf + len, "\n");
828
829 return len;
98cb20e8
PU		 830}
831
832static ssize_t dma_op_mode_store(struct device *dev,
833 struct device_attribute *attr,
834 const char *buf, size_t size)
835{
836 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 837 const char * const *s;
838 int i = 0;
98cb20e8 839
9b300509
JN		 840 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
841 if (sysfs_streq(buf, *s))
842 break;
98cb20e8 843
9b300509
JN		 844 if (i == ARRAY_SIZE(dma_op_modes))
845 return -EINVAL;
98cb20e8 846
9b300509 847 spin_lock_irq(&mcbsp->lock);
98cb20e8
PU		 848 if (!mcbsp->free) {
849 size = -EBUSY;
850 goto unlock;
851 }
9b300509 852 mcbsp->dma_op_mode = i;
98cb20e8
PU		 853
854unlock:
855 spin_unlock_irq(&mcbsp->lock);
856
857 return size;
858}
859
860static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
861
7bba67ab
JN		 862static const struct attribute *additional_attrs[] = {
863 &dev_attr_max_tx_thres.attr,
864 &dev_attr_max_rx_thres.attr,
865 &dev_attr_dma_op_mode.attr,
866 NULL,
867};
868
869static const struct attribute_group additional_attr_group = {
870 .attrs = (struct attribute **)additional_attrs,
871};
872
d912fa92
EN		 873static ssize_t st_taps_show(struct device *dev,
874 struct device_attribute *attr, char *buf)
875{
876 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
877 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
878 ssize_t status = 0;
879 int i;
880
881 spin_lock_irq(&mcbsp->lock);
882 for (i = 0; i < st_data->nr_taps; i++)
883 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
884 st_data->taps[i]);
885 if (i)
886 status += sprintf(&buf[status], "\n");
887 spin_unlock_irq(&mcbsp->lock);
888
889 return status;
890}
891
892static ssize_t st_taps_store(struct device *dev,
893 struct device_attribute *attr,
894 const char *buf, size_t size)
895{
896 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
897 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
898 int val, tmp, status, i = 0;
899
900 spin_lock_irq(&mcbsp->lock);
901 memset(st_data->taps, 0, sizeof(st_data->taps));
902 st_data->nr_taps = 0;
903
904 do {
905 status = sscanf(buf, "%d%n", &val, &tmp);
906 if (status < 0 || status == 0) {
907 size = -EINVAL;
908 goto out;
909 }
910 if (val < -32768 || val > 32767) {
911 size = -EINVAL;
912 goto out;
913 }
914 st_data->taps[i++] = val;
915 buf += tmp;
916 if (*buf != ',')
917 break;
918 buf++;
919 } while (1);
920
921 st_data->nr_taps = i;
922
923out:
924 spin_unlock_irq(&mcbsp->lock);
925
926 return size;
927}
928
929static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
930
d912fa92
EN		 931static const struct attribute *sidetone_attrs[] = {
932 &dev_attr_st_taps.attr,
933 NULL,
934};
935
936static const struct attribute_group sidetone_attr_group = {
937 .attrs = (struct attribute **)sidetone_attrs,
938};
939
7ff60006 940static int omap_st_add(struct omap_mcbsp *mcbsp, struct resource *res)
d912fa92 941{
d912fa92
EN		 942 struct omap_mcbsp_st_data *st_data;
943 int err;
944
2ee65950
PU		 945 st_data = devm_kzalloc(mcbsp->dev, sizeof(*mcbsp->st_data), GFP_KERNEL);
946 if (!st_data)
947 return -ENOMEM;
d912fa92 948
2ee65950
PU		 949 st_data->io_base_st = devm_ioremap(mcbsp->dev, res->start,
950 resource_size(res));
951 if (!st_data->io_base_st)
952 return -ENOMEM;
d912fa92
EN		 953
954 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
955 if (err)
2ee65950 956 return err;
d912fa92
EN		 957
958 mcbsp->st_data = st_data;
959 return 0;
a1a56f5f 960}
a1a56f5f 961
5e1c5ff4
TL		 962/*
963 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
964 * 730 has only 2 McBSP, and both of them are MPU peripherals.
965 */
7ff60006 966int omap_mcbsp_init(struct platform_device *pdev)
bc5d0c89 967{
2ee65950 968 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
3cf32bba 969 struct resource *res;
bc5d0c89 970 int ret = 0;
5e1c5ff4 971
b4b58f58 972 spin_lock_init(&mcbsp->lock);
6722a723 973 mcbsp->free = true;
bc5d0c89 974
3cf32bba 975 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
5aec892a 976 if (!res)
3cf32bba 977 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5aec892a
AL		 978
979 mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
980 if (IS_ERR(mcbsp->io_base))
981 return PTR_ERR(mcbsp->io_base);
2ee65950 982
3cf32bba 983 mcbsp->phys_base = res->start;
ac6747ca 984 mcbsp->reg_cache_size = resource_size(res);
d592dd1a 985
3cf32bba
KVA		 986 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
987 if (!res)
988 mcbsp->phys_dma_base = mcbsp->phys_base;
989 else
990 mcbsp->phys_dma_base = res->start;
991
35d210fa
PU		 992 /*
993 * OMAP1, 2 uses two interrupt lines: TX, RX
994 * OMAP2430, OMAP3 SoC have combined IRQ line as well.
995 * OMAP4 and newer SoC only have the combined IRQ line.
996 * Use the combined IRQ if available since it gives better debugging
997 * possibilities.
998 */
999 mcbsp->irq = platform_get_irq_byname(pdev, "common");
1000 if (mcbsp->irq == -ENXIO) {
1001 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1002
1003 if (mcbsp->tx_irq == -ENXIO) {
1004 mcbsp->irq = platform_get_irq(pdev, 0);
1005 mcbsp->tx_irq = 0;
1006 } else {
1007 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1008 mcbsp->irq = 0;
1009 }
73c9522e 1010 }
cb7e9ded 1011
9ab1fac4
PU		 1012 if (!pdev->dev.of_node) {
1013 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1014 if (!res) {
1015 dev_err(&pdev->dev, "invalid tx DMA channel\n");
1016 return -ENODEV;
1017 }
1018 mcbsp->dma_req[0] = res->start;
1019 mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0];
3cf32bba 1020
9ab1fac4
PU		 1021 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1022 if (!res) {
1023 dev_err(&pdev->dev, "invalid rx DMA channel\n");
1024 return -ENODEV;
1025 }
1026 mcbsp->dma_req[1] = res->start;
1027 mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1];
1028 } else {
1029 mcbsp->dma_data[0].filter_data = "tx";
1030 mcbsp->dma_data[1].filter_data = "rx";
3cf32bba 1031 }
9ab1fac4 1032
09ae3aaf
LPC		 1033 mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp, 0);
1034 mcbsp->dma_data[0].maxburst = 4;
bc5d0c89 1035
9ab1fac4
PU		 1036 mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp, 1);
1037 mcbsp->dma_data[1].maxburst = 4;
1038
b820ce4e
RK		 1039 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1040 if (IS_ERR(mcbsp->fclk)) {
1041 ret = PTR_ERR(mcbsp->fclk);
2ee65950
PU		 1042 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
1043 return ret;
bc5d0c89
EV		 1044 }
1045
7bba67ab
JN		 1046 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1047 if (mcbsp->pdata->buffer_size) {
1048 /*
1049 * Initially configure the maximum thresholds to a safe value.
1050 * The McBSP FIFO usage with these values should not go under
1051 * 16 locations.
1052 * If the whole FIFO without safety buffer is used, than there
1053 * is a possibility that the DMA will be not able to push the
1054 * new data on time, causing channel shifts in runtime.
1055 */
1056 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1057 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1058
1059 ret = sysfs_create_group(&mcbsp->dev->kobj,
1060 &additional_attr_group);
1061 if (ret) {
1062 dev_err(mcbsp->dev,
1063 "Unable to create additional controls\n");
1064 goto err_thres;
1065 }
1066 } else {
1067 mcbsp->max_tx_thres = -EINVAL;
1068 mcbsp->max_rx_thres = -EINVAL;
1069 }
1070
f821eece
JN		 1071 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1072 if (res) {
1073 ret = omap_st_add(mcbsp, res);
1074 if (ret) {
1075 dev_err(mcbsp->dev,
1076 "Unable to create sidetone controls\n");
1077 goto err_st;
1078 }
1079 }
a1a56f5f 1080
d592dd1a 1081 return 0;
bc5d0c89 1082
f821eece
JN		 1083err_st:
1084 if (mcbsp->pdata->buffer_size)
2ee65950 1085 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
7bba67ab
JN		 1086err_thres:
1087 clk_put(mcbsp->fclk);
bc5d0c89
EV		 1088 return ret;
1089}
120db2cb 1090
7ff60006 1091void omap_mcbsp_sysfs_remove(struct omap_mcbsp *mcbsp)
5e1c5ff4 1092{
2ee65950
PU		 1093 if (mcbsp->pdata->buffer_size)
1094 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
5e1c5ff4 1095
2ee65950
PU		 1096 if (mcbsp->st_data)
1097 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
5e1c5ff4 1098}
Linux kernel - Deliverables
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