Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
71e822e9 | 2 | * sound/soc/omap/mcbsp.c |
5e1c5ff4 TL |
3 | * |
4 | * Copyright (C) 2004 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> | |
6 | * | |
71e822e9 PU |
7 | * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com> |
8 | * Peter Ujfalusi <peter.ujfalusi@ti.com> | |
5e1c5ff4 TL |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * Multichannel mode not supported. | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/device.h> | |
bc5d0c89 | 20 | #include <linux/platform_device.h> |
5e1c5ff4 TL |
21 | #include <linux/interrupt.h> |
22 | #include <linux/err.h> | |
f8ce2547 | 23 | #include <linux/clk.h> |
04fbf6a2 | 24 | #include <linux/delay.h> |
fb78d808 | 25 | #include <linux/io.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
f199131a | 27 | #include <linux/pm_runtime.h> |
5e1c5ff4 | 28 | |
2203747c | 29 | #include <linux/platform_data/asoc-ti-mcbsp.h> |
5e1c5ff4 | 30 | |
219f4316 PU |
31 | #include "mcbsp.h" |
32 | ||
b0a330dc | 33 | static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) |
b4b58f58 | 34 | { |
cdc71514 JN |
35 | void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step; |
36 | ||
37 | if (mcbsp->pdata->reg_size == 2) { | |
38 | ((u16 *)mcbsp->reg_cache)[reg] = (u16)val; | |
1b488a48 | 39 | writew_relaxed((u16)val, addr); |
c8c99699 | 40 | } else { |
cdc71514 | 41 | ((u32 *)mcbsp->reg_cache)[reg] = val; |
1b488a48 | 42 | writel_relaxed(val, addr); |
c8c99699 | 43 | } |
b4b58f58 CS |
44 | } |
45 | ||
b0a330dc | 46 | static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) |
b4b58f58 | 47 | { |
cdc71514 JN |
48 | void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step; |
49 | ||
50 | if (mcbsp->pdata->reg_size == 2) { | |
1b488a48 | 51 | return !from_cache ? readw_relaxed(addr) : |
cdc71514 | 52 | ((u16 *)mcbsp->reg_cache)[reg]; |
c8c99699 | 53 | } else { |
1b488a48 | 54 | return !from_cache ? readl_relaxed(addr) : |
cdc71514 | 55 | ((u32 *)mcbsp->reg_cache)[reg]; |
c8c99699 | 56 | } |
b4b58f58 CS |
57 | } |
58 | ||
b0a330dc | 59 | static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) |
d912fa92 | 60 | { |
1b488a48 | 61 | writel_relaxed(val, mcbsp->st_data->io_base_st + reg); |
d912fa92 EN |
62 | } |
63 | ||
b0a330dc | 64 | static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) |
d912fa92 | 65 | { |
1b488a48 | 66 | return readl_relaxed(mcbsp->st_data->io_base_st + reg); |
d912fa92 | 67 | } |
d912fa92 | 68 | |
8ea3200f | 69 | #define MCBSP_READ(mcbsp, reg) \ |
c8c99699 | 70 | omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0) |
8ea3200f JK |
71 | #define MCBSP_WRITE(mcbsp, reg, val) \ |
72 | omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val) | |
c8c99699 JK |
73 | #define MCBSP_READ_CACHE(mcbsp, reg) \ |
74 | omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1) | |
b4b58f58 | 75 | |
d912fa92 EN |
76 | #define MCBSP_ST_READ(mcbsp, reg) \ |
77 | omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg) | |
78 | #define MCBSP_ST_WRITE(mcbsp, reg, val) \ | |
79 | omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val) | |
80 | ||
45656b44 | 81 | static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp) |
5e1c5ff4 | 82 | { |
b4b58f58 CS |
83 | dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id); |
84 | dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", | |
8ea3200f | 85 | MCBSP_READ(mcbsp, DRR2)); |
b4b58f58 | 86 | dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", |
8ea3200f | 87 | MCBSP_READ(mcbsp, DRR1)); |
b4b58f58 | 88 | dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", |
8ea3200f | 89 | MCBSP_READ(mcbsp, DXR2)); |
b4b58f58 | 90 | dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", |
8ea3200f | 91 | MCBSP_READ(mcbsp, DXR1)); |
b4b58f58 | 92 | dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", |
8ea3200f | 93 | MCBSP_READ(mcbsp, SPCR2)); |
b4b58f58 | 94 | dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", |
8ea3200f | 95 | MCBSP_READ(mcbsp, SPCR1)); |
b4b58f58 | 96 | dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", |
8ea3200f | 97 | MCBSP_READ(mcbsp, RCR2)); |
b4b58f58 | 98 | dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", |
8ea3200f | 99 | MCBSP_READ(mcbsp, RCR1)); |
b4b58f58 | 100 | dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", |
8ea3200f | 101 | MCBSP_READ(mcbsp, XCR2)); |
b4b58f58 | 102 | dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", |
8ea3200f | 103 | MCBSP_READ(mcbsp, XCR1)); |
b4b58f58 | 104 | dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", |
8ea3200f | 105 | MCBSP_READ(mcbsp, SRGR2)); |
b4b58f58 | 106 | dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", |
8ea3200f | 107 | MCBSP_READ(mcbsp, SRGR1)); |
b4b58f58 | 108 | dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", |
8ea3200f | 109 | MCBSP_READ(mcbsp, PCR0)); |
b4b58f58 | 110 | dev_dbg(mcbsp->dev, "***********************\n"); |
5e1c5ff4 TL |
111 | } |
112 | ||
35d210fa PU |
113 | static irqreturn_t omap_mcbsp_irq_handler(int irq, void *dev_id) |
114 | { | |
115 | struct omap_mcbsp *mcbsp = dev_id; | |
116 | u16 irqst; | |
117 | ||
118 | irqst = MCBSP_READ(mcbsp, IRQST); | |
119 | dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst); | |
120 | ||
121 | if (irqst & RSYNCERREN) | |
122 | dev_err(mcbsp->dev, "RX Frame Sync Error!\n"); | |
123 | if (irqst & RFSREN) | |
124 | dev_dbg(mcbsp->dev, "RX Frame Sync\n"); | |
125 | if (irqst & REOFEN) | |
126 | dev_dbg(mcbsp->dev, "RX End Of Frame\n"); | |
127 | if (irqst & RRDYEN) | |
128 | dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n"); | |
129 | if (irqst & RUNDFLEN) | |
130 | dev_err(mcbsp->dev, "RX Buffer Underflow!\n"); | |
131 | if (irqst & ROVFLEN) | |
132 | dev_err(mcbsp->dev, "RX Buffer Overflow!\n"); | |
133 | ||
134 | if (irqst & XSYNCERREN) | |
135 | dev_err(mcbsp->dev, "TX Frame Sync Error!\n"); | |
136 | if (irqst & XFSXEN) | |
137 | dev_dbg(mcbsp->dev, "TX Frame Sync\n"); | |
138 | if (irqst & XEOFEN) | |
139 | dev_dbg(mcbsp->dev, "TX End Of Frame\n"); | |
140 | if (irqst & XRDYEN) | |
141 | dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n"); | |
142 | if (irqst & XUNDFLEN) | |
143 | dev_err(mcbsp->dev, "TX Buffer Underflow!\n"); | |
144 | if (irqst & XOVFLEN) | |
145 | dev_err(mcbsp->dev, "TX Buffer Overflow!\n"); | |
146 | if (irqst & XEMPTYEOFEN) | |
147 | dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n"); | |
148 | ||
149 | MCBSP_WRITE(mcbsp, IRQST, irqst); | |
150 | ||
151 | return IRQ_HANDLED; | |
152 | } | |
153 | ||
0cd61b68 | 154 | static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id) |
5e1c5ff4 | 155 | { |
e8f2af17 | 156 | struct omap_mcbsp *mcbsp_tx = dev_id; |
d6d834b0 | 157 | u16 irqst_spcr2; |
5e1c5ff4 | 158 | |
8ea3200f | 159 | irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2); |
d6d834b0 | 160 | dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2); |
5e1c5ff4 | 161 | |
d6d834b0 EN |
162 | if (irqst_spcr2 & XSYNC_ERR) { |
163 | dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n", | |
164 | irqst_spcr2); | |
165 | /* Writing zero to XSYNC_ERR clears the IRQ */ | |
0841cb82 | 166 | MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2)); |
d6d834b0 | 167 | } |
fb78d808 | 168 | |
5e1c5ff4 TL |
169 | return IRQ_HANDLED; |
170 | } | |
171 | ||
0cd61b68 | 172 | static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id) |
5e1c5ff4 | 173 | { |
e8f2af17 | 174 | struct omap_mcbsp *mcbsp_rx = dev_id; |
d6d834b0 EN |
175 | u16 irqst_spcr1; |
176 | ||
8ea3200f | 177 | irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1); |
d6d834b0 EN |
178 | dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1); |
179 | ||
180 | if (irqst_spcr1 & RSYNC_ERR) { | |
181 | dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n", | |
182 | irqst_spcr1); | |
183 | /* Writing zero to RSYNC_ERR clears the IRQ */ | |
0841cb82 | 184 | MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1)); |
d6d834b0 | 185 | } |
fb78d808 | 186 | |
5e1c5ff4 TL |
187 | return IRQ_HANDLED; |
188 | } | |
189 | ||
5e1c5ff4 TL |
190 | /* |
191 | * omap_mcbsp_config simply write a config to the | |
192 | * appropriate McBSP. | |
193 | * You either call this function or set the McBSP registers | |
194 | * by yourself before calling omap_mcbsp_start(). | |
195 | */ | |
45656b44 PU |
196 | void omap_mcbsp_config(struct omap_mcbsp *mcbsp, |
197 | const struct omap_mcbsp_reg_cfg *config) | |
5e1c5ff4 | 198 | { |
b4b58f58 CS |
199 | dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n", |
200 | mcbsp->id, mcbsp->phys_base); | |
5e1c5ff4 TL |
201 | |
202 | /* We write the given config */ | |
8ea3200f JK |
203 | MCBSP_WRITE(mcbsp, SPCR2, config->spcr2); |
204 | MCBSP_WRITE(mcbsp, SPCR1, config->spcr1); | |
205 | MCBSP_WRITE(mcbsp, RCR2, config->rcr2); | |
206 | MCBSP_WRITE(mcbsp, RCR1, config->rcr1); | |
207 | MCBSP_WRITE(mcbsp, XCR2, config->xcr2); | |
208 | MCBSP_WRITE(mcbsp, XCR1, config->xcr1); | |
209 | MCBSP_WRITE(mcbsp, SRGR2, config->srgr2); | |
210 | MCBSP_WRITE(mcbsp, SRGR1, config->srgr1); | |
211 | MCBSP_WRITE(mcbsp, MCR2, config->mcr2); | |
212 | MCBSP_WRITE(mcbsp, MCR1, config->mcr1); | |
213 | MCBSP_WRITE(mcbsp, PCR0, config->pcr0); | |
88408230 | 214 | if (mcbsp->pdata->has_ccr) { |
8ea3200f JK |
215 | MCBSP_WRITE(mcbsp, XCCR, config->xccr); |
216 | MCBSP_WRITE(mcbsp, RCCR, config->rccr); | |
3127f8f8 | 217 | } |
08905d8a PU |
218 | /* Enable wakeup behavior */ |
219 | if (mcbsp->pdata->has_wakeup) | |
220 | MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN); | |
35d210fa PU |
221 | |
222 | /* Enable TX/RX sync error interrupts by default */ | |
223 | if (mcbsp->irq) | |
224 | MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN); | |
5e1c5ff4 | 225 | } |
5e1c5ff4 | 226 | |
9504ba64 KVA |
227 | /** |
228 | * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register | |
229 | * @id - mcbsp id | |
230 | * @stream - indicates the direction of data flow (rx or tx) | |
231 | * | |
232 | * Returns the address of mcbsp data transmit register or data receive register | |
233 | * to be used by DMA for transferring/receiving data based on the value of | |
234 | * @stream for the requested mcbsp given by @id | |
235 | */ | |
b8fb4907 PU |
236 | static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp, |
237 | unsigned int stream) | |
9504ba64 | 238 | { |
9504ba64 KVA |
239 | int data_reg; |
240 | ||
cdc71514 | 241 | if (mcbsp->pdata->reg_size == 2) { |
9504ba64 | 242 | if (stream) |
cdc71514 | 243 | data_reg = OMAP_MCBSP_REG_DRR1; |
9504ba64 | 244 | else |
cdc71514 | 245 | data_reg = OMAP_MCBSP_REG_DXR1; |
9504ba64 KVA |
246 | } else { |
247 | if (stream) | |
cdc71514 | 248 | data_reg = OMAP_MCBSP_REG_DRR; |
9504ba64 | 249 | else |
cdc71514 | 250 | data_reg = OMAP_MCBSP_REG_DXR; |
9504ba64 KVA |
251 | } |
252 | ||
cdc71514 | 253 | return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step; |
9504ba64 | 254 | } |
9504ba64 | 255 | |
d912fa92 EN |
256 | static void omap_st_on(struct omap_mcbsp *mcbsp) |
257 | { | |
258 | unsigned int w; | |
259 | ||
1743d14f JN |
260 | if (mcbsp->pdata->enable_st_clock) |
261 | mcbsp->pdata->enable_st_clock(mcbsp->id, 1); | |
d912fa92 EN |
262 | |
263 | /* Enable McBSP Sidetone */ | |
264 | w = MCBSP_READ(mcbsp, SSELCR); | |
265 | MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN); | |
266 | ||
d912fa92 EN |
267 | /* Enable Sidetone from Sidetone Core */ |
268 | w = MCBSP_ST_READ(mcbsp, SSELCR); | |
269 | MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN); | |
270 | } | |
271 | ||
272 | static void omap_st_off(struct omap_mcbsp *mcbsp) | |
273 | { | |
274 | unsigned int w; | |
275 | ||
276 | w = MCBSP_ST_READ(mcbsp, SSELCR); | |
277 | MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN)); | |
278 | ||
d912fa92 EN |
279 | w = MCBSP_READ(mcbsp, SSELCR); |
280 | MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); | |
281 | ||
1743d14f JN |
282 | if (mcbsp->pdata->enable_st_clock) |
283 | mcbsp->pdata->enable_st_clock(mcbsp->id, 0); | |
d912fa92 EN |
284 | } |
285 | ||
286 | static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) | |
287 | { | |
288 | u16 val, i; | |
d912fa92 EN |
289 | |
290 | val = MCBSP_ST_READ(mcbsp, SSELCR); | |
291 | ||
292 | if (val & ST_COEFFWREN) | |
293 | MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN)); | |
294 | ||
295 | MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN); | |
296 | ||
297 | for (i = 0; i < 128; i++) | |
298 | MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]); | |
299 | ||
300 | i = 0; | |
301 | ||
302 | val = MCBSP_ST_READ(mcbsp, SSELCR); | |
303 | while (!(val & ST_COEFFWRDONE) && (++i < 1000)) | |
304 | val = MCBSP_ST_READ(mcbsp, SSELCR); | |
305 | ||
306 | MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN)); | |
307 | ||
308 | if (i == 1000) | |
309 | dev_err(mcbsp->dev, "McBSP FIR load error!\n"); | |
310 | } | |
311 | ||
312 | static void omap_st_chgain(struct omap_mcbsp *mcbsp) | |
313 | { | |
314 | u16 w; | |
315 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | |
d912fa92 EN |
316 | |
317 | w = MCBSP_ST_READ(mcbsp, SSELCR); | |
318 | ||
319 | MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \ | |
320 | ST_CH1GAIN(st_data->ch1gain)); | |
321 | } | |
322 | ||
45656b44 | 323 | int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain) |
d912fa92 | 324 | { |
e2002ab3 | 325 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; |
d912fa92 EN |
326 | int ret = 0; |
327 | ||
d912fa92 EN |
328 | if (!st_data) |
329 | return -ENOENT; | |
330 | ||
331 | spin_lock_irq(&mcbsp->lock); | |
332 | if (channel == 0) | |
333 | st_data->ch0gain = chgain; | |
334 | else if (channel == 1) | |
335 | st_data->ch1gain = chgain; | |
336 | else | |
337 | ret = -EINVAL; | |
338 | ||
339 | if (st_data->enabled) | |
340 | omap_st_chgain(mcbsp); | |
341 | spin_unlock_irq(&mcbsp->lock); | |
342 | ||
343 | return ret; | |
344 | } | |
d912fa92 | 345 | |
45656b44 | 346 | int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain) |
d912fa92 | 347 | { |
e2002ab3 | 348 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; |
d912fa92 EN |
349 | int ret = 0; |
350 | ||
d912fa92 EN |
351 | if (!st_data) |
352 | return -ENOENT; | |
353 | ||
354 | spin_lock_irq(&mcbsp->lock); | |
355 | if (channel == 0) | |
356 | *chgain = st_data->ch0gain; | |
357 | else if (channel == 1) | |
358 | *chgain = st_data->ch1gain; | |
359 | else | |
360 | ret = -EINVAL; | |
361 | spin_unlock_irq(&mcbsp->lock); | |
362 | ||
363 | return ret; | |
364 | } | |
d912fa92 EN |
365 | |
366 | static int omap_st_start(struct omap_mcbsp *mcbsp) | |
367 | { | |
368 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | |
369 | ||
58db1dcd | 370 | if (st_data->enabled && !st_data->running) { |
d912fa92 EN |
371 | omap_st_fir_write(mcbsp, st_data->taps); |
372 | omap_st_chgain(mcbsp); | |
373 | ||
374 | if (!mcbsp->free) { | |
375 | omap_st_on(mcbsp); | |
376 | st_data->running = 1; | |
377 | } | |
378 | } | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
45656b44 | 383 | int omap_st_enable(struct omap_mcbsp *mcbsp) |
d912fa92 | 384 | { |
e2002ab3 | 385 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; |
d912fa92 EN |
386 | |
387 | if (!st_data) | |
388 | return -ENODEV; | |
389 | ||
390 | spin_lock_irq(&mcbsp->lock); | |
391 | st_data->enabled = 1; | |
392 | omap_st_start(mcbsp); | |
393 | spin_unlock_irq(&mcbsp->lock); | |
394 | ||
395 | return 0; | |
396 | } | |
d912fa92 EN |
397 | |
398 | static int omap_st_stop(struct omap_mcbsp *mcbsp) | |
399 | { | |
400 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | |
401 | ||
58db1dcd | 402 | if (st_data->running) { |
d912fa92 EN |
403 | if (!mcbsp->free) { |
404 | omap_st_off(mcbsp); | |
405 | st_data->running = 0; | |
406 | } | |
407 | } | |
408 | ||
409 | return 0; | |
410 | } | |
411 | ||
45656b44 | 412 | int omap_st_disable(struct omap_mcbsp *mcbsp) |
d912fa92 | 413 | { |
e2002ab3 | 414 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; |
d912fa92 EN |
415 | int ret = 0; |
416 | ||
d912fa92 EN |
417 | if (!st_data) |
418 | return -ENODEV; | |
419 | ||
420 | spin_lock_irq(&mcbsp->lock); | |
421 | omap_st_stop(mcbsp); | |
422 | st_data->enabled = 0; | |
423 | spin_unlock_irq(&mcbsp->lock); | |
424 | ||
425 | return ret; | |
426 | } | |
d912fa92 | 427 | |
45656b44 | 428 | int omap_st_is_enabled(struct omap_mcbsp *mcbsp) |
d912fa92 | 429 | { |
e2002ab3 | 430 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; |
d912fa92 EN |
431 | |
432 | if (!st_data) | |
433 | return -ENODEV; | |
434 | ||
d912fa92 EN |
435 | return st_data->enabled; |
436 | } | |
d912fa92 | 437 | |
7aa9ff56 | 438 | /* |
451fd82d PU |
439 | * omap_mcbsp_set_rx_threshold configures the transmit threshold in words. |
440 | * The threshold parameter is 1 based, and it is converted (threshold - 1) | |
441 | * for the THRSH2 register. | |
7aa9ff56 | 442 | */ |
45656b44 | 443 | void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold) |
7aa9ff56 | 444 | { |
7bba67ab JN |
445 | if (mcbsp->pdata->buffer_size == 0) |
446 | return; | |
7aa9ff56 | 447 | |
451fd82d PU |
448 | if (threshold && threshold <= mcbsp->max_tx_thres) |
449 | MCBSP_WRITE(mcbsp, THRSH2, threshold - 1); | |
7aa9ff56 | 450 | } |
7aa9ff56 EV |
451 | |
452 | /* | |
451fd82d PU |
453 | * omap_mcbsp_set_rx_threshold configures the receive threshold in words. |
454 | * The threshold parameter is 1 based, and it is converted (threshold - 1) | |
455 | * for the THRSH1 register. | |
7aa9ff56 | 456 | */ |
45656b44 | 457 | void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold) |
7aa9ff56 | 458 | { |
7bba67ab JN |
459 | if (mcbsp->pdata->buffer_size == 0) |
460 | return; | |
7aa9ff56 | 461 | |
451fd82d PU |
462 | if (threshold && threshold <= mcbsp->max_rx_thres) |
463 | MCBSP_WRITE(mcbsp, THRSH1, threshold - 1); | |
7aa9ff56 | 464 | } |
a1a56f5f | 465 | |
7dc976ed PU |
466 | /* |
467 | * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO | |
468 | */ | |
45656b44 | 469 | u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp) |
7dc976ed | 470 | { |
7dc976ed PU |
471 | u16 buffstat; |
472 | ||
7bba67ab JN |
473 | if (mcbsp->pdata->buffer_size == 0) |
474 | return 0; | |
7dc976ed PU |
475 | |
476 | /* Returns the number of free locations in the buffer */ | |
477 | buffstat = MCBSP_READ(mcbsp, XBUFFSTAT); | |
478 | ||
479 | /* Number of slots are different in McBSP ports */ | |
f10b8ad1 | 480 | return mcbsp->pdata->buffer_size - buffstat; |
7dc976ed | 481 | } |
7dc976ed PU |
482 | |
483 | /* | |
484 | * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO | |
485 | * to reach the threshold value (when the DMA will be triggered to read it) | |
486 | */ | |
45656b44 | 487 | u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp) |
7dc976ed | 488 | { |
7dc976ed PU |
489 | u16 buffstat, threshold; |
490 | ||
7bba67ab JN |
491 | if (mcbsp->pdata->buffer_size == 0) |
492 | return 0; | |
7dc976ed PU |
493 | |
494 | /* Returns the number of used locations in the buffer */ | |
495 | buffstat = MCBSP_READ(mcbsp, RBUFFSTAT); | |
496 | /* RX threshold */ | |
497 | threshold = MCBSP_READ(mcbsp, THRSH1); | |
498 | ||
499 | /* Return the number of location till we reach the threshold limit */ | |
500 | if (threshold <= buffstat) | |
501 | return 0; | |
502 | else | |
503 | return threshold - buffstat; | |
504 | } | |
7dc976ed | 505 | |
45656b44 | 506 | int omap_mcbsp_request(struct omap_mcbsp *mcbsp) |
5e1c5ff4 | 507 | { |
c8c99699 | 508 | void *reg_cache; |
5e1c5ff4 TL |
509 | int err; |
510 | ||
ac6747ca | 511 | reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL); |
c8c99699 JK |
512 | if (!reg_cache) { |
513 | return -ENOMEM; | |
514 | } | |
515 | ||
b4b58f58 CS |
516 | spin_lock(&mcbsp->lock); |
517 | if (!mcbsp->free) { | |
518 | dev_err(mcbsp->dev, "McBSP%d is currently in use\n", | |
519 | mcbsp->id); | |
c8c99699 JK |
520 | err = -EBUSY; |
521 | goto err_kfree; | |
5e1c5ff4 TL |
522 | } |
523 | ||
6722a723 | 524 | mcbsp->free = false; |
c8c99699 | 525 | mcbsp->reg_cache = reg_cache; |
b4b58f58 | 526 | spin_unlock(&mcbsp->lock); |
5e1c5ff4 | 527 | |
b820ce4e | 528 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) |
45656b44 | 529 | mcbsp->pdata->ops->request(mcbsp->id - 1); |
b820ce4e | 530 | |
5a07055a JN |
531 | /* |
532 | * Make sure that transmitter, receiver and sample-rate generator are | |
533 | * not running before activating IRQs. | |
534 | */ | |
8ea3200f JK |
535 | MCBSP_WRITE(mcbsp, SPCR1, 0); |
536 | MCBSP_WRITE(mcbsp, SPCR2, 0); | |
5a07055a | 537 | |
35d210fa PU |
538 | if (mcbsp->irq) { |
539 | err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0, | |
540 | "McBSP", (void *)mcbsp); | |
541 | if (err != 0) { | |
542 | dev_err(mcbsp->dev, "Unable to request IRQ\n"); | |
543 | goto err_clk_disable; | |
544 | } | |
545 | } else { | |
546 | err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0, | |
547 | "McBSP TX", (void *)mcbsp); | |
548 | if (err != 0) { | |
549 | dev_err(mcbsp->dev, "Unable to request TX IRQ\n"); | |
550 | goto err_clk_disable; | |
551 | } | |
bafe2721 | 552 | |
35d210fa PU |
553 | err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0, |
554 | "McBSP RX", (void *)mcbsp); | |
120db2cb | 555 | if (err != 0) { |
35d210fa | 556 | dev_err(mcbsp->dev, "Unable to request RX IRQ\n"); |
bafe2721 | 557 | goto err_free_irq; |
120db2cb | 558 | } |
5e1c5ff4 TL |
559 | } |
560 | ||
5e1c5ff4 | 561 | return 0; |
c8c99699 | 562 | err_free_irq: |
1866b545 | 563 | free_irq(mcbsp->tx_irq, (void *)mcbsp); |
c8c99699 | 564 | err_clk_disable: |
1866b545 | 565 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) |
45656b44 | 566 | mcbsp->pdata->ops->free(mcbsp->id - 1); |
1866b545 | 567 | |
1a645884 JN |
568 | /* Disable wakeup behavior */ |
569 | if (mcbsp->pdata->has_wakeup) | |
570 | MCBSP_WRITE(mcbsp, WAKEUPEN, 0); | |
1866b545 | 571 | |
c8c99699 | 572 | spin_lock(&mcbsp->lock); |
6722a723 | 573 | mcbsp->free = true; |
c8c99699 JK |
574 | mcbsp->reg_cache = NULL; |
575 | err_kfree: | |
576 | spin_unlock(&mcbsp->lock); | |
577 | kfree(reg_cache); | |
1866b545 JK |
578 | |
579 | return err; | |
5e1c5ff4 TL |
580 | } |
581 | ||
45656b44 | 582 | void omap_mcbsp_free(struct omap_mcbsp *mcbsp) |
5e1c5ff4 | 583 | { |
c8c99699 | 584 | void *reg_cache; |
b4b58f58 | 585 | |
b4b58f58 | 586 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) |
45656b44 | 587 | mcbsp->pdata->ops->free(mcbsp->id - 1); |
bc5d0c89 | 588 | |
1a645884 JN |
589 | /* Disable wakeup behavior */ |
590 | if (mcbsp->pdata->has_wakeup) | |
591 | MCBSP_WRITE(mcbsp, WAKEUPEN, 0); | |
2122fdc6 | 592 | |
35d210fa PU |
593 | /* Disable interrupt requests */ |
594 | if (mcbsp->irq) | |
595 | MCBSP_WRITE(mcbsp, IRQEN, 0); | |
596 | ||
597 | if (mcbsp->irq) { | |
598 | free_irq(mcbsp->irq, (void *)mcbsp); | |
599 | } else { | |
bafe2721 | 600 | free_irq(mcbsp->rx_irq, (void *)mcbsp); |
35d210fa PU |
601 | free_irq(mcbsp->tx_irq, (void *)mcbsp); |
602 | } | |
5e1c5ff4 | 603 | |
c8c99699 | 604 | reg_cache = mcbsp->reg_cache; |
5e1c5ff4 | 605 | |
e386615c PU |
606 | /* |
607 | * Select CLKS source from internal source unconditionally before | |
608 | * marking the McBSP port as free. | |
609 | * If the external clock source via MCBSP_CLKS pin has been selected the | |
610 | * system will refuse to enter idle if the CLKS pin source is not reset | |
611 | * back to internal source. | |
612 | */ | |
e650794a | 613 | if (!mcbsp_omap1()) |
e386615c PU |
614 | omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC); |
615 | ||
c8c99699 JK |
616 | spin_lock(&mcbsp->lock); |
617 | if (mcbsp->free) | |
618 | dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id); | |
619 | else | |
6722a723 | 620 | mcbsp->free = true; |
c8c99699 | 621 | mcbsp->reg_cache = NULL; |
b4b58f58 | 622 | spin_unlock(&mcbsp->lock); |
c8c99699 | 623 | |
bb66f2dc | 624 | kfree(reg_cache); |
5e1c5ff4 TL |
625 | } |
626 | ||
627 | /* | |
c12abc01 JN |
628 | * Here we start the McBSP, by enabling transmitter, receiver or both. |
629 | * If no transmitter or receiver is active prior calling, then sample-rate | |
630 | * generator and frame sync are started. | |
5e1c5ff4 | 631 | */ |
45656b44 | 632 | void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx) |
5e1c5ff4 | 633 | { |
ce3f054b | 634 | int enable_srg = 0; |
5e1c5ff4 TL |
635 | u16 w; |
636 | ||
f821eece | 637 | if (mcbsp->st_data) |
d912fa92 EN |
638 | omap_st_start(mcbsp); |
639 | ||
ce3f054b PU |
640 | /* Only enable SRG, if McBSP is master */ |
641 | w = MCBSP_READ_CACHE(mcbsp, PCR0); | |
642 | if (w & (FSXM | FSRM | CLKXM | CLKRM)) | |
643 | enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | | |
644 | MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); | |
c12abc01 | 645 | |
ce3f054b | 646 | if (enable_srg) { |
c12abc01 | 647 | /* Start the sample generator */ |
96fbd745 | 648 | w = MCBSP_READ_CACHE(mcbsp, SPCR2); |
8ea3200f | 649 | MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); |
c12abc01 | 650 | } |
5e1c5ff4 TL |
651 | |
652 | /* Enable transmitter and receiver */ | |
d09a2afc | 653 | tx &= 1; |
96fbd745 | 654 | w = MCBSP_READ_CACHE(mcbsp, SPCR2); |
8ea3200f | 655 | MCBSP_WRITE(mcbsp, SPCR2, w | tx); |
5e1c5ff4 | 656 | |
d09a2afc | 657 | rx &= 1; |
96fbd745 | 658 | w = MCBSP_READ_CACHE(mcbsp, SPCR1); |
8ea3200f | 659 | MCBSP_WRITE(mcbsp, SPCR1, w | rx); |
5e1c5ff4 | 660 | |
44a6311c EV |
661 | /* |
662 | * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec | |
663 | * REVISIT: 100us may give enough time for two CLKSRG, however | |
664 | * due to some unknown PM related, clock gating etc. reason it | |
665 | * is now at 500us. | |
666 | */ | |
667 | udelay(500); | |
5e1c5ff4 | 668 | |
ce3f054b | 669 | if (enable_srg) { |
c12abc01 | 670 | /* Start frame sync */ |
96fbd745 | 671 | w = MCBSP_READ_CACHE(mcbsp, SPCR2); |
8ea3200f | 672 | MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); |
c12abc01 | 673 | } |
5e1c5ff4 | 674 | |
88408230 | 675 | if (mcbsp->pdata->has_ccr) { |
d09a2afc | 676 | /* Release the transmitter and receiver */ |
96fbd745 | 677 | w = MCBSP_READ_CACHE(mcbsp, XCCR); |
d09a2afc | 678 | w &= ~(tx ? XDISABLE : 0); |
8ea3200f | 679 | MCBSP_WRITE(mcbsp, XCCR, w); |
96fbd745 | 680 | w = MCBSP_READ_CACHE(mcbsp, RCCR); |
d09a2afc | 681 | w &= ~(rx ? RDISABLE : 0); |
8ea3200f | 682 | MCBSP_WRITE(mcbsp, RCCR, w); |
d09a2afc JN |
683 | } |
684 | ||
5e1c5ff4 | 685 | /* Dump McBSP Regs */ |
45656b44 | 686 | omap_mcbsp_dump_reg(mcbsp); |
5e1c5ff4 TL |
687 | } |
688 | ||
45656b44 | 689 | void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx) |
5e1c5ff4 | 690 | { |
c12abc01 | 691 | int idle; |
5e1c5ff4 TL |
692 | u16 w; |
693 | ||
fb78d808 | 694 | /* Reset transmitter */ |
d09a2afc | 695 | tx &= 1; |
88408230 | 696 | if (mcbsp->pdata->has_ccr) { |
96fbd745 | 697 | w = MCBSP_READ_CACHE(mcbsp, XCCR); |
d09a2afc | 698 | w |= (tx ? XDISABLE : 0); |
8ea3200f | 699 | MCBSP_WRITE(mcbsp, XCCR, w); |
d09a2afc | 700 | } |
96fbd745 | 701 | w = MCBSP_READ_CACHE(mcbsp, SPCR2); |
8ea3200f | 702 | MCBSP_WRITE(mcbsp, SPCR2, w & ~tx); |
5e1c5ff4 TL |
703 | |
704 | /* Reset receiver */ | |
d09a2afc | 705 | rx &= 1; |
88408230 | 706 | if (mcbsp->pdata->has_ccr) { |
96fbd745 | 707 | w = MCBSP_READ_CACHE(mcbsp, RCCR); |
a93d4ed2 | 708 | w |= (rx ? RDISABLE : 0); |
8ea3200f | 709 | MCBSP_WRITE(mcbsp, RCCR, w); |
d09a2afc | 710 | } |
96fbd745 | 711 | w = MCBSP_READ_CACHE(mcbsp, SPCR1); |
8ea3200f | 712 | MCBSP_WRITE(mcbsp, SPCR1, w & ~rx); |
5e1c5ff4 | 713 | |
96fbd745 JK |
714 | idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | |
715 | MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); | |
c12abc01 JN |
716 | |
717 | if (idle) { | |
718 | /* Reset the sample rate generator */ | |
96fbd745 | 719 | w = MCBSP_READ_CACHE(mcbsp, SPCR2); |
8ea3200f | 720 | MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6)); |
c12abc01 | 721 | } |
d912fa92 | 722 | |
f821eece | 723 | if (mcbsp->st_data) |
d912fa92 | 724 | omap_st_stop(mcbsp); |
5e1c5ff4 | 725 | } |
5e1c5ff4 | 726 | |
45656b44 | 727 | int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id) |
69d042d1 | 728 | { |
f199131a | 729 | struct clk *fck_src; |
09d28d2c | 730 | const char *src; |
f199131a | 731 | int r; |
09d28d2c | 732 | |
09d28d2c | 733 | if (fck_src_id == MCBSP_CLKS_PAD_SRC) |
f199131a | 734 | src = "pad_fck"; |
09d28d2c | 735 | else if (fck_src_id == MCBSP_CLKS_PRCM_SRC) |
f199131a | 736 | src = "prcm_fck"; |
09d28d2c JN |
737 | else |
738 | return -EINVAL; | |
739 | ||
f199131a PU |
740 | fck_src = clk_get(mcbsp->dev, src); |
741 | if (IS_ERR(fck_src)) { | |
742 | dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src); | |
09d28d2c | 743 | return -EINVAL; |
f199131a | 744 | } |
5788c62e | 745 | |
f199131a | 746 | pm_runtime_put_sync(mcbsp->dev); |
45656b44 | 747 | |
f199131a PU |
748 | r = clk_set_parent(mcbsp->fclk, fck_src); |
749 | if (r) { | |
750 | dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n", | |
751 | src); | |
752 | clk_put(fck_src); | |
753 | return r; | |
cd1f08c7 | 754 | } |
7bc0c4ba | 755 | |
f199131a PU |
756 | pm_runtime_get_sync(mcbsp->dev); |
757 | ||
758 | clk_put(fck_src); | |
759 | ||
760 | return 0; | |
761 | ||
69d042d1 | 762 | } |
69d042d1 | 763 | |
a1a56f5f EV |
764 | #define max_thres(m) (mcbsp->pdata->buffer_size) |
765 | #define valid_threshold(m, val) ((val) <= max_thres(m)) | |
766 | #define THRESHOLD_PROP_BUILDER(prop) \ | |
767 | static ssize_t prop##_show(struct device *dev, \ | |
768 | struct device_attribute *attr, char *buf) \ | |
769 | { \ | |
770 | struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \ | |
771 | \ | |
772 | return sprintf(buf, "%u\n", mcbsp->prop); \ | |
773 | } \ | |
774 | \ | |
775 | static ssize_t prop##_store(struct device *dev, \ | |
776 | struct device_attribute *attr, \ | |
777 | const char *buf, size_t size) \ | |
778 | { \ | |
779 | struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \ | |
780 | unsigned long val; \ | |
781 | int status; \ | |
782 | \ | |
b785a492 | 783 | status = kstrtoul(buf, 0, &val); \ |
a1a56f5f EV |
784 | if (status) \ |
785 | return status; \ | |
786 | \ | |
787 | if (!valid_threshold(mcbsp, val)) \ | |
788 | return -EDOM; \ | |
789 | \ | |
790 | mcbsp->prop = val; \ | |
791 | return size; \ | |
792 | } \ | |
793 | \ | |
794 | static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store); | |
795 | ||
796 | THRESHOLD_PROP_BUILDER(max_tx_thres); | |
797 | THRESHOLD_PROP_BUILDER(max_rx_thres); | |
798 | ||
9b300509 | 799 | static const char *dma_op_modes[] = { |
09fa37ac | 800 | "element", "threshold", |
9b300509 JN |
801 | }; |
802 | ||
98cb20e8 PU |
803 | static ssize_t dma_op_mode_show(struct device *dev, |
804 | struct device_attribute *attr, char *buf) | |
805 | { | |
806 | struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); | |
9b300509 JN |
807 | int dma_op_mode, i = 0; |
808 | ssize_t len = 0; | |
809 | const char * const *s; | |
98cb20e8 | 810 | |
98cb20e8 | 811 | dma_op_mode = mcbsp->dma_op_mode; |
98cb20e8 | 812 | |
9b300509 JN |
813 | for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) { |
814 | if (dma_op_mode == i) | |
815 | len += sprintf(buf + len, "[%s] ", *s); | |
816 | else | |
817 | len += sprintf(buf + len, "%s ", *s); | |
818 | } | |
819 | len += sprintf(buf + len, "\n"); | |
820 | ||
821 | return len; | |
98cb20e8 PU |
822 | } |
823 | ||
824 | static ssize_t dma_op_mode_store(struct device *dev, | |
825 | struct device_attribute *attr, | |
826 | const char *buf, size_t size) | |
827 | { | |
828 | struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); | |
9b300509 JN |
829 | const char * const *s; |
830 | int i = 0; | |
98cb20e8 | 831 | |
9b300509 JN |
832 | for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) |
833 | if (sysfs_streq(buf, *s)) | |
834 | break; | |
98cb20e8 | 835 | |
9b300509 JN |
836 | if (i == ARRAY_SIZE(dma_op_modes)) |
837 | return -EINVAL; | |
98cb20e8 | 838 | |
9b300509 | 839 | spin_lock_irq(&mcbsp->lock); |
98cb20e8 PU |
840 | if (!mcbsp->free) { |
841 | size = -EBUSY; | |
842 | goto unlock; | |
843 | } | |
9b300509 | 844 | mcbsp->dma_op_mode = i; |
98cb20e8 PU |
845 | |
846 | unlock: | |
847 | spin_unlock_irq(&mcbsp->lock); | |
848 | ||
849 | return size; | |
850 | } | |
851 | ||
852 | static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store); | |
853 | ||
7bba67ab JN |
854 | static const struct attribute *additional_attrs[] = { |
855 | &dev_attr_max_tx_thres.attr, | |
856 | &dev_attr_max_rx_thres.attr, | |
857 | &dev_attr_dma_op_mode.attr, | |
858 | NULL, | |
859 | }; | |
860 | ||
861 | static const struct attribute_group additional_attr_group = { | |
862 | .attrs = (struct attribute **)additional_attrs, | |
863 | }; | |
864 | ||
d912fa92 EN |
865 | static ssize_t st_taps_show(struct device *dev, |
866 | struct device_attribute *attr, char *buf) | |
867 | { | |
868 | struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); | |
869 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | |
870 | ssize_t status = 0; | |
871 | int i; | |
872 | ||
873 | spin_lock_irq(&mcbsp->lock); | |
874 | for (i = 0; i < st_data->nr_taps; i++) | |
875 | status += sprintf(&buf[status], (i ? ", %d" : "%d"), | |
876 | st_data->taps[i]); | |
877 | if (i) | |
878 | status += sprintf(&buf[status], "\n"); | |
879 | spin_unlock_irq(&mcbsp->lock); | |
880 | ||
881 | return status; | |
882 | } | |
883 | ||
884 | static ssize_t st_taps_store(struct device *dev, | |
885 | struct device_attribute *attr, | |
886 | const char *buf, size_t size) | |
887 | { | |
888 | struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); | |
889 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | |
890 | int val, tmp, status, i = 0; | |
891 | ||
892 | spin_lock_irq(&mcbsp->lock); | |
893 | memset(st_data->taps, 0, sizeof(st_data->taps)); | |
894 | st_data->nr_taps = 0; | |
895 | ||
896 | do { | |
897 | status = sscanf(buf, "%d%n", &val, &tmp); | |
898 | if (status < 0 || status == 0) { | |
899 | size = -EINVAL; | |
900 | goto out; | |
901 | } | |
902 | if (val < -32768 || val > 32767) { | |
903 | size = -EINVAL; | |
904 | goto out; | |
905 | } | |
906 | st_data->taps[i++] = val; | |
907 | buf += tmp; | |
908 | if (*buf != ',') | |
909 | break; | |
910 | buf++; | |
911 | } while (1); | |
912 | ||
913 | st_data->nr_taps = i; | |
914 | ||
915 | out: | |
916 | spin_unlock_irq(&mcbsp->lock); | |
917 | ||
918 | return size; | |
919 | } | |
920 | ||
921 | static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store); | |
922 | ||
d912fa92 EN |
923 | static const struct attribute *sidetone_attrs[] = { |
924 | &dev_attr_st_taps.attr, | |
925 | NULL, | |
926 | }; | |
927 | ||
928 | static const struct attribute_group sidetone_attr_group = { | |
929 | .attrs = (struct attribute **)sidetone_attrs, | |
930 | }; | |
931 | ||
7ff60006 | 932 | static int omap_st_add(struct omap_mcbsp *mcbsp, struct resource *res) |
d912fa92 | 933 | { |
d912fa92 EN |
934 | struct omap_mcbsp_st_data *st_data; |
935 | int err; | |
936 | ||
2ee65950 PU |
937 | st_data = devm_kzalloc(mcbsp->dev, sizeof(*mcbsp->st_data), GFP_KERNEL); |
938 | if (!st_data) | |
939 | return -ENOMEM; | |
d912fa92 | 940 | |
2ee65950 PU |
941 | st_data->io_base_st = devm_ioremap(mcbsp->dev, res->start, |
942 | resource_size(res)); | |
943 | if (!st_data->io_base_st) | |
944 | return -ENOMEM; | |
d912fa92 EN |
945 | |
946 | err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group); | |
947 | if (err) | |
2ee65950 | 948 | return err; |
d912fa92 EN |
949 | |
950 | mcbsp->st_data = st_data; | |
951 | return 0; | |
a1a56f5f | 952 | } |
a1a56f5f | 953 | |
5e1c5ff4 TL |
954 | /* |
955 | * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. | |
956 | * 730 has only 2 McBSP, and both of them are MPU peripherals. | |
957 | */ | |
7ff60006 | 958 | int omap_mcbsp_init(struct platform_device *pdev) |
bc5d0c89 | 959 | { |
2ee65950 | 960 | struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); |
3cf32bba | 961 | struct resource *res; |
bc5d0c89 | 962 | int ret = 0; |
5e1c5ff4 | 963 | |
b4b58f58 | 964 | spin_lock_init(&mcbsp->lock); |
6722a723 | 965 | mcbsp->free = true; |
bc5d0c89 | 966 | |
3cf32bba | 967 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
5aec892a | 968 | if (!res) |
3cf32bba | 969 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
5aec892a AL |
970 | |
971 | mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res); | |
972 | if (IS_ERR(mcbsp->io_base)) | |
973 | return PTR_ERR(mcbsp->io_base); | |
2ee65950 | 974 | |
3cf32bba | 975 | mcbsp->phys_base = res->start; |
ac6747ca | 976 | mcbsp->reg_cache_size = resource_size(res); |
d592dd1a | 977 | |
3cf32bba KVA |
978 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); |
979 | if (!res) | |
980 | mcbsp->phys_dma_base = mcbsp->phys_base; | |
981 | else | |
982 | mcbsp->phys_dma_base = res->start; | |
983 | ||
35d210fa PU |
984 | /* |
985 | * OMAP1, 2 uses two interrupt lines: TX, RX | |
986 | * OMAP2430, OMAP3 SoC have combined IRQ line as well. | |
987 | * OMAP4 and newer SoC only have the combined IRQ line. | |
988 | * Use the combined IRQ if available since it gives better debugging | |
989 | * possibilities. | |
990 | */ | |
991 | mcbsp->irq = platform_get_irq_byname(pdev, "common"); | |
992 | if (mcbsp->irq == -ENXIO) { | |
993 | mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx"); | |
994 | ||
995 | if (mcbsp->tx_irq == -ENXIO) { | |
996 | mcbsp->irq = platform_get_irq(pdev, 0); | |
997 | mcbsp->tx_irq = 0; | |
998 | } else { | |
999 | mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx"); | |
1000 | mcbsp->irq = 0; | |
1001 | } | |
73c9522e | 1002 | } |
cb7e9ded | 1003 | |
9ab1fac4 PU |
1004 | if (!pdev->dev.of_node) { |
1005 | res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); | |
1006 | if (!res) { | |
1007 | dev_err(&pdev->dev, "invalid tx DMA channel\n"); | |
1008 | return -ENODEV; | |
1009 | } | |
1010 | mcbsp->dma_req[0] = res->start; | |
1011 | mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0]; | |
3cf32bba | 1012 | |
9ab1fac4 PU |
1013 | res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); |
1014 | if (!res) { | |
1015 | dev_err(&pdev->dev, "invalid rx DMA channel\n"); | |
1016 | return -ENODEV; | |
1017 | } | |
1018 | mcbsp->dma_req[1] = res->start; | |
1019 | mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1]; | |
1020 | } else { | |
1021 | mcbsp->dma_data[0].filter_data = "tx"; | |
1022 | mcbsp->dma_data[1].filter_data = "rx"; | |
3cf32bba | 1023 | } |
9ab1fac4 | 1024 | |
09ae3aaf LPC |
1025 | mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp, 0); |
1026 | mcbsp->dma_data[0].maxburst = 4; | |
bc5d0c89 | 1027 | |
9ab1fac4 PU |
1028 | mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp, 1); |
1029 | mcbsp->dma_data[1].maxburst = 4; | |
1030 | ||
b820ce4e RK |
1031 | mcbsp->fclk = clk_get(&pdev->dev, "fck"); |
1032 | if (IS_ERR(mcbsp->fclk)) { | |
1033 | ret = PTR_ERR(mcbsp->fclk); | |
2ee65950 PU |
1034 | dev_err(mcbsp->dev, "unable to get fck: %d\n", ret); |
1035 | return ret; | |
bc5d0c89 EV |
1036 | } |
1037 | ||
7bba67ab JN |
1038 | mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT; |
1039 | if (mcbsp->pdata->buffer_size) { | |
1040 | /* | |
1041 | * Initially configure the maximum thresholds to a safe value. | |
1042 | * The McBSP FIFO usage with these values should not go under | |
1043 | * 16 locations. | |
1044 | * If the whole FIFO without safety buffer is used, than there | |
1045 | * is a possibility that the DMA will be not able to push the | |
1046 | * new data on time, causing channel shifts in runtime. | |
1047 | */ | |
1048 | mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10; | |
1049 | mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10; | |
1050 | ||
1051 | ret = sysfs_create_group(&mcbsp->dev->kobj, | |
1052 | &additional_attr_group); | |
1053 | if (ret) { | |
1054 | dev_err(mcbsp->dev, | |
1055 | "Unable to create additional controls\n"); | |
1056 | goto err_thres; | |
1057 | } | |
1058 | } else { | |
1059 | mcbsp->max_tx_thres = -EINVAL; | |
1060 | mcbsp->max_rx_thres = -EINVAL; | |
1061 | } | |
1062 | ||
f821eece JN |
1063 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone"); |
1064 | if (res) { | |
1065 | ret = omap_st_add(mcbsp, res); | |
1066 | if (ret) { | |
1067 | dev_err(mcbsp->dev, | |
1068 | "Unable to create sidetone controls\n"); | |
1069 | goto err_st; | |
1070 | } | |
1071 | } | |
a1a56f5f | 1072 | |
d592dd1a | 1073 | return 0; |
bc5d0c89 | 1074 | |
f821eece JN |
1075 | err_st: |
1076 | if (mcbsp->pdata->buffer_size) | |
2ee65950 | 1077 | sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group); |
7bba67ab JN |
1078 | err_thres: |
1079 | clk_put(mcbsp->fclk); | |
bc5d0c89 EV |
1080 | return ret; |
1081 | } | |
120db2cb | 1082 | |
7ff60006 | 1083 | void omap_mcbsp_sysfs_remove(struct omap_mcbsp *mcbsp) |
5e1c5ff4 | 1084 | { |
2ee65950 PU |
1085 | if (mcbsp->pdata->buffer_size) |
1086 | sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group); | |
5e1c5ff4 | 1087 | |
2ee65950 PU |
1088 | if (mcbsp->st_data) |
1089 | sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group); | |
5e1c5ff4 | 1090 | } |