[deliverable/linux.git] / sound / soc / omap / mcbsp.h

/*
 * sound/soc/omap/mcbsp.h
 *
 * OMAP Multi-Channel Buffered Serial Port
 *
 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
 *          Peter Ujfalusi <peter.ujfalusi@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 */
#ifndef __ASOC_MCBSP_H
#define __ASOC_MCBSP_H

#ifdef CONFIG_ARCH_OMAP1
#define mcbsp_omap1()	1
#else
#define mcbsp_omap1()	0
#endif

#include <sound/dmaengine_pcm.h>

/* McBSP register numbers. Register address offset = num * reg_step */
enum {
	/* Common registers */
	OMAP_MCBSP_REG_SPCR2 = 4,
	OMAP_MCBSP_REG_SPCR1,
	OMAP_MCBSP_REG_RCR2,
	OMAP_MCBSP_REG_RCR1,
	OMAP_MCBSP_REG_XCR2,
	OMAP_MCBSP_REG_XCR1,
	OMAP_MCBSP_REG_SRGR2,
	OMAP_MCBSP_REG_SRGR1,
	OMAP_MCBSP_REG_MCR2,
	OMAP_MCBSP_REG_MCR1,
	OMAP_MCBSP_REG_RCERA,
	OMAP_MCBSP_REG_RCERB,
	OMAP_MCBSP_REG_XCERA,
	OMAP_MCBSP_REG_XCERB,
	OMAP_MCBSP_REG_PCR0,
	OMAP_MCBSP_REG_RCERC,
	OMAP_MCBSP_REG_RCERD,
	OMAP_MCBSP_REG_XCERC,
	OMAP_MCBSP_REG_XCERD,
	OMAP_MCBSP_REG_RCERE,
	OMAP_MCBSP_REG_RCERF,
	OMAP_MCBSP_REG_XCERE,
	OMAP_MCBSP_REG_XCERF,
	OMAP_MCBSP_REG_RCERG,
	OMAP_MCBSP_REG_RCERH,
	OMAP_MCBSP_REG_XCERG,
	OMAP_MCBSP_REG_XCERH,

	/* OMAP1-OMAP2420 registers */
	OMAP_MCBSP_REG_DRR2 = 0,
	OMAP_MCBSP_REG_DRR1,
	OMAP_MCBSP_REG_DXR2,
	OMAP_MCBSP_REG_DXR1,

	/* OMAP2430 and onwards */
	OMAP_MCBSP_REG_DRR = 0,
	OMAP_MCBSP_REG_DXR = 2,
	OMAP_MCBSP_REG_SYSCON =	35,
	OMAP_MCBSP_REG_THRSH2,
	OMAP_MCBSP_REG_THRSH1,
	OMAP_MCBSP_REG_IRQST = 40,
	OMAP_MCBSP_REG_IRQEN,
	OMAP_MCBSP_REG_WAKEUPEN,
	OMAP_MCBSP_REG_XCCR,
	OMAP_MCBSP_REG_RCCR,
	OMAP_MCBSP_REG_XBUFFSTAT,
	OMAP_MCBSP_REG_RBUFFSTAT,
	OMAP_MCBSP_REG_SSELCR,
};

/* OMAP3 sidetone control registers */
#define OMAP_ST_REG_REV		0x00
#define OMAP_ST_REG_SYSCONFIG	0x10
#define OMAP_ST_REG_IRQSTATUS	0x18
#define OMAP_ST_REG_IRQENABLE	0x1C
#define OMAP_ST_REG_SGAINCR	0x24
#define OMAP_ST_REG_SFIRCR	0x28
#define OMAP_ST_REG_SSELCR	0x2C

/************************** McBSP SPCR1 bit definitions ***********************/
#define RRST			BIT(0)
#define RRDY			BIT(1)
#define RFULL			BIT(2)
#define RSYNC_ERR		BIT(3)
#define RINTM(value)		(((value) & 0x3) << 4)	/* bits 4:5 */
#define ABIS			BIT(6)
#define DXENA			BIT(7)
#define CLKSTP(value)		(((value) & 0x3) << 11)	/* bits 11:12 */
#define RJUST(value)		(((value) & 0x3) << 13)	/* bits 13:14 */
#define ALB			BIT(15)
#define DLB			BIT(15)

/************************** McBSP SPCR2 bit definitions ***********************/
#define XRST			BIT(0)
#define XRDY			BIT(1)
#define XEMPTY			BIT(2)
#define XSYNC_ERR		BIT(3)
#define XINTM(value)		(((value) & 0x3) << 4)	/* bits 4:5 */
#define GRST			BIT(6)
#define FRST			BIT(7)
#define SOFT			BIT(8)
#define FREE			BIT(9)

/************************** McBSP PCR bit definitions *************************/
#define CLKRP			BIT(0)
#define CLKXP			BIT(1)
#define FSRP			BIT(2)
#define FSXP			BIT(3)
#define DR_STAT			BIT(4)
#define DX_STAT			BIT(5)
#define CLKS_STAT		BIT(6)
#define SCLKME			BIT(7)
#define CLKRM			BIT(8)
#define CLKXM			BIT(9)
#define FSRM			BIT(10)
#define FSXM			BIT(11)
#define RIOEN			BIT(12)
#define XIOEN			BIT(13)
#define IDLE_EN			BIT(14)

/************************** McBSP RCR1 bit definitions ************************/
#define RWDLEN1(value)		(((value) & 0x7) << 5)	/* Bits 5:7 */
#define RFRLEN1(value)		(((value) & 0x7f) << 8)	/* Bits 8:14 */

/************************** McBSP XCR1 bit definitions ************************/
#define XWDLEN1(value)		(((value) & 0x7) << 5)	/* Bits 5:7 */
#define XFRLEN1(value)		(((value) & 0x7f) << 8)	/* Bits 8:14 */

/*************************** McBSP RCR2 bit definitions ***********************/
#define RDATDLY(value)		((value) & 0x3)		/* Bits 0:1 */
#define RFIG			BIT(2)
#define RCOMPAND(value)		(((value) & 0x3) << 3)	/* Bits 3:4 */
#define RWDLEN2(value)		(((value) & 0x7) << 5)	/* Bits 5:7 */
#define RFRLEN2(value)		(((value) & 0x7f) << 8)	/* Bits 8:14 */
#define RPHASE			BIT(15)

/*************************** McBSP XCR2 bit definitions ***********************/
#define XDATDLY(value)		((value) & 0x3)		/* Bits 0:1 */
#define XFIG			BIT(2)
#define XCOMPAND(value)		(((value) & 0x3) << 3)	/* Bits 3:4 */
#define XWDLEN2(value)		(((value) & 0x7) << 5)	/* Bits 5:7 */
#define XFRLEN2(value)		(((value) & 0x7f) << 8)	/* Bits 8:14 */
#define XPHASE			BIT(15)

/************************* McBSP SRGR1 bit definitions ************************/
#define CLKGDV(value)		((value) & 0x7f)		/* Bits 0:7 */
#define FWID(value)		(((value) & 0xff) << 8)	/* Bits 8:15 */

/************************* McBSP SRGR2 bit definitions ************************/
#define FPER(value)		((value) & 0x0fff)	/* Bits 0:11 */
#define FSGM			BIT(12)
#define CLKSM			BIT(13)
#define CLKSP			BIT(14)
#define GSYNC			BIT(15)

/************************* McBSP MCR1 bit definitions *************************/
#define RMCM			BIT(0)
#define RCBLK(value)		(((value) & 0x7) << 2)	/* Bits 2:4 */
#define RPABLK(value)		(((value) & 0x3) << 5)	/* Bits 5:6 */
#define RPBBLK(value)		(((value) & 0x3) << 7)	/* Bits 7:8 */

/************************* McBSP MCR2 bit definitions *************************/
#define XMCM(value)		((value) & 0x3)		/* Bits 0:1 */
#define XCBLK(value)		(((value) & 0x7) << 2)	/* Bits 2:4 */
#define XPABLK(value)		(((value) & 0x3) << 5)	/* Bits 5:6 */
#define XPBBLK(value)		(((value) & 0x3) << 7)	/* Bits 7:8 */

/*********************** McBSP XCCR bit definitions *************************/
#define XDISABLE		BIT(0)
#define XDMAEN			BIT(3)
#define DILB			BIT(5)
#define XFULL_CYCLE		BIT(11)
#define DXENDLY(value)		(((value) & 0x3) << 12)	/* Bits 12:13 */
#define PPCONNECT		BIT(14)
#define EXTCLKGATE		BIT(15)

/********************** McBSP RCCR bit definitions *************************/
#define RDISABLE		BIT(0)
#define RDMAEN			BIT(3)
#define RFULL_CYCLE		BIT(11)

/********************** McBSP SYSCONFIG bit definitions ********************/
#define SOFTRST			BIT(1)
#define ENAWAKEUP		BIT(2)
#define SIDLEMODE(value)	(((value) & 0x3) << 3)
#define CLOCKACTIVITY(value)	(((value) & 0x3) << 8)

/********************** McBSP SSELCR bit definitions ***********************/
#define SIDETONEEN		BIT(10)

/********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
#define ST_AUTOIDLE		BIT(0)

/********************** McBSP Sidetone SGAINCR bit definitions *************/
#define ST_CH0GAIN(value)	((value) & 0xffff)	/* Bits 0:15 */
#define ST_CH1GAIN(value)	(((value) & 0xffff) << 16) /* Bits 16:31 */

/********************** McBSP Sidetone SFIRCR bit definitions **************/
#define ST_FIRCOEFF(value)	((value) & 0xffff)	/* Bits 0:15 */

/********************** McBSP Sidetone SSELCR bit definitions **************/
#define ST_SIDETONEEN		BIT(0)
#define ST_COEFFWREN		BIT(1)
#define ST_COEFFWRDONE		BIT(2)

/********************** McBSP DMA operating modes **************************/
#define MCBSP_DMA_MODE_ELEMENT		0
#define MCBSP_DMA_MODE_THRESHOLD	1

/********************** McBSP WAKEUPEN/IRQST/IRQEN bit definitions *********/
#define RSYNCERREN		BIT(0)
#define RFSREN			BIT(1)
#define REOFEN			BIT(2)
#define RRDYEN			BIT(3)
#define RUNDFLEN		BIT(4)
#define ROVFLEN			BIT(5)
#define XSYNCERREN		BIT(7)
#define XFSXEN			BIT(8)
#define XEOFEN			BIT(9)
#define XRDYEN			BIT(10)
#define XUNDFLEN		BIT(11)
#define XOVFLEN			BIT(12)
#define XEMPTYEOFEN		BIT(14)

/* Clock signal muxing options */
#define CLKR_SRC_CLKR		0 /* CLKR signal is from the CLKR pin */
#define CLKR_SRC_CLKX		1 /* CLKR signal is from the CLKX pin */
#define FSR_SRC_FSR		2 /* FSR signal is from the FSR pin */
#define FSR_SRC_FSX		3 /* FSR signal is from the FSX pin */

/* McBSP functional clock sources */
#define MCBSP_CLKS_PRCM_SRC	0
#define MCBSP_CLKS_PAD_SRC	1

/* we don't do multichannel for now */
struct omap_mcbsp_reg_cfg {
	u16 spcr2;
	u16 spcr1;
	u16 rcr2;
	u16 rcr1;
	u16 xcr2;
	u16 xcr1;
	u16 srgr2;
	u16 srgr1;
	u16 mcr2;
	u16 mcr1;
	u16 pcr0;
	u16 rcerc;
	u16 rcerd;
	u16 xcerc;
	u16 xcerd;
	u16 rcere;
	u16 rcerf;
	u16 xcere;
	u16 xcerf;
	u16 rcerg;
	u16 rcerh;
	u16 xcerg;
	u16 xcerh;
	u16 xccr;
	u16 rccr;
};

struct omap_mcbsp_st_data {
	void __iomem *io_base_st;
	struct clk *mcbsp_iclk;
	bool running;
	bool enabled;
	s16 taps[128];	/* Sidetone filter coefficients */
	int nr_taps;	/* Number of filter coefficients in use */
	s16 ch0gain;
	s16 ch1gain;
};

struct omap_mcbsp {
	struct device *dev;
	struct clk *fclk;
	spinlock_t lock;
	unsigned long phys_base;
	unsigned long phys_dma_base;
	void __iomem *io_base;
	u8 id;
	/*
	 * Flags indicating is the bus already activated and configured by
	 * another substream
	 */
	int active;
	int configured;
	u8 free;

	int irq;
	int rx_irq;
	int tx_irq;

	/* Protect the field .free, while checking if the mcbsp is in use */
	struct omap_mcbsp_platform_data *pdata;
	struct omap_mcbsp_st_data *st_data;
	struct omap_mcbsp_reg_cfg cfg_regs;
	struct snd_dmaengine_dai_dma_data dma_data[2];
	unsigned int dma_req[2];
	int dma_op_mode;
	u16 max_tx_thres;
	u16 max_rx_thres;
	void *reg_cache;
	int reg_cache_size;

	unsigned int fmt;
	unsigned int in_freq;
	int clk_div;
	int wlen;
};

void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
		       const struct omap_mcbsp_reg_cfg *config);
void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold);
void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold);
u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp);
u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp);
int omap_mcbsp_get_dma_op_mode(struct omap_mcbsp *mcbsp);
int omap_mcbsp_request(struct omap_mcbsp *mcbsp);
void omap_mcbsp_free(struct omap_mcbsp *mcbsp);
void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx);
void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx);

/* McBSP functional clock source changing function */
int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id);

/* Sidetone specific API */
int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain);
int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain);
int omap_st_enable(struct omap_mcbsp *mcbsp);
int omap_st_disable(struct omap_mcbsp *mcbsp);
int omap_st_is_enabled(struct omap_mcbsp *mcbsp);

int omap_mcbsp_init(struct platform_device *pdev);
void omap_mcbsp_cleanup(struct omap_mcbsp *mcbsp);

#endif /* __ASOC_MCBSP_H */
Commit	Line	Data
219f4316 PU	1	/*
	2	* sound/soc/omap/mcbsp.h
	3	*
	4	* OMAP Multi-Channel Buffered Serial Port
	5	*
	6	* Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
	7	* Peter Ujfalusi <peter.ujfalusi@ti.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	*/
	24	#ifndef __ASOC_MCBSP_H
	25	#define __ASOC_MCBSP_H
	26
e650794a TL	27	#ifdef CONFIG_ARCH_OMAP1
	28	#define mcbsp_omap1() 1
	29	#else
	30	#define mcbsp_omap1() 0
	31	#endif
	32
09ae3aaf LPC	33	#include <sound/dmaengine_pcm.h>
09ae3aaf LPC	34
219f4316 PU	35	/* McBSP register numbers. Register address offset = num * reg_step */
	36	enum {
	37	/* Common registers */
	38	OMAP_MCBSP_REG_SPCR2 = 4,
	39	OMAP_MCBSP_REG_SPCR1,
	40	OMAP_MCBSP_REG_RCR2,
	41	OMAP_MCBSP_REG_RCR1,
	42	OMAP_MCBSP_REG_XCR2,
	43	OMAP_MCBSP_REG_XCR1,
	44	OMAP_MCBSP_REG_SRGR2,
	45	OMAP_MCBSP_REG_SRGR1,
	46	OMAP_MCBSP_REG_MCR2,
	47	OMAP_MCBSP_REG_MCR1,
	48	OMAP_MCBSP_REG_RCERA,
	49	OMAP_MCBSP_REG_RCERB,
	50	OMAP_MCBSP_REG_XCERA,
	51	OMAP_MCBSP_REG_XCERB,
	52	OMAP_MCBSP_REG_PCR0,
	53	OMAP_MCBSP_REG_RCERC,
	54	OMAP_MCBSP_REG_RCERD,
	55	OMAP_MCBSP_REG_XCERC,
	56	OMAP_MCBSP_REG_XCERD,
	57	OMAP_MCBSP_REG_RCERE,
	58	OMAP_MCBSP_REG_RCERF,
	59	OMAP_MCBSP_REG_XCERE,
	60	OMAP_MCBSP_REG_XCERF,
	61	OMAP_MCBSP_REG_RCERG,
	62	OMAP_MCBSP_REG_RCERH,
	63	OMAP_MCBSP_REG_XCERG,
	64	OMAP_MCBSP_REG_XCERH,
	65
	66	/* OMAP1-OMAP2420 registers */
	67	OMAP_MCBSP_REG_DRR2 = 0,
	68	OMAP_MCBSP_REG_DRR1,
	69	OMAP_MCBSP_REG_DXR2,
	70	OMAP_MCBSP_REG_DXR1,
	71
	72	/* OMAP2430 and onwards */
	73	OMAP_MCBSP_REG_DRR = 0,
	74	OMAP_MCBSP_REG_DXR = 2,
	75	OMAP_MCBSP_REG_SYSCON = 35,
	76	OMAP_MCBSP_REG_THRSH2,
	77	OMAP_MCBSP_REG_THRSH1,
	78	OMAP_MCBSP_REG_IRQST = 40,
	79	OMAP_MCBSP_REG_IRQEN,
	80	OMAP_MCBSP_REG_WAKEUPEN,
	81	OMAP_MCBSP_REG_XCCR,
	82	OMAP_MCBSP_REG_RCCR,
	83	OMAP_MCBSP_REG_XBUFFSTAT,
	84	OMAP_MCBSP_REG_RBUFFSTAT,
	85	OMAP_MCBSP_REG_SSELCR,
	86	};
	87
	88	/* OMAP3 sidetone control registers */
	89	#define OMAP_ST_REG_REV 0x00
	90	#define OMAP_ST_REG_SYSCONFIG 0x10
	91	#define OMAP_ST_REG_IRQSTATUS 0x18
	92	#define OMAP_ST_REG_IRQENABLE 0x1C
	93	#define OMAP_ST_REG_SGAINCR 0x24
	94	#define OMAP_ST_REG_SFIRCR 0x28
	95	#define OMAP_ST_REG_SSELCR 0x2C
	96
	97	/************************ McBSP SPCR1 bit definitions *********************/
81da6a9e PU	98	#define RRST BIT(0)
	99	#define RRDY BIT(1)
	100	#define RFULL BIT(2)
	101	#define RSYNC_ERR BIT(3)
	102	#define RINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */
	103	#define ABIS BIT(6)
	104	#define DXENA BIT(7)
	105	#define CLKSTP(value) (((value) & 0x3) << 11) /* bits 11:12 */
	106	#define RJUST(value) (((value) & 0x3) << 13) /* bits 13:14 */
	107	#define ALB BIT(15)
	108	#define DLB BIT(15)
219f4316 PU	109
219f4316 PU	110	/************************ McBSP SPCR2 bit definitions *********************/
81da6a9e PU	111	#define XRST BIT(0)
	112	#define XRDY BIT(1)
	113	#define XEMPTY BIT(2)
	114	#define XSYNC_ERR BIT(3)
	115	#define XINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */
	116	#define GRST BIT(6)
	117	#define FRST BIT(7)
	118	#define SOFT BIT(8)
	119	#define FREE BIT(9)
219f4316 PU	120
219f4316 PU	121	/************************ McBSP PCR bit definitions ***********************/
81da6a9e PU	122	#define CLKRP BIT(0)
	123	#define CLKXP BIT(1)
	124	#define FSRP BIT(2)
	125	#define FSXP BIT(3)
	126	#define DR_STAT BIT(4)
	127	#define DX_STAT BIT(5)
	128	#define CLKS_STAT BIT(6)
	129	#define SCLKME BIT(7)
	130	#define CLKRM BIT(8)
	131	#define CLKXM BIT(9)
	132	#define FSRM BIT(10)
	133	#define FSXM BIT(11)
	134	#define RIOEN BIT(12)
	135	#define XIOEN BIT(13)
	136	#define IDLE_EN BIT(14)
219f4316 PU	137
219f4316 PU	138	/************************ McBSP RCR1 bit definitions **********************/
81da6a9e PU	139	#define RWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */
81da6a9e PU	140	#define RFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
219f4316 PU	141
219f4316 PU	142	/************************ McBSP XCR1 bit definitions **********************/
81da6a9e PU	143	#define XWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */
81da6a9e PU	144	#define XFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
219f4316 PU	145
219f4316 PU	146	/************************* McBSP RCR2 bit definitions *********************/
81da6a9e PU	147	#define RDATDLY(value) ((value) & 0x3) /* Bits 0:1 */
	148	#define RFIG BIT(2)
	149	#define RCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */
	150	#define RWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */
	151	#define RFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
	152	#define RPHASE BIT(15)
219f4316 PU	153
219f4316 PU	154	/************************* McBSP XCR2 bit definitions *********************/
81da6a9e PU	155	#define XDATDLY(value) ((value) & 0x3) /* Bits 0:1 */
	156	#define XFIG BIT(2)
	157	#define XCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */
	158	#define XWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */
	159	#define XFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
	160	#define XPHASE BIT(15)
219f4316 PU	161
219f4316 PU	162	/*********************** McBSP SRGR1 bit definitions **********************/
81da6a9e PU	163	#define CLKGDV(value) ((value) & 0x7f) /* Bits 0:7 */
81da6a9e PU	164	#define FWID(value) (((value) & 0xff) << 8) /* Bits 8:15 */
219f4316 PU	165
219f4316 PU	166	/*********************** McBSP SRGR2 bit definitions **********************/
81da6a9e PU	167	#define FPER(value) ((value) & 0x0fff) /* Bits 0:11 */
	168	#define FSGM BIT(12)
	169	#define CLKSM BIT(13)
	170	#define CLKSP BIT(14)
	171	#define GSYNC BIT(15)
219f4316 PU	172
219f4316 PU	173	/*********************** McBSP MCR1 bit definitions ***********************/
81da6a9e PU	174	#define RMCM BIT(0)
	175	#define RCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */
	176	#define RPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */
	177	#define RPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */
219f4316 PU	178
219f4316 PU	179	/*********************** McBSP MCR2 bit definitions ***********************/
81da6a9e PU	180	#define XMCM(value) ((value) & 0x3) /* Bits 0:1 */
	181	#define XCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */
	182	#define XPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */
	183	#define XPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */
219f4316 PU	184
219f4316 PU	185	/********************* McBSP XCCR bit definitions ***********************/
81da6a9e PU	186	#define XDISABLE BIT(0)
	187	#define XDMAEN BIT(3)
	188	#define DILB BIT(5)
	189	#define XFULL_CYCLE BIT(11)
	190	#define DXENDLY(value) (((value) & 0x3) << 12) /* Bits 12:13 */
	191	#define PPCONNECT BIT(14)
	192	#define EXTCLKGATE BIT(15)
219f4316 PU	193
219f4316 PU	194	/******************** McBSP RCCR bit definitions ***********************/
81da6a9e PU	195	#define RDISABLE BIT(0)
	196	#define RDMAEN BIT(3)
	197	#define RFULL_CYCLE BIT(11)
219f4316 PU	198
219f4316 PU	199	/******************** McBSP SYSCONFIG bit definitions ******************/
81da6a9e PU	200	#define SOFTRST BIT(1)
	201	#define ENAWAKEUP BIT(2)
	202	#define SIDLEMODE(value) (((value) & 0x3) << 3)
	203	#define CLOCKACTIVITY(value) (((value) & 0x3) << 8)
219f4316 PU	204
219f4316 PU	205	/******************** McBSP SSELCR bit definitions *********************/
81da6a9e	206	#define SIDETONEEN BIT(10)
219f4316 PU	207
219f4316 PU	208	/******************** McBSP Sidetone SYSCONFIG bit definitions *********/
81da6a9e	209	#define ST_AUTOIDLE BIT(0)
219f4316 PU	210
219f4316 PU	211	/******************** McBSP Sidetone SGAINCR bit definitions ***********/
81da6a9e PU	212	#define ST_CH0GAIN(value) ((value) & 0xffff) /* Bits 0:15 */
81da6a9e PU	213	#define ST_CH1GAIN(value) (((value) & 0xffff) << 16) /* Bits 16:31 */
219f4316 PU	214
219f4316 PU	215	/******************** McBSP Sidetone SFIRCR bit definitions ************/
81da6a9e	216	#define ST_FIRCOEFF(value) ((value) & 0xffff) /* Bits 0:15 */
219f4316 PU	217
219f4316 PU	218	/******************** McBSP Sidetone SSELCR bit definitions ************/
81da6a9e PU	219	#define ST_SIDETONEEN BIT(0)
	220	#define ST_COEFFWREN BIT(1)
	221	#define ST_COEFFWRDONE BIT(2)
219f4316 PU	222
	223	/******************** McBSP DMA operating modes ************************/
	224	#define MCBSP_DMA_MODE_ELEMENT 0
	225	#define MCBSP_DMA_MODE_THRESHOLD 1
219f4316	226
35d210fa	227	/******************** McBSP WAKEUPEN/IRQST/IRQEN bit definitions *******/
81da6a9e PU	228	#define RSYNCERREN BIT(0)
	229	#define RFSREN BIT(1)
	230	#define REOFEN BIT(2)
	231	#define RRDYEN BIT(3)
35d210fa PU	232	#define RUNDFLEN BIT(4)
35d210fa PU	233	#define ROVFLEN BIT(5)
81da6a9e PU	234	#define XSYNCERREN BIT(7)
	235	#define XFSXEN BIT(8)
	236	#define XEOFEN BIT(9)
	237	#define XRDYEN BIT(10)
35d210fa PU	238	#define XUNDFLEN BIT(11)
35d210fa PU	239	#define XOVFLEN BIT(12)
81da6a9e	240	#define XEMPTYEOFEN BIT(14)
219f4316	241
cd1f08c7 PU	242	/* Clock signal muxing options */
	243	#define CLKR_SRC_CLKR 0 /* CLKR signal is from the CLKR pin */
	244	#define CLKR_SRC_CLKX 1 /* CLKR signal is from the CLKX pin */
	245	#define FSR_SRC_FSR 2 /* FSR signal is from the FSR pin */
	246	#define FSR_SRC_FSX 3 /* FSR signal is from the FSX pin */
33cec399 PU	247
	248	/* McBSP functional clock sources */
	249	#define MCBSP_CLKS_PRCM_SRC 0
	250	#define MCBSP_CLKS_PAD_SRC 1
	251
219f4316 PU	252	/* we don't do multichannel for now */
	253	struct omap_mcbsp_reg_cfg {
	254	u16 spcr2;
	255	u16 spcr1;
	256	u16 rcr2;
	257	u16 rcr1;
	258	u16 xcr2;
	259	u16 xcr1;
	260	u16 srgr2;
	261	u16 srgr1;
	262	u16 mcr2;
	263	u16 mcr1;
	264	u16 pcr0;
	265	u16 rcerc;
	266	u16 rcerd;
	267	u16 xcerc;
	268	u16 xcerd;
	269	u16 rcere;
	270	u16 rcerf;
	271	u16 xcere;
	272	u16 xcerf;
	273	u16 rcerg;
	274	u16 rcerh;
	275	u16 xcerg;
	276	u16 xcerh;
	277	u16 xccr;
	278	u16 rccr;
	279	};
	280
45656b44 PU	281	struct omap_mcbsp_st_data {
45656b44 PU	282	void __iomem *io_base_st;
bbfa26c5	283	struct clk *mcbsp_iclk;
45656b44 PU	284	bool running;
	285	bool enabled;
	286	s16 taps[128]; /* Sidetone filter coefficients */
	287	int nr_taps; /* Number of filter coefficients in use */
	288	s16 ch0gain;
	289	s16 ch1gain;
	290	};
	291
45656b44 PU	292	struct omap_mcbsp {
45656b44 PU	293	struct device *dev;
256d9c25 PU	294	struct clk *fclk;
256d9c25 PU	295	spinlock_t lock;
45656b44 PU	296	unsigned long phys_base;
	297	unsigned long phys_dma_base;
	298	void __iomem *io_base;
	299	u8 id;
256d9c25 PU	300	/*
	301	* Flags indicating is the bus already activated and configured by
	302	* another substream
	303	*/
	304	int active;
	305	int configured;
45656b44 PU	306	u8 free;
45656b44 PU	307
35d210fa	308	int irq;
45656b44 PU	309	int rx_irq;
	310	int tx_irq;
	311
45656b44	312	/* Protect the field .free, while checking if the mcbsp is in use */
45656b44	313	struct omap_mcbsp_platform_data *pdata;
45656b44	314	struct omap_mcbsp_st_data *st_data;
256d9c25	315	struct omap_mcbsp_reg_cfg cfg_regs;
09ae3aaf LPC	316	struct snd_dmaengine_dai_dma_data dma_data[2];
09ae3aaf LPC	317	unsigned int dma_req[2];
45656b44 PU	318	int dma_op_mode;
	319	u16 max_tx_thres;
	320	u16 max_rx_thres;
	321	void *reg_cache;
	322	int reg_cache_size;
256d9c25 PU	323
	324	unsigned int fmt;
	325	unsigned int in_freq;
	326	int clk_div;
	327	int wlen;
45656b44 PU	328	};
	329
	330	void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
219f4316	331	const struct omap_mcbsp_reg_cfg *config);
45656b44 PU	332	void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold);
45656b44 PU	333	void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold);
45656b44 PU	334	u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp);
	335	u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp);
	336	int omap_mcbsp_get_dma_op_mode(struct omap_mcbsp *mcbsp);
	337	int omap_mcbsp_request(struct omap_mcbsp *mcbsp);
	338	void omap_mcbsp_free(struct omap_mcbsp *mcbsp);
	339	void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx);
	340	void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx);
219f4316 PU	341
219f4316 PU	342	/* McBSP functional clock source changing function */
45656b44	343	int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id);
219f4316	344
219f4316	345	/* Sidetone specific API */
45656b44 PU	346	int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain);
	347	int omap_st_get_chgain(struct omap_mcbsp mcbsp, int channel, s16 chgain);
	348	int omap_st_enable(struct omap_mcbsp *mcbsp);
	349	int omap_st_disable(struct omap_mcbsp *mcbsp);
	350	int omap_st_is_enabled(struct omap_mcbsp *mcbsp);
	351
7ff60006	352	int omap_mcbsp_init(struct platform_device *pdev);
6610d357	353	void omap_mcbsp_cleanup(struct omap_mcbsp *mcbsp);
219f4316 PU	354
219f4316 PU	355	#endif /* __ASOC_MCBSP_H */