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b3b0b458 CVJ |
1 | /* |
2 | * mcpdm.h -- Defines for McPDM driver | |
3 | * | |
4 | * Author: Jorge Eduardo Candelaria <x0107209@ti.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
18 | * 02110-1301 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | /* McPDM registers */ | |
23 | ||
24 | #define MCPDM_REVISION 0x00 | |
25 | #define MCPDM_SYSCONFIG 0x10 | |
26 | #define MCPDM_IRQSTATUS_RAW 0x24 | |
27 | #define MCPDM_IRQSTATUS 0x28 | |
28 | #define MCPDM_IRQENABLE_SET 0x2C | |
29 | #define MCPDM_IRQENABLE_CLR 0x30 | |
30 | #define MCPDM_IRQWAKE_EN 0x34 | |
31 | #define MCPDM_DMAENABLE_SET 0x38 | |
32 | #define MCPDM_DMAENABLE_CLR 0x3C | |
33 | #define MCPDM_DMAWAKEEN 0x40 | |
34 | #define MCPDM_CTRL 0x44 | |
35 | #define MCPDM_DN_DATA 0x48 | |
36 | #define MCPDM_UP_DATA 0x4C | |
37 | #define MCPDM_FIFO_CTRL_DN 0x50 | |
38 | #define MCPDM_FIFO_CTRL_UP 0x54 | |
39 | #define MCPDM_DN_OFFSET 0x58 | |
40 | ||
41 | /* | |
42 | * MCPDM_IRQ bit fields | |
43 | * IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR | |
44 | */ | |
45 | ||
46 | #define MCPDM_DN_IRQ (1 << 0) | |
47 | #define MCPDM_DN_IRQ_EMPTY (1 << 1) | |
48 | #define MCPDM_DN_IRQ_ALMST_EMPTY (1 << 2) | |
49 | #define MCPDM_DN_IRQ_FULL (1 << 3) | |
50 | ||
51 | #define MCPDM_UP_IRQ (1 << 8) | |
52 | #define MCPDM_UP_IRQ_EMPTY (1 << 9) | |
53 | #define MCPDM_UP_IRQ_ALMST_FULL (1 << 10) | |
54 | #define MCPDM_UP_IRQ_FULL (1 << 11) | |
55 | ||
56 | #define MCPDM_DOWNLINK_IRQ_MASK 0x00F | |
57 | #define MCPDM_UPLINK_IRQ_MASK 0xF00 | |
58 | ||
59 | /* | |
60 | * MCPDM_DMAENABLE bit fields | |
61 | */ | |
62 | ||
63 | #define DMA_DN_ENABLE 0x1 | |
64 | #define DMA_UP_ENABLE 0x2 | |
65 | ||
66 | /* | |
67 | * MCPDM_CTRL bit fields | |
68 | */ | |
69 | ||
70 | #define PDM_UP1_EN 0x0001 | |
71 | #define PDM_UP2_EN 0x0002 | |
72 | #define PDM_UP3_EN 0x0004 | |
73 | #define PDM_DN1_EN 0x0008 | |
74 | #define PDM_DN2_EN 0x0010 | |
75 | #define PDM_DN3_EN 0x0020 | |
76 | #define PDM_DN4_EN 0x0040 | |
77 | #define PDM_DN5_EN 0x0080 | |
78 | #define PDMOUTFORMAT 0x0100 | |
79 | #define CMD_INT 0x0200 | |
80 | #define STATUS_INT 0x0400 | |
81 | #define SW_UP_RST 0x0800 | |
82 | #define SW_DN_RST 0x1000 | |
83 | #define PDM_UP_MASK 0x007 | |
84 | #define PDM_DN_MASK 0x0F8 | |
85 | #define PDM_CMD_MASK 0x200 | |
86 | #define PDM_STATUS_MASK 0x400 | |
87 | ||
88 | ||
89 | #define PDMOUTFORMAT_LJUST (0 << 8) | |
90 | #define PDMOUTFORMAT_RJUST (1 << 8) | |
91 | ||
92 | /* | |
93 | * MCPDM_FIFO_CTRL bit fields | |
94 | */ | |
95 | ||
96 | #define UP_THRES_MAX 0xF | |
97 | #define DN_THRES_MAX 0xF | |
98 | ||
99 | /* | |
100 | * MCPDM_DN_OFFSET bit fields | |
101 | */ | |
102 | ||
103 | #define DN_OFST_RX1_EN 0x0001 | |
104 | #define DN_OFST_RX2_EN 0x0100 | |
105 | ||
106 | #define DN_OFST_RX1 1 | |
107 | #define DN_OFST_RX2 9 | |
108 | #define DN_OFST_MAX 0x1F | |
109 | ||
110 | #define MCPDM_UPLINK 1 | |
111 | #define MCPDM_DOWNLINK 2 | |
112 | ||
113 | struct omap_mcpdm_link { | |
114 | int irq_mask; | |
115 | int threshold; | |
116 | int format; | |
117 | int channels; | |
118 | }; | |
119 | ||
120 | struct omap_mcpdm_platform_data { | |
121 | unsigned long phys_base; | |
122 | u16 irq; | |
123 | }; | |
124 | ||
125 | struct omap_mcpdm { | |
126 | struct device *dev; | |
127 | unsigned long phys_base; | |
128 | void __iomem *io_base; | |
129 | u8 free; | |
130 | int irq; | |
131 | ||
132 | spinlock_t lock; | |
133 | struct omap_mcpdm_platform_data *pdata; | |
134 | struct clk *clk; | |
135 | struct omap_mcpdm_link *downlink; | |
136 | struct omap_mcpdm_link *uplink; | |
137 | struct completion irq_completion; | |
138 | ||
139 | int dn_channels; | |
140 | int up_channels; | |
141 | }; | |
142 | ||
143 | extern void omap_mcpdm_start(int stream); | |
144 | extern void omap_mcpdm_stop(int stream); | |
145 | extern int omap_mcpdm_capture_open(struct omap_mcpdm_link *uplink); | |
146 | extern int omap_mcpdm_playback_open(struct omap_mcpdm_link *downlink); | |
147 | extern int omap_mcpdm_capture_close(struct omap_mcpdm_link *uplink); | |
148 | extern int omap_mcpdm_playback_close(struct omap_mcpdm_link *downlink); | |
149 | extern int omap_mcpdm_request(void); | |
150 | extern void omap_mcpdm_free(void); | |
151 | extern int omap_mcpdm_set_offset(int offset1, int offset2); | |
f0fba2ad LG |
152 | int __devinit omap_mcpdm_probe(struct platform_device *pdev); |
153 | int __devexit omap_mcpdm_remove(struct platform_device *pdev); |