[deliverable/linux.git] / sound / soc / omap / omap-dmic.c

/*
 * omap-dmic.c  --  OMAP ASoC DMIC DAI driver
 *
 * Copyright (C) 2010 - 2011 Texas Instruments
 *
 * Author: David Lambert <dlambert@ti.com>
 *	   Misael Lopez Cruz <misael.lopez@ti.com>
 *	   Liam Girdwood <lrg@ti.com>
 *	   Peter Ujfalusi <peter.ujfalusi@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/of_device.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>

#include "omap-dmic.h"

struct omap_dmic {
	struct device *dev;
	void __iomem *io_base;
	struct clk *fclk;
	int fclk_freq;
	int out_freq;
	int clk_div;
	int sysclk;
	int threshold;
	u32 ch_enabled;
	bool active;
	struct mutex mutex;

	struct snd_dmaengine_dai_dma_data dma_data;
};

static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
{
	writel_relaxed(val, dmic->io_base + reg);
}

static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
{
	return readl_relaxed(dmic->io_base + reg);
}

static inline void omap_dmic_start(struct omap_dmic *dmic)
{
	u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);

	/* Configure DMA controller */
	omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
			OMAP_DMIC_DMA_ENABLE);

	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled);
}

static inline void omap_dmic_stop(struct omap_dmic *dmic)
{
	u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
			ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);

	/* Disable DMA request generation */
	omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
			OMAP_DMIC_DMA_ENABLE);

}

static inline int dmic_is_enabled(struct omap_dmic *dmic)
{
	return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
						OMAP_DMIC_UP_ENABLE_MASK;
}

static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	int ret = 0;

	mutex_lock(&dmic->mutex);

	if (!dai->active)
		dmic->active = 1;
	else
		ret = -EBUSY;

	mutex_unlock(&dmic->mutex);

	snd_soc_dai_set_dma_data(dai, substream, &dmic->dma_data);
	return ret;
}

static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
				    struct snd_soc_dai *dai)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&dmic->mutex);

	if (!dai->active)
		dmic->active = 0;

	mutex_unlock(&dmic->mutex);
}

static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
{
	int divider = -EINVAL;

	/*
	 * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
	 * configuration.
	 */
	if (sample_rate == 192000) {
		if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
			divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
		else
			dev_err(dmic->dev,
				"invalid clock configuration for 192KHz\n");

		return divider;
	}

	switch (dmic->out_freq) {
	case 1536000:
		if (dmic->fclk_freq != 24576000)
			goto div_err;
		divider = 0x4; /* Divider: 16 */
		break;
	case 2400000:
		switch (dmic->fclk_freq) {
		case 12000000:
			divider = 0x5; /* Divider: 5 */
			break;
		case 19200000:
			divider = 0x0; /* Divider: 8 */
			break;
		case 24000000:
			divider = 0x2; /* Divider: 10 */
			break;
		default:
			goto div_err;
		}
		break;
	case 3072000:
		if (dmic->fclk_freq != 24576000)
			goto div_err;
		divider = 0x3; /* Divider: 8 */
		break;
	case 3840000:
		if (dmic->fclk_freq != 19200000)
			goto div_err;
		divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
		break;
	default:
		dev_err(dmic->dev, "invalid out frequency: %dHz\n",
			dmic->out_freq);
		break;
	}

	return divider;

div_err:
	dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
		dmic->out_freq, dmic->fclk_freq);
	return -EINVAL;
}

static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	struct snd_dmaengine_dai_dma_data *dma_data;
	int channels;

	dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
	if (dmic->clk_div < 0) {
		dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
			dmic->out_freq, dmic->fclk_freq);
		return -EINVAL;
	}

	dmic->ch_enabled = 0;
	channels = params_channels(params);
	switch (channels) {
	case 6:
		dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE;
	case 4:
		dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE;
	case 2:
		dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE;
		break;
	default:
		dev_err(dmic->dev, "invalid number of legacy channels\n");
		return -EINVAL;
	}

	/* packet size is threshold * channels */
	dma_data = snd_soc_dai_get_dma_data(dai, substream);
	dma_data->maxburst = dmic->threshold * channels;

	return 0;
}

static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	u32 ctrl;

	/* Configure uplink threshold */
	omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);

	ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);

	/* Set dmic out format */
	ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK);
	ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
		 OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);

	/* Configure dmic clock divider */
	ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
	ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div);

	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);

	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
			ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
			OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);

	return 0;
}

static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
				  int cmd, struct snd_soc_dai *dai)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
		omap_dmic_start(dmic);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
		omap_dmic_stop(dmic);
		break;
	default:
		break;
	}

	return 0;
}

static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
				 unsigned int freq)
{
	struct clk *parent_clk;
	char *parent_clk_name;
	int ret = 0;

	switch (freq) {
	case 12000000:
	case 19200000:
	case 24000000:
	case 24576000:
		break;
	default:
		dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
		dmic->fclk_freq = 0;
		return -EINVAL;
	}

	if (dmic->sysclk == clk_id) {
		dmic->fclk_freq = freq;
		return 0;
	}

	/* re-parent not allowed if a stream is ongoing */
	if (dmic->active && dmic_is_enabled(dmic)) {
		dev_err(dmic->dev, "can't re-parent when DMIC active\n");
		return -EBUSY;
	}

	switch (clk_id) {
	case OMAP_DMIC_SYSCLK_PAD_CLKS:
		parent_clk_name = "pad_clks_ck";
		break;
	case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
		parent_clk_name = "slimbus_clk";
		break;
	case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
		parent_clk_name = "dmic_sync_mux_ck";
		break;
	default:
		dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
		return -EINVAL;
	}

	parent_clk = clk_get(dmic->dev, parent_clk_name);
	if (IS_ERR(parent_clk)) {
		dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
		return -ENODEV;
	}

	mutex_lock(&dmic->mutex);
	if (dmic->active) {
		/* disable clock while reparenting */
		pm_runtime_put_sync(dmic->dev);
		ret = clk_set_parent(dmic->fclk, parent_clk);
		pm_runtime_get_sync(dmic->dev);
	} else {
		ret = clk_set_parent(dmic->fclk, parent_clk);
	}
	mutex_unlock(&dmic->mutex);

	if (ret < 0) {
		dev_err(dmic->dev, "re-parent failed\n");
		goto err_busy;
	}

	dmic->sysclk = clk_id;
	dmic->fclk_freq = freq;

err_busy:
	clk_put(parent_clk);

	return ret;
}

static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
				    unsigned int freq)
{
	int ret = 0;

	if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
		dev_err(dmic->dev, "output clk_id (%d) not supported\n",
			clk_id);
		return -EINVAL;
	}

	switch (freq) {
	case 1536000:
	case 2400000:
	case 3072000:
	case 3840000:
		dmic->out_freq = freq;
		break;
	default:
		dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
		dmic->out_freq = 0;
		ret = -EINVAL;
	}

	return ret;
}

static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
				    unsigned int freq, int dir)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);

	if (dir == SND_SOC_CLOCK_IN)
		return omap_dmic_select_fclk(dmic, clk_id, freq);
	else if (dir == SND_SOC_CLOCK_OUT)
		return omap_dmic_select_outclk(dmic, clk_id, freq);

	dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
	return -EINVAL;
}

static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
	.startup	= omap_dmic_dai_startup,
	.shutdown	= omap_dmic_dai_shutdown,
	.hw_params	= omap_dmic_dai_hw_params,
	.prepare	= omap_dmic_dai_prepare,
	.trigger	= omap_dmic_dai_trigger,
	.set_sysclk	= omap_dmic_set_dai_sysclk,
};

static int omap_dmic_probe(struct snd_soc_dai *dai)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);

	pm_runtime_enable(dmic->dev);

	/* Disable lines while request is ongoing */
	pm_runtime_get_sync(dmic->dev);
	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
	pm_runtime_put_sync(dmic->dev);

	/* Configure DMIC threshold value */
	dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
	return 0;
}

static int omap_dmic_remove(struct snd_soc_dai *dai)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);

	pm_runtime_disable(dmic->dev);

	return 0;
}

static struct snd_soc_dai_driver omap_dmic_dai = {
	.name = "omap-dmic",
	.probe = omap_dmic_probe,
	.remove = omap_dmic_remove,
	.capture = {
		.channels_min = 2,
		.channels_max = 6,
		.rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
		.formats = SNDRV_PCM_FMTBIT_S32_LE,
		.sig_bits = 24,
	},
	.ops = &omap_dmic_dai_ops,
};

static const struct snd_soc_component_driver omap_dmic_component = {
	.name		= "omap-dmic",
};

static int asoc_dmic_probe(struct platform_device *pdev)
{
	struct omap_dmic *dmic;
	struct resource *res;
	int ret;

	dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
	if (!dmic)
		return -ENOMEM;

	platform_set_drvdata(pdev, dmic);
	dmic->dev = &pdev->dev;
	dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;

	mutex_init(&dmic->mutex);

	dmic->fclk = clk_get(dmic->dev, "fck");
	if (IS_ERR(dmic->fclk)) {
		dev_err(dmic->dev, "cant get fck\n");
		return -ENODEV;
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	if (!res) {
		dev_err(dmic->dev, "invalid dma memory resource\n");
		ret = -ENODEV;
		goto err_put_clk;
	}
	dmic->dma_data.addr = res->start + OMAP_DMIC_DATA_REG;

	dmic->dma_data.filter_data = "up_link";

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
	dmic->io_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(dmic->io_base)) {
		ret = PTR_ERR(dmic->io_base);
		goto err_put_clk;
	}


	ret = snd_soc_register_component(&pdev->dev, &omap_dmic_component,
					 &omap_dmic_dai, 1);
	if (ret)
		goto err_put_clk;

	return 0;

err_put_clk:
	clk_put(dmic->fclk);
	return ret;
}

static int asoc_dmic_remove(struct platform_device *pdev)
{
	struct omap_dmic *dmic = platform_get_drvdata(pdev);

	snd_soc_unregister_component(&pdev->dev);
	clk_put(dmic->fclk);

	return 0;
}

static const struct of_device_id omap_dmic_of_match[] = {
	{ .compatible = "ti,omap4-dmic", },
	{ }
};
MODULE_DEVICE_TABLE(of, omap_dmic_of_match);

static struct platform_driver asoc_dmic_driver = {
	.driver = {
		.name = "omap-dmic",
		.owner = THIS_MODULE,
		.of_match_table = omap_dmic_of_match,
	},
	.probe = asoc_dmic_probe,
	.remove = asoc_dmic_remove,
};

module_platform_driver(asoc_dmic_driver);

MODULE_ALIAS("platform:omap-dmic");
MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
fd26f947 PU	1	/*
	2	* omap-dmic.c -- OMAP ASoC DMIC DAI driver
	3	*
	4	* Copyright (C) 2010 - 2011 Texas Instruments
	5	*
	6	* Author: David Lambert <dlambert@ti.com>
	7	* Misael Lopez Cruz <misael.lopez@ti.com>
	8	* Liam Girdwood <lrg@ti.com>
	9	* Peter Ujfalusi <peter.ujfalusi@ti.com>
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License
	13	* version 2 as published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful, but
	16	* WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	23	* 02110-1301 USA
	24	*
	25	*/
	26
	27	#include <linux/init.h>
	28	#include <linux/module.h>
	29	#include <linux/platform_device.h>
	30	#include <linux/err.h>
	31	#include <linux/clk.h>
	32	#include <linux/io.h>
	33	#include <linux/slab.h>
	34	#include <linux/pm_runtime.h>
2ec1be37	35	#include <linux/of_device.h>
fd26f947 PU	36
	37	#include <sound/core.h>
	38	#include <sound/pcm.h>
	39	#include <sound/pcm_params.h>
	40	#include <sound/initval.h>
	41	#include <sound/soc.h>
09ae3aaf	42	#include <sound/dmaengine_pcm.h>
fd26f947	43
fd26f947 PU	44	#include "omap-dmic.h"
	45
	46	struct omap_dmic {
	47	struct device *dev;
	48	void __iomem *io_base;
	49	struct clk *fclk;
	50	int fclk_freq;
	51	int out_freq;
	52	int clk_div;
	53	int sysclk;
	54	int threshold;
	55	u32 ch_enabled;
	56	bool active;
	57	struct mutex mutex;
fd26f947	58
09ae3aaf	59	struct snd_dmaengine_dai_dma_data dma_data;
fd26f947 PU	60	};
	61
	62	static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
	63	{
1b488a48	64	writel_relaxed(val, dmic->io_base + reg);
fd26f947 PU	65	}
	66
	67	static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
	68	{
1b488a48	69	return readl_relaxed(dmic->io_base + reg);
fd26f947 PU	70	}
	71
	72	static inline void omap_dmic_start(struct omap_dmic *dmic)
	73	{
	74	u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
	75
	76	/* Configure DMA controller */
	77	omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
	78	OMAP_DMIC_DMA_ENABLE);
	79
	80	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl \| dmic->ch_enabled);
	81	}
	82
	83	static inline void omap_dmic_stop(struct omap_dmic *dmic)
	84	{
	85	u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
	86	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
	87	ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);
	88
	89	/* Disable DMA request generation */
	90	omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
	91	OMAP_DMIC_DMA_ENABLE);
	92
	93	}
	94
	95	static inline int dmic_is_enabled(struct omap_dmic *dmic)
	96	{
	97	return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
	98	OMAP_DMIC_UP_ENABLE_MASK;
	99	}
	100
	101	static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
	102	struct snd_soc_dai *dai)
	103	{
	104	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	105	int ret = 0;
	106
	107	mutex_lock(&dmic->mutex);
	108
7df6f255	109	if (!dai->active)
fd26f947	110	dmic->active = 1;
7df6f255	111	else
fd26f947	112	ret = -EBUSY;
fd26f947 PU	113
	114	mutex_unlock(&dmic->mutex);
	115
09ae3aaf	116	snd_soc_dai_set_dma_data(dai, substream, &dmic->dma_data);
fd26f947 PU	117	return ret;
	118	}
	119
	120	static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
	121	struct snd_soc_dai *dai)
	122	{
	123	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	124
	125	mutex_lock(&dmic->mutex);
	126
06d07b6b	127	if (!dai->active)
fd26f947	128	dmic->active = 0;
fd26f947 PU	129
	130	mutex_unlock(&dmic->mutex);
	131	}
	132
	133	static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
	134	{
	135	int divider = -EINVAL;
	136
	137	/*
	138	* 192KHz rate is only supported with 19.2MHz/3.84MHz clock
	139	* configuration.
	140	*/
	141	if (sample_rate == 192000) {
	142	if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
	143	divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
	144	else
	145	dev_err(dmic->dev,
	146	"invalid clock configuration for 192KHz\n");
	147
	148	return divider;
	149	}
	150
	151	switch (dmic->out_freq) {
	152	case 1536000:
	153	if (dmic->fclk_freq != 24576000)
	154	goto div_err;
	155	divider = 0x4; /* Divider: 16 */
	156	break;
	157	case 2400000:
	158	switch (dmic->fclk_freq) {
	159	case 12000000:
	160	divider = 0x5; /* Divider: 5 */
	161	break;
	162	case 19200000:
	163	divider = 0x0; /* Divider: 8 */
	164	break;
	165	case 24000000:
	166	divider = 0x2; /* Divider: 10 */
	167	break;
	168	default:
	169	goto div_err;
	170	}
	171	break;
	172	case 3072000:
	173	if (dmic->fclk_freq != 24576000)
	174	goto div_err;
	175	divider = 0x3; /* Divider: 8 */
	176	break;
	177	case 3840000:
	178	if (dmic->fclk_freq != 19200000)
	179	goto div_err;
	180	divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
	181	break;
	182	default:
	183	dev_err(dmic->dev, "invalid out frequency: %dHz\n",
	184	dmic->out_freq);
	185	break;
	186	}
	187
	188	return divider;
	189
	190	div_err:
	191	dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
	192	dmic->out_freq, dmic->fclk_freq);
193	return -EINVAL;
194	}
195
196	static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
197	struct snd_pcm_hw_params *params,
198	struct snd_soc_dai *dai)
199	{
200	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
09ae3aaf	201	struct snd_dmaengine_dai_dma_data *dma_data;
fd26f947 PU	202	int channels;
	203
	204	dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
	205	if (dmic->clk_div < 0) {
	206	dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
	207	dmic->out_freq, dmic->fclk_freq);
	208	return -EINVAL;
	209	}
	210
	211	dmic->ch_enabled = 0;
	212	channels = params_channels(params);
	213	switch (channels) {
	214	case 6:
	215	dmic->ch_enabled \|= OMAP_DMIC_UP3_ENABLE;
	216	case 4:
	217	dmic->ch_enabled \|= OMAP_DMIC_UP2_ENABLE;
	218	case 2:
	219	dmic->ch_enabled \|= OMAP_DMIC_UP1_ENABLE;
	220	break;
	221	default:
	222	dev_err(dmic->dev, "invalid number of legacy channels\n");
	223	return -EINVAL;
	224	}
	225
	226	/* packet size is threshold * channels */
bcd6da7b	227	dma_data = snd_soc_dai_get_dma_data(dai, substream);
09ae3aaf	228	dma_data->maxburst = dmic->threshold * channels;
fd26f947 PU	229
	230	return 0;
	231	}
	232
	233	static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
	234	struct snd_soc_dai *dai)
	235	{
	236	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	237	u32 ctrl;
	238
	239	/* Configure uplink threshold */
	240	omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);
	241
	242	ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
	243
	244	/* Set dmic out format */
	245	ctrl &= ~(OMAP_DMIC_FORMAT \| OMAP_DMIC_POLAR_MASK);
	246	ctrl \|= (OMAP_DMICOUTFORMAT_LJUST \| OMAP_DMIC_POLAR1 \|
	247	OMAP_DMIC_POLAR2 \| OMAP_DMIC_POLAR3);
	248
	249	/* Configure dmic clock divider */
	250	ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
	251	ctrl \|= OMAP_DMIC_CLK_DIV(dmic->clk_div);
	252
	253	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);
	254
	255	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
	256	ctrl \| OMAP_DMICOUTFORMAT_LJUST \| OMAP_DMIC_POLAR1 \|
	257	OMAP_DMIC_POLAR2 \| OMAP_DMIC_POLAR3);
	258
	259	return 0;
	260	}
	261
	262	static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
	263	int cmd, struct snd_soc_dai *dai)
	264	{
	265	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	266
	267	switch (cmd) {
	268	case SNDRV_PCM_TRIGGER_START:
	269	omap_dmic_start(dmic);
	270	break;
	271	case SNDRV_PCM_TRIGGER_STOP:
	272	omap_dmic_stop(dmic);
	273	break;
	274	default:
	275	break;
	276	}
	277
	278	return 0;
	279	}
	280
	281	static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
	282	unsigned int freq)
	283	{
	284	struct clk *parent_clk;
	285	char *parent_clk_name;
	286	int ret = 0;
	287
	288	switch (freq) {
	289	case 12000000:
	290	case 19200000:
	291	case 24000000:
	292	case 24576000:
293	break;
294	default:
295	dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
296	dmic->fclk_freq = 0;
297	return -EINVAL;
298	}
299
300	if (dmic->sysclk == clk_id) {
301	dmic->fclk_freq = freq;
302	return 0;
303	}
304
305	/* re-parent not allowed if a stream is ongoing */
306	if (dmic->active && dmic_is_enabled(dmic)) {
307	dev_err(dmic->dev, "can't re-parent when DMIC active\n");
308	return -EBUSY;
309	}
310
311	switch (clk_id) {
312	case OMAP_DMIC_SYSCLK_PAD_CLKS:
313	parent_clk_name = "pad_clks_ck";
314	break;
315	case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
316	parent_clk_name = "slimbus_clk";
317	break;
318	case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
319	parent_clk_name = "dmic_sync_mux_ck";
320	break;
321	default:
322	dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
323	return -EINVAL;
324	}
325
326	parent_clk = clk_get(dmic->dev, parent_clk_name);
327	if (IS_ERR(parent_clk)) {
328	dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
329	return -ENODEV;
330	}
331
332	mutex_lock(&dmic->mutex);
333	if (dmic->active) {
334	/* disable clock while reparenting */
335	pm_runtime_put_sync(dmic->dev);
336	ret = clk_set_parent(dmic->fclk, parent_clk);
337	pm_runtime_get_sync(dmic->dev);
338	} else {
339	ret = clk_set_parent(dmic->fclk, parent_clk);
340	}
341	mutex_unlock(&dmic->mutex);
342
343	if (ret < 0) {
344	dev_err(dmic->dev, "re-parent failed\n");
345	goto err_busy;
346	}
347
348	dmic->sysclk = clk_id;
349	dmic->fclk_freq = freq;
350
351	err_busy:
352	clk_put(parent_clk);
353
354	return ret;
355	}
356
357	static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
358	unsigned int freq)
359	{
360	int ret = 0;
361
362	if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
363	dev_err(dmic->dev, "output clk_id (%d) not supported\n",
364	clk_id);
365	return -EINVAL;
366	}
367
368	switch (freq) {
369	case 1536000:
370	case 2400000:
371	case 3072000:
372	case 3840000:
373	dmic->out_freq = freq;
374	break;
375	default:
376	dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
377	dmic->out_freq = 0;
378	ret = -EINVAL;
379	}
380
381	return ret;
382	}
383
384	static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
385	unsigned int freq, int dir)
386	{
387	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
388
389	if (dir == SND_SOC_CLOCK_IN)
390	return omap_dmic_select_fclk(dmic, clk_id, freq);
391	else if (dir == SND_SOC_CLOCK_OUT)
392	return omap_dmic_select_outclk(dmic, clk_id, freq);
393
394	dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
395	return -EINVAL;
396	}
397
398	static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
399	.startup = omap_dmic_dai_startup,
400	.shutdown = omap_dmic_dai_shutdown,
401	.hw_params = omap_dmic_dai_hw_params,
402	.prepare = omap_dmic_dai_prepare,
403	.trigger = omap_dmic_dai_trigger,
404	.set_sysclk = omap_dmic_set_dai_sysclk,
405	};
406
407	static int omap_dmic_probe(struct snd_soc_dai *dai)
408	{
409	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
410
411	pm_runtime_enable(dmic->dev);
412
413	/* Disable lines while request is ongoing */
414	pm_runtime_get_sync(dmic->dev);
415	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
416	pm_runtime_put_sync(dmic->dev);
417
418	/* Configure DMIC threshold value */
419	dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
420	return 0;
421	}
422
423	static int omap_dmic_remove(struct snd_soc_dai *dai)
424	{
425	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
426
427	pm_runtime_disable(dmic->dev);
428
429	return 0;
430	}
431
432	static struct snd_soc_dai_driver omap_dmic_dai = {
433	.name = "omap-dmic",
434	.probe = omap_dmic_probe,
435	.remove = omap_dmic_remove,
436	.capture = {
437	.channels_min = 2,
438	.channels_max = 6,
439	.rates = SNDRV_PCM_RATE_96000 \| SNDRV_PCM_RATE_192000,
440	.formats = SNDRV_PCM_FMTBIT_S32_LE,
7df6f255	441	.sig_bits = 24,
fd26f947 PU	442	},
	443	.ops = &omap_dmic_dai_ops,
	444	};
	445
ed22853a KM	446	static const struct snd_soc_component_driver omap_dmic_component = {
	447	.name = "omap-dmic",
	448	};
	449
7ff60006	450	static int asoc_dmic_probe(struct platform_device *pdev)
fd26f947 PU	451	{
	452	struct omap_dmic *dmic;
	453	struct resource *res;
	454	int ret;
	455
	456	dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
	457	if (!dmic)
	458	return -ENOMEM;
	459
	460	platform_set_drvdata(pdev, dmic);
	461	dmic->dev = &pdev->dev;
	462	dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;
	463
	464	mutex_init(&dmic->mutex);
	465
19118eb8	466	dmic->fclk = clk_get(dmic->dev, "fck");
fd26f947	467	if (IS_ERR(dmic->fclk)) {
19118eb8	468	dev_err(dmic->dev, "cant get fck\n");
fd26f947 PU	469	return -ENODEV;
	470	}
	471
	472	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	473	if (!res) {
	474	dev_err(dmic->dev, "invalid dma memory resource\n");
	475	ret = -ENODEV;
	476	goto err_put_clk;
	477	}
09ae3aaf	478	dmic->dma_data.addr = res->start + OMAP_DMIC_DATA_REG;
fd26f947	479
2ebef447	480	dmic->dma_data.filter_data = "up_link";
fd26f947 PU	481
fd26f947 PU	482	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
673c24e9 JL	483	dmic->io_base = devm_ioremap_resource(&pdev->dev, res);
	484	if (IS_ERR(dmic->io_base)) {
	485	ret = PTR_ERR(dmic->io_base);
fd26f947 PU	486	goto err_put_clk;
	487	}
	488
fd26f947	489
ed22853a KM	490	ret = snd_soc_register_component(&pdev->dev, &omap_dmic_component,
ed22853a KM	491	&omap_dmic_dai, 1);
fd26f947 PU	492	if (ret)
	493	goto err_put_clk;
	494
	495	return 0;
	496
	497	err_put_clk:
	498	clk_put(dmic->fclk);
	499	return ret;
	500	}
	501
7ff60006	502	static int asoc_dmic_remove(struct platform_device *pdev)
fd26f947 PU	503	{
	504	struct omap_dmic *dmic = platform_get_drvdata(pdev);
	505
ed22853a	506	snd_soc_unregister_component(&pdev->dev);
fd26f947 PU	507	clk_put(dmic->fclk);
	508
	509	return 0;
	510	}
	511
2ec1be37 PU	512	static const struct of_device_id omap_dmic_of_match[] = {
	513	{ .compatible = "ti,omap4-dmic", },
	514	{ }
	515	};
	516	MODULE_DEVICE_TABLE(of, omap_dmic_of_match);
	517
fd26f947 PU	518	static struct platform_driver asoc_dmic_driver = {
	519	.driver = {
	520	.name = "omap-dmic",
	521	.owner = THIS_MODULE,
2ec1be37	522	.of_match_table = omap_dmic_of_match,
fd26f947 PU	523	},
fd26f947 PU	524	.probe = asoc_dmic_probe,
7ff60006	525	.remove = asoc_dmic_remove,
fd26f947 PU	526	};
	527
	528	module_platform_driver(asoc_dmic_driver);
	529
	530	MODULE_ALIAS("platform:omap-dmic");
	531	MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
	532	MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
	533	MODULE_LICENSE("GPL");