Commit | Line | Data |
---|---|---|
fd26f947 PU |
1 | /* |
2 | * omap-dmic.c -- OMAP ASoC DMIC DAI driver | |
3 | * | |
4 | * Copyright (C) 2010 - 2011 Texas Instruments | |
5 | * | |
6 | * Author: David Lambert <dlambert@ti.com> | |
7 | * Misael Lopez Cruz <misael.lopez@ti.com> | |
8 | * Liam Girdwood <lrg@ti.com> | |
9 | * Peter Ujfalusi <peter.ujfalusi@ti.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * version 2 as published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
23 | * 02110-1301 USA | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/err.h> | |
31 | #include <linux/clk.h> | |
32 | #include <linux/io.h> | |
33 | #include <linux/slab.h> | |
34 | #include <linux/pm_runtime.h> | |
2ec1be37 | 35 | #include <linux/of_device.h> |
fd26f947 PU |
36 | #include <plat/dma.h> |
37 | ||
38 | #include <sound/core.h> | |
39 | #include <sound/pcm.h> | |
40 | #include <sound/pcm_params.h> | |
41 | #include <sound/initval.h> | |
42 | #include <sound/soc.h> | |
43 | ||
44 | #include "omap-pcm.h" | |
45 | #include "omap-dmic.h" | |
46 | ||
47 | struct omap_dmic { | |
48 | struct device *dev; | |
49 | void __iomem *io_base; | |
50 | struct clk *fclk; | |
51 | int fclk_freq; | |
52 | int out_freq; | |
53 | int clk_div; | |
54 | int sysclk; | |
55 | int threshold; | |
56 | u32 ch_enabled; | |
57 | bool active; | |
58 | struct mutex mutex; | |
59 | }; | |
60 | ||
61 | /* | |
62 | * Stream DMA parameters | |
63 | */ | |
64 | static struct omap_pcm_dma_data omap_dmic_dai_dma_params = { | |
65 | .name = "DMIC capture", | |
66 | .data_type = OMAP_DMA_DATA_TYPE_S32, | |
67 | .sync_mode = OMAP_DMA_SYNC_PACKET, | |
68 | }; | |
69 | ||
70 | static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val) | |
71 | { | |
72 | __raw_writel(val, dmic->io_base + reg); | |
73 | } | |
74 | ||
75 | static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg) | |
76 | { | |
77 | return __raw_readl(dmic->io_base + reg); | |
78 | } | |
79 | ||
80 | static inline void omap_dmic_start(struct omap_dmic *dmic) | |
81 | { | |
82 | u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG); | |
83 | ||
84 | /* Configure DMA controller */ | |
85 | omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG, | |
86 | OMAP_DMIC_DMA_ENABLE); | |
87 | ||
88 | omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled); | |
89 | } | |
90 | ||
91 | static inline void omap_dmic_stop(struct omap_dmic *dmic) | |
92 | { | |
93 | u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG); | |
94 | omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, | |
95 | ctrl & ~OMAP_DMIC_UP_ENABLE_MASK); | |
96 | ||
97 | /* Disable DMA request generation */ | |
98 | omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG, | |
99 | OMAP_DMIC_DMA_ENABLE); | |
100 | ||
101 | } | |
102 | ||
103 | static inline int dmic_is_enabled(struct omap_dmic *dmic) | |
104 | { | |
105 | return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) & | |
106 | OMAP_DMIC_UP_ENABLE_MASK; | |
107 | } | |
108 | ||
109 | static int omap_dmic_dai_startup(struct snd_pcm_substream *substream, | |
110 | struct snd_soc_dai *dai) | |
111 | { | |
112 | struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); | |
113 | int ret = 0; | |
114 | ||
115 | mutex_lock(&dmic->mutex); | |
116 | ||
7df6f255 | 117 | if (!dai->active) |
fd26f947 | 118 | dmic->active = 1; |
7df6f255 | 119 | else |
fd26f947 | 120 | ret = -EBUSY; |
fd26f947 PU |
121 | |
122 | mutex_unlock(&dmic->mutex); | |
123 | ||
124 | return ret; | |
125 | } | |
126 | ||
127 | static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream, | |
128 | struct snd_soc_dai *dai) | |
129 | { | |
130 | struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); | |
131 | ||
132 | mutex_lock(&dmic->mutex); | |
133 | ||
06d07b6b | 134 | if (!dai->active) |
fd26f947 | 135 | dmic->active = 0; |
fd26f947 PU |
136 | |
137 | mutex_unlock(&dmic->mutex); | |
138 | } | |
139 | ||
140 | static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate) | |
141 | { | |
142 | int divider = -EINVAL; | |
143 | ||
144 | /* | |
145 | * 192KHz rate is only supported with 19.2MHz/3.84MHz clock | |
146 | * configuration. | |
147 | */ | |
148 | if (sample_rate == 192000) { | |
149 | if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000) | |
150 | divider = 0x6; /* Divider: 5 (192KHz sampling rate) */ | |
151 | else | |
152 | dev_err(dmic->dev, | |
153 | "invalid clock configuration for 192KHz\n"); | |
154 | ||
155 | return divider; | |
156 | } | |
157 | ||
158 | switch (dmic->out_freq) { | |
159 | case 1536000: | |
160 | if (dmic->fclk_freq != 24576000) | |
161 | goto div_err; | |
162 | divider = 0x4; /* Divider: 16 */ | |
163 | break; | |
164 | case 2400000: | |
165 | switch (dmic->fclk_freq) { | |
166 | case 12000000: | |
167 | divider = 0x5; /* Divider: 5 */ | |
168 | break; | |
169 | case 19200000: | |
170 | divider = 0x0; /* Divider: 8 */ | |
171 | break; | |
172 | case 24000000: | |
173 | divider = 0x2; /* Divider: 10 */ | |
174 | break; | |
175 | default: | |
176 | goto div_err; | |
177 | } | |
178 | break; | |
179 | case 3072000: | |
180 | if (dmic->fclk_freq != 24576000) | |
181 | goto div_err; | |
182 | divider = 0x3; /* Divider: 8 */ | |
183 | break; | |
184 | case 3840000: | |
185 | if (dmic->fclk_freq != 19200000) | |
186 | goto div_err; | |
187 | divider = 0x1; /* Divider: 5 (96KHz sampling rate) */ | |
188 | break; | |
189 | default: | |
190 | dev_err(dmic->dev, "invalid out frequency: %dHz\n", | |
191 | dmic->out_freq); | |
192 | break; | |
193 | } | |
194 | ||
195 | return divider; | |
196 | ||
197 | div_err: | |
198 | dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n", | |
199 | dmic->out_freq, dmic->fclk_freq); | |
200 | return -EINVAL; | |
201 | } | |
202 | ||
203 | static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream, | |
204 | struct snd_pcm_hw_params *params, | |
205 | struct snd_soc_dai *dai) | |
206 | { | |
207 | struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); | |
208 | int channels; | |
209 | ||
210 | dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params)); | |
211 | if (dmic->clk_div < 0) { | |
212 | dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n", | |
213 | dmic->out_freq, dmic->fclk_freq); | |
214 | return -EINVAL; | |
215 | } | |
216 | ||
217 | dmic->ch_enabled = 0; | |
218 | channels = params_channels(params); | |
219 | switch (channels) { | |
220 | case 6: | |
221 | dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE; | |
222 | case 4: | |
223 | dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE; | |
224 | case 2: | |
225 | dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE; | |
226 | break; | |
227 | default: | |
228 | dev_err(dmic->dev, "invalid number of legacy channels\n"); | |
229 | return -EINVAL; | |
230 | } | |
231 | ||
232 | /* packet size is threshold * channels */ | |
233 | omap_dmic_dai_dma_params.packet_size = dmic->threshold * channels; | |
234 | snd_soc_dai_set_dma_data(dai, substream, &omap_dmic_dai_dma_params); | |
235 | ||
236 | return 0; | |
237 | } | |
238 | ||
239 | static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream, | |
240 | struct snd_soc_dai *dai) | |
241 | { | |
242 | struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); | |
243 | u32 ctrl; | |
244 | ||
245 | /* Configure uplink threshold */ | |
246 | omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold); | |
247 | ||
248 | ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG); | |
249 | ||
250 | /* Set dmic out format */ | |
251 | ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK); | |
252 | ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 | | |
253 | OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3); | |
254 | ||
255 | /* Configure dmic clock divider */ | |
256 | ctrl &= ~OMAP_DMIC_CLK_DIV_MASK; | |
257 | ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div); | |
258 | ||
259 | omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl); | |
260 | ||
261 | omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, | |
262 | ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 | | |
263 | OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3); | |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
268 | static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream, | |
269 | int cmd, struct snd_soc_dai *dai) | |
270 | { | |
271 | struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); | |
272 | ||
273 | switch (cmd) { | |
274 | case SNDRV_PCM_TRIGGER_START: | |
275 | omap_dmic_start(dmic); | |
276 | break; | |
277 | case SNDRV_PCM_TRIGGER_STOP: | |
278 | omap_dmic_stop(dmic); | |
279 | break; | |
280 | default: | |
281 | break; | |
282 | } | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
287 | static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id, | |
288 | unsigned int freq) | |
289 | { | |
290 | struct clk *parent_clk; | |
291 | char *parent_clk_name; | |
292 | int ret = 0; | |
293 | ||
294 | switch (freq) { | |
295 | case 12000000: | |
296 | case 19200000: | |
297 | case 24000000: | |
298 | case 24576000: | |
299 | break; | |
300 | default: | |
301 | dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq); | |
302 | dmic->fclk_freq = 0; | |
303 | return -EINVAL; | |
304 | } | |
305 | ||
306 | if (dmic->sysclk == clk_id) { | |
307 | dmic->fclk_freq = freq; | |
308 | return 0; | |
309 | } | |
310 | ||
311 | /* re-parent not allowed if a stream is ongoing */ | |
312 | if (dmic->active && dmic_is_enabled(dmic)) { | |
313 | dev_err(dmic->dev, "can't re-parent when DMIC active\n"); | |
314 | return -EBUSY; | |
315 | } | |
316 | ||
317 | switch (clk_id) { | |
318 | case OMAP_DMIC_SYSCLK_PAD_CLKS: | |
319 | parent_clk_name = "pad_clks_ck"; | |
320 | break; | |
321 | case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS: | |
322 | parent_clk_name = "slimbus_clk"; | |
323 | break; | |
324 | case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS: | |
325 | parent_clk_name = "dmic_sync_mux_ck"; | |
326 | break; | |
327 | default: | |
328 | dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id); | |
329 | return -EINVAL; | |
330 | } | |
331 | ||
332 | parent_clk = clk_get(dmic->dev, parent_clk_name); | |
333 | if (IS_ERR(parent_clk)) { | |
334 | dev_err(dmic->dev, "can't get %s\n", parent_clk_name); | |
335 | return -ENODEV; | |
336 | } | |
337 | ||
338 | mutex_lock(&dmic->mutex); | |
339 | if (dmic->active) { | |
340 | /* disable clock while reparenting */ | |
341 | pm_runtime_put_sync(dmic->dev); | |
342 | ret = clk_set_parent(dmic->fclk, parent_clk); | |
343 | pm_runtime_get_sync(dmic->dev); | |
344 | } else { | |
345 | ret = clk_set_parent(dmic->fclk, parent_clk); | |
346 | } | |
347 | mutex_unlock(&dmic->mutex); | |
348 | ||
349 | if (ret < 0) { | |
350 | dev_err(dmic->dev, "re-parent failed\n"); | |
351 | goto err_busy; | |
352 | } | |
353 | ||
354 | dmic->sysclk = clk_id; | |
355 | dmic->fclk_freq = freq; | |
356 | ||
357 | err_busy: | |
358 | clk_put(parent_clk); | |
359 | ||
360 | return ret; | |
361 | } | |
362 | ||
363 | static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id, | |
364 | unsigned int freq) | |
365 | { | |
366 | int ret = 0; | |
367 | ||
368 | if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) { | |
369 | dev_err(dmic->dev, "output clk_id (%d) not supported\n", | |
370 | clk_id); | |
371 | return -EINVAL; | |
372 | } | |
373 | ||
374 | switch (freq) { | |
375 | case 1536000: | |
376 | case 2400000: | |
377 | case 3072000: | |
378 | case 3840000: | |
379 | dmic->out_freq = freq; | |
380 | break; | |
381 | default: | |
382 | dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq); | |
383 | dmic->out_freq = 0; | |
384 | ret = -EINVAL; | |
385 | } | |
386 | ||
387 | return ret; | |
388 | } | |
389 | ||
390 | static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, | |
391 | unsigned int freq, int dir) | |
392 | { | |
393 | struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); | |
394 | ||
395 | if (dir == SND_SOC_CLOCK_IN) | |
396 | return omap_dmic_select_fclk(dmic, clk_id, freq); | |
397 | else if (dir == SND_SOC_CLOCK_OUT) | |
398 | return omap_dmic_select_outclk(dmic, clk_id, freq); | |
399 | ||
400 | dev_err(dmic->dev, "invalid clock direction (%d)\n", dir); | |
401 | return -EINVAL; | |
402 | } | |
403 | ||
404 | static const struct snd_soc_dai_ops omap_dmic_dai_ops = { | |
405 | .startup = omap_dmic_dai_startup, | |
406 | .shutdown = omap_dmic_dai_shutdown, | |
407 | .hw_params = omap_dmic_dai_hw_params, | |
408 | .prepare = omap_dmic_dai_prepare, | |
409 | .trigger = omap_dmic_dai_trigger, | |
410 | .set_sysclk = omap_dmic_set_dai_sysclk, | |
411 | }; | |
412 | ||
413 | static int omap_dmic_probe(struct snd_soc_dai *dai) | |
414 | { | |
415 | struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); | |
416 | ||
417 | pm_runtime_enable(dmic->dev); | |
418 | ||
419 | /* Disable lines while request is ongoing */ | |
420 | pm_runtime_get_sync(dmic->dev); | |
421 | omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00); | |
422 | pm_runtime_put_sync(dmic->dev); | |
423 | ||
424 | /* Configure DMIC threshold value */ | |
425 | dmic->threshold = OMAP_DMIC_THRES_MAX - 3; | |
426 | return 0; | |
427 | } | |
428 | ||
429 | static int omap_dmic_remove(struct snd_soc_dai *dai) | |
430 | { | |
431 | struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); | |
432 | ||
433 | pm_runtime_disable(dmic->dev); | |
434 | ||
435 | return 0; | |
436 | } | |
437 | ||
438 | static struct snd_soc_dai_driver omap_dmic_dai = { | |
439 | .name = "omap-dmic", | |
440 | .probe = omap_dmic_probe, | |
441 | .remove = omap_dmic_remove, | |
442 | .capture = { | |
443 | .channels_min = 2, | |
444 | .channels_max = 6, | |
445 | .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000, | |
446 | .formats = SNDRV_PCM_FMTBIT_S32_LE, | |
7df6f255 | 447 | .sig_bits = 24, |
fd26f947 PU |
448 | }, |
449 | .ops = &omap_dmic_dai_ops, | |
450 | }; | |
451 | ||
452 | static __devinit int asoc_dmic_probe(struct platform_device *pdev) | |
453 | { | |
454 | struct omap_dmic *dmic; | |
455 | struct resource *res; | |
456 | int ret; | |
457 | ||
458 | dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL); | |
459 | if (!dmic) | |
460 | return -ENOMEM; | |
461 | ||
462 | platform_set_drvdata(pdev, dmic); | |
463 | dmic->dev = &pdev->dev; | |
464 | dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS; | |
465 | ||
466 | mutex_init(&dmic->mutex); | |
467 | ||
468 | dmic->fclk = clk_get(dmic->dev, "dmic_fck"); | |
469 | if (IS_ERR(dmic->fclk)) { | |
470 | dev_err(dmic->dev, "cant get dmic_fck\n"); | |
471 | return -ENODEV; | |
472 | } | |
473 | ||
474 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); | |
475 | if (!res) { | |
476 | dev_err(dmic->dev, "invalid dma memory resource\n"); | |
477 | ret = -ENODEV; | |
478 | goto err_put_clk; | |
479 | } | |
480 | omap_dmic_dai_dma_params.port_addr = res->start + OMAP_DMIC_DATA_REG; | |
481 | ||
482 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
483 | if (!res) { | |
484 | dev_err(dmic->dev, "invalid dma resource\n"); | |
485 | ret = -ENODEV; | |
486 | goto err_put_clk; | |
487 | } | |
488 | omap_dmic_dai_dma_params.dma_req = res->start; | |
489 | ||
490 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); | |
491 | if (!res) { | |
492 | dev_err(dmic->dev, "invalid memory resource\n"); | |
493 | ret = -ENODEV; | |
494 | goto err_put_clk; | |
495 | } | |
496 | ||
497 | if (!devm_request_mem_region(&pdev->dev, res->start, | |
498 | resource_size(res), pdev->name)) { | |
499 | dev_err(dmic->dev, "memory region already claimed\n"); | |
500 | ret = -ENODEV; | |
501 | goto err_put_clk; | |
502 | } | |
503 | ||
504 | dmic->io_base = devm_ioremap(&pdev->dev, res->start, | |
505 | resource_size(res)); | |
506 | if (!dmic->io_base) { | |
507 | ret = -ENOMEM; | |
508 | goto err_put_clk; | |
509 | } | |
510 | ||
511 | ret = snd_soc_register_dai(&pdev->dev, &omap_dmic_dai); | |
512 | if (ret) | |
513 | goto err_put_clk; | |
514 | ||
515 | return 0; | |
516 | ||
517 | err_put_clk: | |
518 | clk_put(dmic->fclk); | |
519 | return ret; | |
520 | } | |
521 | ||
522 | static int __devexit asoc_dmic_remove(struct platform_device *pdev) | |
523 | { | |
524 | struct omap_dmic *dmic = platform_get_drvdata(pdev); | |
525 | ||
526 | snd_soc_unregister_dai(&pdev->dev); | |
527 | clk_put(dmic->fclk); | |
528 | ||
529 | return 0; | |
530 | } | |
531 | ||
2ec1be37 PU |
532 | static const struct of_device_id omap_dmic_of_match[] = { |
533 | { .compatible = "ti,omap4-dmic", }, | |
534 | { } | |
535 | }; | |
536 | MODULE_DEVICE_TABLE(of, omap_dmic_of_match); | |
537 | ||
fd26f947 PU |
538 | static struct platform_driver asoc_dmic_driver = { |
539 | .driver = { | |
540 | .name = "omap-dmic", | |
541 | .owner = THIS_MODULE, | |
2ec1be37 | 542 | .of_match_table = omap_dmic_of_match, |
fd26f947 PU |
543 | }, |
544 | .probe = asoc_dmic_probe, | |
545 | .remove = __devexit_p(asoc_dmic_remove), | |
546 | }; | |
547 | ||
548 | module_platform_driver(asoc_dmic_driver); | |
549 | ||
550 | MODULE_ALIAS("platform:omap-dmic"); | |
551 | MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); | |
552 | MODULE_DESCRIPTION("OMAP DMIC ASoC Interface"); | |
553 | MODULE_LICENSE("GPL"); |