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ASoC: Hook up microphone jack detection on 1133-EV1 board
[deliverable/linux.git] / sound / soc / omap / omap-mcbsp.c
CommitLineData
2e74796a
JN		 1/*
2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
3 *
4 * Copyright (C) 2008 Nokia Corporation
5 *
b08f7a62
JN		 6 * Contact: Jarkko Nikula <jhnikula@gmail.com>
7 * Peter Ujfalusi <peter.ujfalusi@nokia.com>
2e74796a
JN		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/device.h>
28#include <sound/core.h>
29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/initval.h>
32#include <sound/soc.h>
33
ce491cf8
TL		 34#include <plat/control.h>
35#include <plat/dma.h>
36#include <plat/mcbsp.h>
2e74796a
JN		 37#include "omap-mcbsp.h"
38#include "omap-pcm.h"
39
0b604856 40#define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
2e74796a 41
83905c13
IK		 42#define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
43 xhandler_get, xhandler_put) \
44{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
45 .info = omap_mcbsp_st_info_volsw, \
46 .get = xhandler_get, .put = xhandler_put, \
47 .private_value = (unsigned long) &(struct soc_mixer_control) \
48 {.min = xmin, .max = xmax} }
49
2e74796a
JN		 50struct omap_mcbsp_data {
51 unsigned int bus_id;
52 struct omap_mcbsp_reg_cfg regs;
ba9d0fd0 53 unsigned int fmt;
2e74796a
JN		 54 /*
55 * Flags indicating is the bus already activated and configured by
56 * another substream
57 */
58 int active;
59 int configured;
5f63ef99
GG		 60 unsigned int in_freq;
61 int clk_div;
2e74796a
JN		 62};
63
64#define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
65
66static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
67
68/*
69 * Stream DMA parameters. DMA request line and port address are set runtime
70 * since they are different between OMAP1 and later OMAPs
71 */
2e89713a 72static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
2e74796a
JN		 73
74#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
75static const int omap1_dma_reqs[][2] = {
76 { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
77 { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
78 { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
79};
80static const unsigned long omap1_mcbsp_port[][2] = {
81 { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
82 OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
83 { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
84 OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
85 { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
86 OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
87};
88#else
89static const int omap1_dma_reqs[][2] = {};
90static const unsigned long omap1_mcbsp_port[][2] = {};
91#endif
406e2c48 92
a8eb7ca0 93#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
406e2c48 94static const int omap24xx_dma_reqs[][2] = {
2e74796a
JN		 95 { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
96 { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
a8eb7ca0 97#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
406e2c48
JN		 98 { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
99 { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
100 { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
101#endif
2e74796a 102};
406e2c48
JN		 103#else
104static const int omap24xx_dma_reqs[][2] = {};
105#endif
106
107#if defined(CONFIG_ARCH_OMAP2420)
2e74796a
JN		 108static const unsigned long omap2420_mcbsp_port[][2] = {
109 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
110 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
111 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
112 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
113};
114#else
2e74796a
JN		 115static const unsigned long omap2420_mcbsp_port[][2] = {};
116#endif
117
406e2c48
JN		 118#if defined(CONFIG_ARCH_OMAP2430)
119static const unsigned long omap2430_mcbsp_port[][2] = {
120 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
121 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
122 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
123 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
124 { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
125 OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
126 { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
127 OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
128 { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
129 OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
130};
131#else
132static const unsigned long omap2430_mcbsp_port[][2] = {};
133#endif
134
a8eb7ca0 135#if defined(CONFIG_ARCH_OMAP3)
406e2c48
JN		 136static const unsigned long omap34xx_mcbsp_port[][2] = {
137 { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
138 OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
139 { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
140 OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
141 { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
142 OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
143 { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
144 OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
145 { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
146 OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
147};
148#else
149static const unsigned long omap34xx_mcbsp_port[][2] = {};
150#endif
151
caebc0cb
EV		 152static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
153{
154 struct snd_soc_pcm_runtime *rtd = substream->private_data;
155 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
156 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
a0a499c5
EV		 157 int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
158 int samples;
159
160 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
161 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
162 samples = snd_pcm_lib_period_bytes(substream) >> 1;
163 else
164 samples = 1;
caebc0cb
EV		 165
166 /* Configure McBSP internal buffer usage */
167 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
168 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, samples - 1);
169 else
170 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, samples - 1);
171}
172
dee89c4d
MB		 173static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
174 struct snd_soc_dai *dai)
2e74796a
JN		 175{
176 struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b 177 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a 178 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
caebc0cb 179 int bus_id = mcbsp_data->bus_id;
2e74796a
JN		 180 int err = 0;
181
caebc0cb
EV		 182 if (!cpu_dai->active)
183 err = omap_mcbsp_request(bus_id);
184
185 if (cpu_is_omap343x()) {
a0a499c5 186 int dma_op_mode = omap_mcbsp_get_dma_op_mode(bus_id);
caebc0cb
EV		 187 int max_period;
188
6984992b
JN		 189 /*
190 * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
191 * Set constraint for minimum buffer size to the same than FIFO
192 * size in order to avoid underruns in playback startup because
193 * HW is keeping the DMA request active until FIFO is filled.
194 */
caebc0cb
EV		 195 if (bus_id == 1)
196 snd_pcm_hw_constraint_minmax(substream->runtime,
197 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
198 4096, UINT_MAX);
199
200 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
201 max_period = omap_mcbsp_get_max_tx_threshold(bus_id);
202 else
203 max_period = omap_mcbsp_get_max_rx_threshold(bus_id);
204
205 max_period++;
206 max_period <<= 1;
207
a0a499c5
EV		 208 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
209 snd_pcm_hw_constraint_minmax(substream->runtime,
caebc0cb
EV		 210 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
211 32, max_period);
6984992b
JN		 212 }
213
2e74796a
JN		 214 return err;
215}
216
dee89c4d
MB		 217static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
218 struct snd_soc_dai *dai)
2e74796a
JN		 219{
220 struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b 221 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a
JN		 222 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
223
224 if (!cpu_dai->active) {
225 omap_mcbsp_free(mcbsp_data->bus_id);
226 mcbsp_data->configured = 0;
227 }
228}
229
dee89c4d
MB		 230static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
231 struct snd_soc_dai *dai)
2e74796a
JN		 232{
233 struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b 234 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a 235 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
c12abc01 236 int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
2e74796a
JN		 237
238 switch (cmd) {
239 case SNDRV_PCM_TRIGGER_START:
240 case SNDRV_PCM_TRIGGER_RESUME:
241 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
c12abc01
JN		 242 mcbsp_data->active++;
243 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
2e74796a
JN		 244 break;
245
246 case SNDRV_PCM_TRIGGER_STOP:
247 case SNDRV_PCM_TRIGGER_SUSPEND:
248 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
c12abc01
JN		 249 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
250 mcbsp_data->active--;
2e74796a
JN		 251 break;
252 default:
253 err = -EINVAL;
254 }
255
256 return err;
257}
258
75581d24
PU		 259static snd_pcm_sframes_t omap_mcbsp_dai_delay(
260 struct snd_pcm_substream *substream,
261 struct snd_soc_dai *dai)
262{
263 struct snd_soc_pcm_runtime *rtd = substream->private_data;
264 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
265 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
266 u16 fifo_use;
267 snd_pcm_sframes_t delay;
268
269 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
270 fifo_use = omap_mcbsp_get_tx_delay(mcbsp_data->bus_id);
271 else
272 fifo_use = omap_mcbsp_get_rx_delay(mcbsp_data->bus_id);
273
274 /*
275 * Divide the used locations with the channel count to get the
276 * FIFO usage in samples (don't care about partial samples in the
277 * buffer).
278 */
279 delay = fifo_use / substream->runtime->channels;
280
281 return delay;
282}
283
2e74796a 284static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 285 struct snd_pcm_hw_params *params,
286 struct snd_soc_dai *dai)
2e74796a
JN		 287{
288 struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b 289 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a
JN		 290 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
291 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
292 int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
caebc0cb 293 int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
2e74796a 294 unsigned long port;
5f63ef99 295 unsigned int format, div, framesize, master;
2e74796a
JN		 296
297 if (cpu_class_is_omap1()) {
298 dma = omap1_dma_reqs[bus_id][substream->stream];
299 port = omap1_mcbsp_port[bus_id][substream->stream];
300 } else if (cpu_is_omap2420()) {
406e2c48 301 dma = omap24xx_dma_reqs[bus_id][substream->stream];
2e74796a 302 port = omap2420_mcbsp_port[bus_id][substream->stream];
406e2c48
JN		 303 } else if (cpu_is_omap2430()) {
304 dma = omap24xx_dma_reqs[bus_id][substream->stream];
305 port = omap2430_mcbsp_port[bus_id][substream->stream];
306 } else if (cpu_is_omap343x()) {
307 dma = omap24xx_dma_reqs[bus_id][substream->stream];
308 port = omap34xx_mcbsp_port[bus_id][substream->stream];
caebc0cb
EV		 309 omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold =
310 omap_mcbsp_set_threshold;
a0a499c5
EV		 311 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
312 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
313 MCBSP_DMA_MODE_THRESHOLD)
314 sync_mode = OMAP_DMA_SYNC_FRAME;
2e74796a 315 } else {
2e74796a
JN		 316 return -ENODEV;
317 }
2e89713a
JN		 318 omap_mcbsp_dai_dma_params[id][substream->stream].name =
319 substream->stream ? "Audio Capture" : "Audio Playback";
2e74796a
JN		 320 omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
321 omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
caebc0cb 322 omap_mcbsp_dai_dma_params[id][substream->stream].sync_mode = sync_mode;
e17dd32f
MLC		 323 omap_mcbsp_dai_dma_params[id][substream->stream].data_type =
324 OMAP_DMA_DATA_TYPE_S16;
2e74796a
JN		 325 cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
326
327 if (mcbsp_data->configured) {
328 /* McBSP already configured by another stream */
329 return 0;
330 }
331
c29b206f
PU		 332 format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
333 wpf = channels = params_channels(params);
299a151f
PU		 334 if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
335 format == SND_SOC_DAIFMT_LEFT_J)) {
5f63ef99
GG		 336 /* Use dual-phase frames */
337 regs->rcr2 |= RPHASE;
338 regs->xcr2 |= XPHASE;
339 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
340 wpf--;
341 regs->rcr2 |= RFRLEN2(wpf - 1);
342 regs->xcr2 |= XFRLEN2(wpf - 1);
2e74796a
JN		 343 }
344
5f63ef99
GG		 345 regs->rcr1 |= RFRLEN1(wpf - 1);
346 regs->xcr1 |= XFRLEN1(wpf - 1);
347
2e74796a
JN		 348 switch (params_format(params)) {
349 case SNDRV_PCM_FORMAT_S16_LE:
350 /* Set word lengths */
ba9d0fd0 351 wlen = 16;
2e74796a
JN		 352 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
353 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
354 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
355 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
2e74796a
JN		 356 break;
357 default:
358 /* Unsupported PCM format */
359 return -EINVAL;
360 }
361
5f63ef99
GG		 362 /* In McBSP master modes, FRAME (i.e. sample rate) is generated
363 * by _counting_ BCLKs. Calculate frame size in BCLKs */
364 master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
365 if (master == SND_SOC_DAIFMT_CBS_CFS) {
366 div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
367 framesize = (mcbsp_data->in_freq / div) / params_rate(params);
368
369 if (framesize < wlen * channels) {
370 printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
371 "channels\n", __func__);
372 return -EINVAL;
373 }
374 } else
375 framesize = wlen * channels;
376
ba9d0fd0 377 /* Set FS period and length in terms of bit clock periods */
c29b206f 378 switch (format) {
ba9d0fd0 379 case SND_SOC_DAIFMT_I2S:
299a151f 380 case SND_SOC_DAIFMT_LEFT_J:
5f63ef99
GG		 381 regs->srgr2 |= FPER(framesize - 1);
382 regs->srgr1 |= FWID((framesize >> 1) - 1);
ba9d0fd0 383 break;
3ba191ce 384 case SND_SOC_DAIFMT_DSP_A:
bd25867a 385 case SND_SOC_DAIFMT_DSP_B:
5f63ef99 386 regs->srgr2 |= FPER(framesize - 1);
36ce8582 387 regs->srgr1 |= FWID(0);
ba9d0fd0
JN		 388 break;
389 }
390
2e74796a
JN		 391 omap_mcbsp_config(bus_id, &mcbsp_data->regs);
392 mcbsp_data->configured = 1;
393
394 return 0;
395}
396
397/*
398 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
399 * cache is initialized here
400 */
8687eb8b 401static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
2e74796a
JN		 402 unsigned int fmt)
403{
404 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
405 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
36ce8582 406 unsigned int temp_fmt = fmt;
2e74796a
JN		 407
408 if (mcbsp_data->configured)
409 return 0;
410
ba9d0fd0 411 mcbsp_data->fmt = fmt;
2e74796a
JN		 412 memset(regs, 0, sizeof(*regs));
413 /* Generic McBSP register settings */
414 regs->spcr2 |= XINTM(3) | FREE;
415 regs->spcr1 |= RINTM(3);
c721bbda
EN		 416 /* RFIG and XFIG are not defined in 34xx */
417 if (!cpu_is_omap34xx()) {
418 regs->rcr2 |= RFIG;
419 regs->xcr2 |= XFIG;
420 }
ef390c0b 421 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
32080af7
JN		 422 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
423 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
ef390c0b 424 }
2e74796a
JN		 425
426 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
427 case SND_SOC_DAIFMT_I2S:
428 /* 1-bit data delay */
429 regs->rcr2 |= RDATDLY(1);
430 regs->xcr2 |= XDATDLY(1);
431 break;
299a151f
PU		 432 case SND_SOC_DAIFMT_LEFT_J:
433 /* 0-bit data delay */
434 regs->rcr2 |= RDATDLY(0);
435 regs->xcr2 |= XDATDLY(0);
436 regs->spcr1 |= RJUST(2);
437 /* Invert FS polarity configuration */
438 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
439 break;
3ba191ce
PU		 440 case SND_SOC_DAIFMT_DSP_A:
441 /* 1-bit data delay */
442 regs->rcr2 |= RDATDLY(1);
443 regs->xcr2 |= XDATDLY(1);
444 /* Invert FS polarity configuration */
445 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
446 break;
bd25867a 447 case SND_SOC_DAIFMT_DSP_B:
3336c5b5
AK		 448 /* 0-bit data delay */
449 regs->rcr2 |= RDATDLY(0);
450 regs->xcr2 |= XDATDLY(0);
36ce8582
JN		 451 /* Invert FS polarity configuration */
452 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
3336c5b5 453 break;
2e74796a
JN		 454 default:
455 /* Unsupported data format */
456 return -EINVAL;
457 }
458
459 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
460 case SND_SOC_DAIFMT_CBS_CFS:
461 /* McBSP master. Set FS and bit clocks as outputs */
462 regs->pcr0 |= FSXM | FSRM |
463 CLKXM | CLKRM;
464 /* Sample rate generator drives the FS */
465 regs->srgr2 |= FSGM;
466 break;
467 case SND_SOC_DAIFMT_CBM_CFM:
468 /* McBSP slave */
469 break;
470 default:
471 /* Unsupported master/slave configuration */
472 return -EINVAL;
473 }
474
475 /* Set bit clock (CLKX/CLKR) and FS polarities */
36ce8582 476 switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
2e74796a
JN		 477 case SND_SOC_DAIFMT_NB_NF:
478 /*
479 * Normal BCLK + FS.
480 * FS active low. TX data driven on falling edge of bit clock
481 * and RX data sampled on rising edge of bit clock.
482 */
483 regs->pcr0 |= FSXP | FSRP |
484 CLKXP | CLKRP;
485 break;
486 case SND_SOC_DAIFMT_NB_IF:
487 regs->pcr0 |= CLKXP | CLKRP;
488 break;
489 case SND_SOC_DAIFMT_IB_NF:
490 regs->pcr0 |= FSXP | FSRP;
491 break;
492 case SND_SOC_DAIFMT_IB_IF:
493 break;
494 default:
495 return -EINVAL;
496 }
497
498 return 0;
499}
500
8687eb8b 501static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
2e74796a
JN		 502 int div_id, int div)
503{
504 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
505 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
506
507 if (div_id != OMAP_MCBSP_CLKGDV)
508 return -ENODEV;
509
5f63ef99 510 mcbsp_data->clk_div = div;
2e74796a
JN		 511 regs->srgr1 |= CLKGDV(div - 1);
512
513 return 0;
514}
515
516static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
517 int clk_id)
518{
519 int sel_bit;
406e2c48 520 u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
2e74796a
JN		 521
522 if (cpu_class_is_omap1()) {
523 /* OMAP1's can use only external source clock */
524 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
525 return -EINVAL;
526 else
527 return 0;
528 }
529
406e2c48
JN		 530 if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
531 return -EINVAL;
532
533 if (cpu_is_omap343x())
534 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
535
2e74796a
JN		 536 switch (mcbsp_data->bus_id) {
537 case 0:
538 reg = OMAP2_CONTROL_DEVCONF0;
539 sel_bit = 2;
540 break;
541 case 1:
542 reg = OMAP2_CONTROL_DEVCONF0;
543 sel_bit = 6;
544 break;
406e2c48
JN		 545 case 2:
546 reg = reg_devconf1;
547 sel_bit = 0;
548 break;
549 case 3:
550 reg = reg_devconf1;
551 sel_bit = 2;
552 break;
553 case 4:
554 reg = reg_devconf1;
555 sel_bit = 4;
556 break;
2e74796a
JN		 557 default:
558 return -EINVAL;
559 }
560
406e2c48
JN		 561 if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
562 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
563 else
564 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
2e74796a
JN		 565
566 return 0;
567}
568
d2c0bdaa
JN		 569static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data,
570 int clk_id)
571{
572 int sel_bit, set = 0;
573 u16 reg = OMAP2_CONTROL_DEVCONF0;
574
575 if (cpu_class_is_omap1())
576 return -EINVAL; /* TODO: Can this be implemented for OMAP1? */
577 if (mcbsp_data->bus_id != 0)
578 return -EINVAL;
579
580 switch (clk_id) {
581 case OMAP_MCBSP_CLKR_SRC_CLKX:
582 set = 1;
583 case OMAP_MCBSP_CLKR_SRC_CLKR:
584 sel_bit = 3;
585 break;
586 case OMAP_MCBSP_FSR_SRC_FSX:
587 set = 1;
588 case OMAP_MCBSP_FSR_SRC_FSR:
589 sel_bit = 4;
590 break;
591 default:
592 return -EINVAL;
593 }
594
595 if (set)
596 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
597 else
598 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
599
600 return 0;
601}
602
8687eb8b 603static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
2e74796a
JN		 604 int clk_id, unsigned int freq,
605 int dir)
606{
607 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
608 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
609 int err = 0;
610
5f63ef99
GG		 611 mcbsp_data->in_freq = freq;
612
2e74796a
JN		 613 switch (clk_id) {
614 case OMAP_MCBSP_SYSCLK_CLK:
615 regs->srgr2 |= CLKSM;
616 break;
617 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
618 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
619 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
620 break;
621
622 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
623 regs->srgr2 |= CLKSM;
624 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
625 regs->pcr0 |= SCLKME;
626 break;
d2c0bdaa
JN		 627
628 case OMAP_MCBSP_CLKR_SRC_CLKR:
629 case OMAP_MCBSP_CLKR_SRC_CLKX:
630 case OMAP_MCBSP_FSR_SRC_FSR:
631 case OMAP_MCBSP_FSR_SRC_FSX:
632 err = omap_mcbsp_dai_set_rcvr_src(mcbsp_data, clk_id);
633 break;
2e74796a
JN		 634 default:
635 err = -ENODEV;
636 }
637
638 return err;
639}
640
6335d055
EM		 641static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
642 .startup = omap_mcbsp_dai_startup,
643 .shutdown = omap_mcbsp_dai_shutdown,
644 .trigger = omap_mcbsp_dai_trigger,
75581d24 645 .delay = omap_mcbsp_dai_delay,
6335d055
EM		 646 .hw_params = omap_mcbsp_dai_hw_params,
647 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
648 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
649 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
650};
651
8def464d
JN		 652#define OMAP_MCBSP_DAI_BUILDER(link_id) \
653{ \
0c758bdd 654 .name = "omap-mcbsp-dai-"#link_id, \
8def464d 655 .id = (link_id), \
8def464d 656 .playback = { \
375e8a7c 657 .channels_min = 1, \
5f63ef99 658 .channels_max = 16, \
8def464d
JN		 659 .rates = OMAP_MCBSP_RATES, \
660 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
661 }, \
662 .capture = { \
375e8a7c 663 .channels_min = 1, \
5f63ef99 664 .channels_max = 16, \
8def464d
JN		 665 .rates = OMAP_MCBSP_RATES, \
666 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
667 }, \
6335d055 668 .ops = &omap_mcbsp_dai_ops, \
8def464d
JN		 669 .private_data = &mcbsp_data[(link_id)].bus_id, \
670}
671
672struct snd_soc_dai omap_mcbsp_dai[] = {
673 OMAP_MCBSP_DAI_BUILDER(0),
674 OMAP_MCBSP_DAI_BUILDER(1),
675#if NUM_LINKS >= 3
676 OMAP_MCBSP_DAI_BUILDER(2),
677#endif
678#if NUM_LINKS == 5
679 OMAP_MCBSP_DAI_BUILDER(3),
680 OMAP_MCBSP_DAI_BUILDER(4),
681#endif
2e74796a 682};
8def464d 683
2e74796a
JN		 684EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
685
83905c13
IK		 686int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
687 struct snd_ctl_elem_info *uinfo)
688{
689 struct soc_mixer_control *mc =
690 (struct soc_mixer_control *)kcontrol->private_value;
691 int max = mc->max;
692 int min = mc->min;
693
694 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
695 uinfo->count = 1;
696 uinfo->value.integer.min = min;
697 uinfo->value.integer.max = max;
698 return 0;
699}
700
701#define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel) \
702static int \
703omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
704 struct snd_ctl_elem_value *uc) \
705{ \
706 struct soc_mixer_control *mc = \
707 (struct soc_mixer_control *)kc->private_value; \
708 int max = mc->max; \
709 int min = mc->min; \
710 int val = uc->value.integer.value[0]; \
711 \
712 if (val < min || val > max) \
713 return -EINVAL; \
714 \
715 /* OMAP McBSP implementation uses index values 0..4 */ \
716 return omap_st_set_chgain((id)-1, channel, val); \
717}
718
719#define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel) \
720static int \
721omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
722 struct snd_ctl_elem_value *uc) \
723{ \
724 s16 chgain; \
725 \
726 if (omap_st_get_chgain((id)-1, channel, &chgain)) \
727 return -EAGAIN; \
728 \
729 uc->value.integer.value[0] = chgain; \
730 return 0; \
731}
732
733OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
734OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
735OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
736OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
737OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
738OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
739OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
740OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
741
742static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
743 struct snd_ctl_elem_value *ucontrol)
744{
745 struct soc_mixer_control *mc =
746 (struct soc_mixer_control *)kcontrol->private_value;
747 u8 value = ucontrol->value.integer.value[0];
748
749 if (value == omap_st_is_enabled(mc->reg))
750 return 0;
751
752 if (value)
753 omap_st_enable(mc->reg);
754 else
755 omap_st_disable(mc->reg);
756
757 return 1;
758}
759
760static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
761 struct snd_ctl_elem_value *ucontrol)
762{
763 struct soc_mixer_control *mc =
764 (struct soc_mixer_control *)kcontrol->private_value;
765
766 ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg);
767 return 0;
768}
769
770static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
771 SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
772 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
773 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
774 -32768, 32767,
775 omap_mcbsp2_get_st_ch0_volume,
776 omap_mcbsp2_set_st_ch0_volume),
777 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
778 -32768, 32767,
779 omap_mcbsp2_get_st_ch1_volume,
780 omap_mcbsp2_set_st_ch1_volume),
781};
782
783static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
784 SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
785 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
786 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
787 -32768, 32767,
788 omap_mcbsp3_get_st_ch0_volume,
789 omap_mcbsp3_set_st_ch0_volume),
790 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
791 -32768, 32767,
792 omap_mcbsp3_get_st_ch1_volume,
793 omap_mcbsp3_set_st_ch1_volume),
794};
795
796int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id)
797{
798 if (!cpu_is_omap34xx())
799 return -ENODEV;
800
801 switch (mcbsp_id) {
802 case 1: /* McBSP 2 */
803 return snd_soc_add_controls(codec, omap_mcbsp2_st_controls,
804 ARRAY_SIZE(omap_mcbsp2_st_controls));
805 case 2: /* McBSP 3 */
806 return snd_soc_add_controls(codec, omap_mcbsp3_st_controls,
807 ARRAY_SIZE(omap_mcbsp3_st_controls));
808 default:
809 break;
810 }
811
812 return -EINVAL;
813}
814EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
815
f73f2a6a 816static int __init snd_omap_mcbsp_init(void)
3f4b783c
MB		 817{
818 return snd_soc_register_dais(omap_mcbsp_dai,
819 ARRAY_SIZE(omap_mcbsp_dai));
820}
f73f2a6a 821module_init(snd_omap_mcbsp_init);
3f4b783c 822
f73f2a6a 823static void __exit snd_omap_mcbsp_exit(void)
3f4b783c
MB		 824{
825 snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
826}
f73f2a6a 827module_exit(snd_omap_mcbsp_exit);
3f4b783c 828
b08f7a62 829MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
2e74796a
JN		 830MODULE_DESCRIPTION("OMAP I2S SoC Interface");
831MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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