[deliverable/linux.git] / sound / soc / omap / omap-mcbsp.c

/*
 * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
 *
 * Copyright (C) 2008 Nokia Corporation
 *
 * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include <mach/control.h>
#include <mach/dma.h>
#include <mach/mcbsp.h>
#include "omap-mcbsp.h"
#include "omap-pcm.h"

#define OMAP_MCBSP_RATES	(SNDRV_PCM_RATE_8000_96000)

struct omap_mcbsp_data {
	unsigned int			bus_id;
	struct omap_mcbsp_reg_cfg	regs;
	unsigned int			fmt;
	/*
	 * Flags indicating is the bus already activated and configured by
	 * another substream
	 */
	int				active;
	int				configured;
};

#define to_mcbsp(priv)	container_of((priv), struct omap_mcbsp_data, bus_id)

static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];

/*
 * Stream DMA parameters. DMA request line and port address are set runtime
 * since they are different between OMAP1 and later OMAPs
 */
static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];

#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
static const int omap1_dma_reqs[][2] = {
	{ OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
	{ OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
	{ OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
};
static const unsigned long omap1_mcbsp_port[][2] = {
	{ OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	{ OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
	{ OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
};
#else
static const int omap1_dma_reqs[][2] = {};
static const unsigned long omap1_mcbsp_port[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
static const int omap24xx_dma_reqs[][2] = {
	{ OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
	{ OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
	{ OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
	{ OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
	{ OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
#endif
};
#else
static const int omap24xx_dma_reqs[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP2420)
static const unsigned long omap2420_mcbsp_port[][2] = {
	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
};
#else
static const unsigned long omap2420_mcbsp_port[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP2430)
static const unsigned long omap2430_mcbsp_port[][2] = {
	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
};
#else
static const unsigned long omap2430_mcbsp_port[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP34XX)
static const unsigned long omap34xx_mcbsp_port[][2] = {
	{ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
};
#else
static const unsigned long omap34xx_mcbsp_port[][2] = {};
#endif

static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	int err = 0;

	if (cpu_is_omap343x() && mcbsp_data->bus_id == 1) {
		/*
		 * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
		 * Set constraint for minimum buffer size to the same than FIFO
		 * size in order to avoid underruns in playback startup because
		 * HW is keeping the DMA request active until FIFO is filled.
		 */
		snd_pcm_hw_constraint_minmax(substream->runtime,
			SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4096, UINT_MAX);
	}

	if (!cpu_dai->active)
		err = omap_mcbsp_request(mcbsp_data->bus_id);

	return err;
}

static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
				    struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);

	if (!cpu_dai->active) {
		omap_mcbsp_free(mcbsp_data->bus_id);
		mcbsp_data->configured = 0;
	}
}

static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
				  struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	int err = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (!mcbsp_data->active++)
			omap_mcbsp_start(mcbsp_data->bus_id);
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (!--mcbsp_data->active)
			omap_mcbsp_stop(mcbsp_data->bus_id);
		break;
	default:
		err = -EINVAL;
	}

	return err;
}

static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
	int wlen, channels;
	unsigned long port;

	if (cpu_class_is_omap1()) {
		dma = omap1_dma_reqs[bus_id][substream->stream];
		port = omap1_mcbsp_port[bus_id][substream->stream];
	} else if (cpu_is_omap2420()) {
		dma = omap24xx_dma_reqs[bus_id][substream->stream];
		port = omap2420_mcbsp_port[bus_id][substream->stream];
	} else if (cpu_is_omap2430()) {
		dma = omap24xx_dma_reqs[bus_id][substream->stream];
		port = omap2430_mcbsp_port[bus_id][substream->stream];
	} else if (cpu_is_omap343x()) {
		dma = omap24xx_dma_reqs[bus_id][substream->stream];
		port = omap34xx_mcbsp_port[bus_id][substream->stream];
	} else {
		return -ENODEV;
	}
	omap_mcbsp_dai_dma_params[id][substream->stream].name =
		substream->stream ? "Audio Capture" : "Audio Playback";
	omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
	omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
	cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];

	if (mcbsp_data->configured) {
		/* McBSP already configured by another stream */
		return 0;
	}

	channels = params_channels(params);
	switch (channels) {
	case 2:
		/* Use dual-phase frames */
		regs->rcr2	|= RPHASE;
		regs->xcr2	|= XPHASE;
	case 1:
		/* Set 1 word per (McBSP) frame */
		regs->rcr2	|= RFRLEN2(1 - 1);
		regs->rcr1	|= RFRLEN1(1 - 1);
		regs->xcr2	|= XFRLEN2(1 - 1);
		regs->xcr1	|= XFRLEN1(1 - 1);
		break;
	default:
		/* Unsupported number of channels */
		return -EINVAL;
	}

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		/* Set word lengths */
		wlen = 16;
		regs->rcr2	|= RWDLEN2(OMAP_MCBSP_WORD_16);
		regs->rcr1	|= RWDLEN1(OMAP_MCBSP_WORD_16);
		regs->xcr2	|= XWDLEN2(OMAP_MCBSP_WORD_16);
		regs->xcr1	|= XWDLEN1(OMAP_MCBSP_WORD_16);
		break;
	default:
		/* Unsupported PCM format */
		return -EINVAL;
	}

	/* Set FS period and length in terms of bit clock periods */
	switch (mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		regs->srgr2	|= FPER(wlen * 2 - 1);
		regs->srgr1	|= FWID(wlen - 1);
		break;
	case SND_SOC_DAIFMT_DSP_B:
		regs->srgr2	|= FPER(wlen * channels - 1);
		regs->srgr1	|= FWID(0);
		break;
	}

	omap_mcbsp_config(bus_id, &mcbsp_data->regs);
	mcbsp_data->configured = 1;

	return 0;
}

/*
 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 * cache is initialized here
 */
static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
				      unsigned int fmt)
{
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	unsigned int temp_fmt = fmt;

	if (mcbsp_data->configured)
		return 0;

	mcbsp_data->fmt = fmt;
	memset(regs, 0, sizeof(*regs));
	/* Generic McBSP register settings */
	regs->spcr2	|= XINTM(3) | FREE;
	regs->spcr1	|= RINTM(3);
	regs->rcr2	|= RFIG;
	regs->xcr2	|= XFIG;
	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
		regs->xccr = DXENDLY(1) | XDMAEN;
		regs->rccr = RFULL_CYCLE | RDMAEN;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		/* 1-bit data delay */
		regs->rcr2	|= RDATDLY(1);
		regs->xcr2	|= XDATDLY(1);
		break;
	case SND_SOC_DAIFMT_DSP_B:
		/* 0-bit data delay */
		regs->rcr2      |= RDATDLY(0);
		regs->xcr2      |= XDATDLY(0);
		/* Invert FS polarity configuration */
		temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
		break;
	default:
		/* Unsupported data format */
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* McBSP master. Set FS and bit clocks as outputs */
		regs->pcr0	|= FSXM | FSRM |
				   CLKXM | CLKRM;
		/* Sample rate generator drives the FS */
		regs->srgr2	|= FSGM;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		/* McBSP slave */
		break;
	default:
		/* Unsupported master/slave configuration */
		return -EINVAL;
	}

	/* Set bit clock (CLKX/CLKR) and FS polarities */
	switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		/*
		 * Normal BCLK + FS.
		 * FS active low. TX data driven on falling edge of bit clock
		 * and RX data sampled on rising edge of bit clock.
		 */
		regs->pcr0	|= FSXP | FSRP |
				   CLKXP | CLKRP;
		break;
	case SND_SOC_DAIFMT_NB_IF:
		regs->pcr0	|= CLKXP | CLKRP;
		break;
	case SND_SOC_DAIFMT_IB_NF:
		regs->pcr0	|= FSXP | FSRP;
		break;
	case SND_SOC_DAIFMT_IB_IF:
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
				     int div_id, int div)
{
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;

	if (div_id != OMAP_MCBSP_CLKGDV)
		return -ENODEV;

	regs->srgr1	|= CLKGDV(div - 1);

	return 0;
}

static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
				       int clk_id)
{
	int sel_bit;
	u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;

	if (cpu_class_is_omap1()) {
		/* OMAP1's can use only external source clock */
		if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
			return -EINVAL;
		else
			return 0;
	}

	if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
		return -EINVAL;

	if (cpu_is_omap343x())
		reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;

	switch (mcbsp_data->bus_id) {
	case 0:
		reg = OMAP2_CONTROL_DEVCONF0;
		sel_bit = 2;
		break;
	case 1:
		reg = OMAP2_CONTROL_DEVCONF0;
		sel_bit = 6;
		break;
	case 2:
		reg = reg_devconf1;
		sel_bit = 0;
		break;
	case 3:
		reg = reg_devconf1;
		sel_bit = 2;
		break;
	case 4:
		reg = reg_devconf1;
		sel_bit = 4;
		break;
	default:
		return -EINVAL;
	}

	if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
		omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
	else
		omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);

	return 0;
}

static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
					 int clk_id, unsigned int freq,
					 int dir)
{
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	int err = 0;

	switch (clk_id) {
	case OMAP_MCBSP_SYSCLK_CLK:
		regs->srgr2	|= CLKSM;
		break;
	case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
	case OMAP_MCBSP_SYSCLK_CLKS_EXT:
		err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
		break;

	case OMAP_MCBSP_SYSCLK_CLKX_EXT:
		regs->srgr2	|= CLKSM;
	case OMAP_MCBSP_SYSCLK_CLKR_EXT:
		regs->pcr0	|= SCLKME;
		break;
	default:
		err = -ENODEV;
	}

	return err;
}

static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
	.startup	= omap_mcbsp_dai_startup,
	.shutdown	= omap_mcbsp_dai_shutdown,
	.trigger	= omap_mcbsp_dai_trigger,
	.hw_params	= omap_mcbsp_dai_hw_params,
	.set_fmt	= omap_mcbsp_dai_set_dai_fmt,
	.set_clkdiv	= omap_mcbsp_dai_set_clkdiv,
	.set_sysclk	= omap_mcbsp_dai_set_dai_sysclk,
};

#define OMAP_MCBSP_DAI_BUILDER(link_id)				\
{								\
	.name = "omap-mcbsp-dai-"#link_id,			\
	.id = (link_id),					\
	.playback = {						\
		.channels_min = 1,				\
		.channels_max = 2,				\
		.rates = OMAP_MCBSP_RATES,			\
		.formats = SNDRV_PCM_FMTBIT_S16_LE,		\
	},							\
	.capture = {						\
		.channels_min = 1,				\
		.channels_max = 2,				\
		.rates = OMAP_MCBSP_RATES,			\
		.formats = SNDRV_PCM_FMTBIT_S16_LE,		\
	},							\
	.ops = &omap_mcbsp_dai_ops,				\
	.private_data = &mcbsp_data[(link_id)].bus_id,		\
}

struct snd_soc_dai omap_mcbsp_dai[] = {
	OMAP_MCBSP_DAI_BUILDER(0),
	OMAP_MCBSP_DAI_BUILDER(1),
#if NUM_LINKS >= 3
	OMAP_MCBSP_DAI_BUILDER(2),
#endif
#if NUM_LINKS == 5
	OMAP_MCBSP_DAI_BUILDER(3),
	OMAP_MCBSP_DAI_BUILDER(4),
#endif
};

EXPORT_SYMBOL_GPL(omap_mcbsp_dai);

static int __init snd_omap_mcbsp_init(void)
{
	return snd_soc_register_dais(omap_mcbsp_dai,
				     ARRAY_SIZE(omap_mcbsp_dai));
}
module_init(snd_omap_mcbsp_init);

static void __exit snd_omap_mcbsp_exit(void)
{
	snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
}
module_exit(snd_omap_mcbsp_exit);

MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
MODULE_DESCRIPTION("OMAP I2S SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
2e74796a JN	1	/*
	2	* omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
	3	*
	4	* Copyright (C) 2008 Nokia Corporation
	5	*
	6	* Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*
	22	*/
	23
	24	#include <linux/init.h>
	25	#include <linux/module.h>
	26	#include <linux/device.h>
	27	#include <sound/core.h>
	28	#include <sound/pcm.h>
	29	#include <sound/pcm_params.h>
	30	#include <sound/initval.h>
	31	#include <sound/soc.h>
	32
a09e64fb RK	33	#include <mach/control.h>
	34	#include <mach/dma.h>
	35	#include <mach/mcbsp.h>
2e74796a JN	36	#include "omap-mcbsp.h"
	37	#include "omap-pcm.h"
	38
0b604856	39	#define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
2e74796a JN	40
	41	struct omap_mcbsp_data {
	42	unsigned int bus_id;
	43	struct omap_mcbsp_reg_cfg regs;
ba9d0fd0	44	unsigned int fmt;
2e74796a JN	45	/*
	46	* Flags indicating is the bus already activated and configured by
	47	* another substream
	48	*/
	49	int active;
	50	int configured;
	51	};
	52
	53	#define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
	54
	55	static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
	56
	57	/*
	58	* Stream DMA parameters. DMA request line and port address are set runtime
	59	* since they are different between OMAP1 and later OMAPs
	60	*/
2e89713a	61	static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
2e74796a JN	62
	63	#if defined(CONFIG_ARCH_OMAP15XX) \|\| defined(CONFIG_ARCH_OMAP16XX)
	64	static const int omap1_dma_reqs[][2] = {
	65	{ OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
	66	{ OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
	67	{ OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
	68	};
	69	static const unsigned long omap1_mcbsp_port[][2] = {
	70	{ OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	71	OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	72	{ OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	73	OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
	74	{ OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
	75	OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
	76	};
	77	#else
	78	static const int omap1_dma_reqs[][2] = {};
	79	static const unsigned long omap1_mcbsp_port[][2] = {};
	80	#endif
406e2c48 JN	81
	82	#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
	83	static const int omap24xx_dma_reqs[][2] = {
2e74796a JN	84	{ OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
2e74796a JN	85	{ OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
406e2c48 JN	86	#if defined(CONFIG_ARCH_OMAP2430) \|\| defined(CONFIG_ARCH_OMAP34XX)
	87	{ OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
	88	{ OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
	89	{ OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
	90	#endif
2e74796a	91	};
406e2c48 JN	92	#else
	93	static const int omap24xx_dma_reqs[][2] = {};
	94	#endif
	95
	96	#if defined(CONFIG_ARCH_OMAP2420)
2e74796a JN	97	static const unsigned long omap2420_mcbsp_port[][2] = {
	98	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	99	OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	100	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	101	OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
	102	};
	103	#else
2e74796a JN	104	static const unsigned long omap2420_mcbsp_port[][2] = {};
	105	#endif
	106
406e2c48 JN	107	#if defined(CONFIG_ARCH_OMAP2430)
	108	static const unsigned long omap2430_mcbsp_port[][2] = {
	109	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	110	OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	111	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	112	OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	113	{ OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	114	OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	115	{ OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	116	OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	117	{ OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	118	OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
	119	};
	120	#else
	121	static const unsigned long omap2430_mcbsp_port[][2] = {};
	122	#endif
	123
	124	#if defined(CONFIG_ARCH_OMAP34XX)
	125	static const unsigned long omap34xx_mcbsp_port[][2] = {
	126	{ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	127	OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	128	{ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	129	OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	130	{ OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	131	OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	132	{ OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	133	OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	134	{ OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	135	OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
	136	};
	137	#else
	138	static const unsigned long omap34xx_mcbsp_port[][2] = {};
	139	#endif
	140
dee89c4d MB	141	static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
dee89c4d MB	142	struct snd_soc_dai *dai)
2e74796a JN	143	{
2e74796a JN	144	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	145	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	146	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	147	int err = 0;
	148
6984992b JN	149	if (cpu_is_omap343x() && mcbsp_data->bus_id == 1) {
	150	/*
	151	* McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
	152	* Set constraint for minimum buffer size to the same than FIFO
	153	* size in order to avoid underruns in playback startup because
	154	* HW is keeping the DMA request active until FIFO is filled.
	155	*/
	156	snd_pcm_hw_constraint_minmax(substream->runtime,
	157	SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4096, UINT_MAX);
	158	}
	159
2e74796a JN	160	if (!cpu_dai->active)
	161	err = omap_mcbsp_request(mcbsp_data->bus_id);
	162
	163	return err;
	164	}
	165
dee89c4d MB	166	static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
dee89c4d MB	167	struct snd_soc_dai *dai)
2e74796a JN	168	{
2e74796a JN	169	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	170	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	171	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	172
	173	if (!cpu_dai->active) {
	174	omap_mcbsp_free(mcbsp_data->bus_id);
	175	mcbsp_data->configured = 0;
	176	}
	177	}
	178
dee89c4d MB	179	static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
dee89c4d MB	180	struct snd_soc_dai *dai)
2e74796a JN	181	{
2e74796a JN	182	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	183	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	184	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	185	int err = 0;
	186
	187	switch (cmd) {
	188	case SNDRV_PCM_TRIGGER_START:
	189	case SNDRV_PCM_TRIGGER_RESUME:
	190	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	191	if (!mcbsp_data->active++)
	192	omap_mcbsp_start(mcbsp_data->bus_id);
	193	break;
	194
	195	case SNDRV_PCM_TRIGGER_STOP:
	196	case SNDRV_PCM_TRIGGER_SUSPEND:
	197	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	198	if (!--mcbsp_data->active)
	199	omap_mcbsp_stop(mcbsp_data->bus_id);
	200	break;
	201	default:
	202	err = -EINVAL;
	203	}
	204
	205	return err;
	206	}
	207
	208	static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	209	struct snd_pcm_hw_params *params,
dee89c4d MB	210	struct snd_soc_dai *dai)
2e74796a JN	211	{
2e74796a JN	212	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	213	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	214	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	215	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	216	int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
375e8a7c	217	int wlen, channels;
2e74796a JN	218	unsigned long port;
	219
	220	if (cpu_class_is_omap1()) {
	221	dma = omap1_dma_reqs[bus_id][substream->stream];
	222	port = omap1_mcbsp_port[bus_id][substream->stream];
	223	} else if (cpu_is_omap2420()) {
406e2c48	224	dma = omap24xx_dma_reqs[bus_id][substream->stream];
2e74796a	225	port = omap2420_mcbsp_port[bus_id][substream->stream];
406e2c48 JN	226	} else if (cpu_is_omap2430()) {
	227	dma = omap24xx_dma_reqs[bus_id][substream->stream];
	228	port = omap2430_mcbsp_port[bus_id][substream->stream];
	229	} else if (cpu_is_omap343x()) {
	230	dma = omap24xx_dma_reqs[bus_id][substream->stream];
	231	port = omap34xx_mcbsp_port[bus_id][substream->stream];
2e74796a	232	} else {
2e74796a JN	233	return -ENODEV;
2e74796a JN	234	}
2e89713a JN	235	omap_mcbsp_dai_dma_params[id][substream->stream].name =
2e89713a JN	236	substream->stream ? "Audio Capture" : "Audio Playback";
2e74796a JN	237	omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
	238	omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
	239	cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
	240
	241	if (mcbsp_data->configured) {
	242	/* McBSP already configured by another stream */
	243	return 0;
	244	}
	245
375e8a7c JN	246	channels = params_channels(params);
375e8a7c JN	247	switch (channels) {
2e74796a	248	case 2:
375e8a7c JN	249	/* Use dual-phase frames */
	250	regs->rcr2 \|= RPHASE;
	251	regs->xcr2 \|= XPHASE;
	252	case 1:
	253	/* Set 1 word per (McBSP) frame */
	254	regs->rcr2 \|= RFRLEN2(1 - 1);
2e74796a	255	regs->rcr1 \|= RFRLEN1(1 - 1);
375e8a7c	256	regs->xcr2 \|= XFRLEN2(1 - 1);
2e74796a JN	257	regs->xcr1 \|= XFRLEN1(1 - 1);
	258	break;
	259	default:
	260	/* Unsupported number of channels */
	261	return -EINVAL;
	262	}
	263
	264	switch (params_format(params)) {
	265	case SNDRV_PCM_FORMAT_S16_LE:
	266	/* Set word lengths */
ba9d0fd0	267	wlen = 16;
2e74796a JN	268	regs->rcr2 \|= RWDLEN2(OMAP_MCBSP_WORD_16);
	269	regs->rcr1 \|= RWDLEN1(OMAP_MCBSP_WORD_16);
	270	regs->xcr2 \|= XWDLEN2(OMAP_MCBSP_WORD_16);
	271	regs->xcr1 \|= XWDLEN1(OMAP_MCBSP_WORD_16);
2e74796a JN	272	break;
	273	default:
	274	/* Unsupported PCM format */
	275	return -EINVAL;
	276	}
	277
ba9d0fd0 JN	278	/* Set FS period and length in terms of bit clock periods */
	279	switch (mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	280	case SND_SOC_DAIFMT_I2S:
	281	regs->srgr2 \|= FPER(wlen * 2 - 1);
	282	regs->srgr1 \|= FWID(wlen - 1);
	283	break;
bd25867a	284	case SND_SOC_DAIFMT_DSP_B:
375e8a7c	285	regs->srgr2 \|= FPER(wlen * channels - 1);
36ce8582	286	regs->srgr1 \|= FWID(0);
ba9d0fd0 JN	287	break;
	288	}
	289
2e74796a JN	290	omap_mcbsp_config(bus_id, &mcbsp_data->regs);
	291	mcbsp_data->configured = 1;
	292
	293	return 0;
	294	}
	295
	296	/*
	297	* This must be called before _set_clkdiv and _set_sysclk since McBSP register
	298	* cache is initialized here
	299	*/
8687eb8b	300	static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
2e74796a JN	301	unsigned int fmt)
	302	{
	303	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	304	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
36ce8582	305	unsigned int temp_fmt = fmt;
2e74796a JN	306
	307	if (mcbsp_data->configured)
	308	return 0;
	309
ba9d0fd0	310	mcbsp_data->fmt = fmt;
2e74796a JN	311	memset(regs, 0, sizeof(*regs));
	312	/* Generic McBSP register settings */
	313	regs->spcr2 \|= XINTM(3) \| FREE;
	314	regs->spcr1 \|= RINTM(3);
	315	regs->rcr2 \|= RFIG;
	316	regs->xcr2 \|= XFIG;
ef390c0b MLC	317	if (cpu_is_omap2430() \|\| cpu_is_omap34xx()) {
	318	regs->xccr = DXENDLY(1) \| XDMAEN;
	319	regs->rccr = RFULL_CYCLE \| RDMAEN;
	320	}
2e74796a JN	321
	322	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	323	case SND_SOC_DAIFMT_I2S:
	324	/* 1-bit data delay */
	325	regs->rcr2 \|= RDATDLY(1);
	326	regs->xcr2 \|= XDATDLY(1);
	327	break;
bd25867a	328	case SND_SOC_DAIFMT_DSP_B:
3336c5b5 AK	329	/* 0-bit data delay */
	330	regs->rcr2 \|= RDATDLY(0);
	331	regs->xcr2 \|= XDATDLY(0);
36ce8582 JN	332	/* Invert FS polarity configuration */
36ce8582 JN	333	temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
3336c5b5	334	break;
2e74796a JN	335	default:
	336	/* Unsupported data format */
	337	return -EINVAL;
	338	}
	339
	340	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	341	case SND_SOC_DAIFMT_CBS_CFS:
	342	/* McBSP master. Set FS and bit clocks as outputs */
	343	regs->pcr0 \|= FSXM \| FSRM \|
	344	CLKXM \| CLKRM;
	345	/* Sample rate generator drives the FS */
	346	regs->srgr2 \|= FSGM;
	347	break;
	348	case SND_SOC_DAIFMT_CBM_CFM:
	349	/* McBSP slave */
	350	break;
	351	default:
	352	/* Unsupported master/slave configuration */
	353	return -EINVAL;
	354	}
	355
	356	/* Set bit clock (CLKX/CLKR) and FS polarities */
36ce8582	357	switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
2e74796a JN	358	case SND_SOC_DAIFMT_NB_NF:
	359	/*
	360	* Normal BCLK + FS.
	361	* FS active low. TX data driven on falling edge of bit clock
	362	* and RX data sampled on rising edge of bit clock.
	363	*/
	364	regs->pcr0 \|= FSXP \| FSRP \|
	365	CLKXP \| CLKRP;
	366	break;
	367	case SND_SOC_DAIFMT_NB_IF:
	368	regs->pcr0 \|= CLKXP \| CLKRP;
	369	break;
	370	case SND_SOC_DAIFMT_IB_NF:
	371	regs->pcr0 \|= FSXP \| FSRP;
	372	break;
	373	case SND_SOC_DAIFMT_IB_IF:
	374	break;
	375	default:
	376	return -EINVAL;
	377	}
	378
	379	return 0;
	380	}
	381
8687eb8b	382	static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
2e74796a JN	383	int div_id, int div)
	384	{
	385	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	386	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	387
	388	if (div_id != OMAP_MCBSP_CLKGDV)
	389	return -ENODEV;
	390
	391	regs->srgr1 \|= CLKGDV(div - 1);
	392
	393	return 0;
	394	}
	395
	396	static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
	397	int clk_id)
	398	{
	399	int sel_bit;
406e2c48	400	u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
2e74796a JN	401
	402	if (cpu_class_is_omap1()) {
	403	/* OMAP1's can use only external source clock */
	404	if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
	405	return -EINVAL;
	406	else
	407	return 0;
	408	}
	409
406e2c48 JN	410	if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
	411	return -EINVAL;
	412
	413	if (cpu_is_omap343x())
	414	reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
	415
2e74796a JN	416	switch (mcbsp_data->bus_id) {
	417	case 0:
	418	reg = OMAP2_CONTROL_DEVCONF0;
	419	sel_bit = 2;
	420	break;
	421	case 1:
	422	reg = OMAP2_CONTROL_DEVCONF0;
	423	sel_bit = 6;
	424	break;
406e2c48 JN	425	case 2:
	426	reg = reg_devconf1;
	427	sel_bit = 0;
	428	break;
	429	case 3:
	430	reg = reg_devconf1;
	431	sel_bit = 2;
	432	break;
	433	case 4:
	434	reg = reg_devconf1;
	435	sel_bit = 4;
	436	break;
2e74796a JN	437	default:
	438	return -EINVAL;
	439	}
	440
406e2c48 JN	441	if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
	442	omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
	443	else
	444	omap_ctrl_writel(omap_ctrl_readl(reg) \| (1 << sel_bit), reg);
2e74796a JN	445
	446	return 0;
	447	}
	448
8687eb8b	449	static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
2e74796a JN	450	int clk_id, unsigned int freq,
	451	int dir)
	452	{
	453	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	454	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	455	int err = 0;
	456
	457	switch (clk_id) {
	458	case OMAP_MCBSP_SYSCLK_CLK:
	459	regs->srgr2 \|= CLKSM;
	460	break;
	461	case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
	462	case OMAP_MCBSP_SYSCLK_CLKS_EXT:
	463	err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
	464	break;
	465
	466	case OMAP_MCBSP_SYSCLK_CLKX_EXT:
	467	regs->srgr2 \|= CLKSM;
	468	case OMAP_MCBSP_SYSCLK_CLKR_EXT:
	469	regs->pcr0 \|= SCLKME;
	470	break;
	471	default:
	472	err = -ENODEV;
	473	}
	474
	475	return err;
	476	}
	477
6335d055 EM	478	static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
	479	.startup = omap_mcbsp_dai_startup,
	480	.shutdown = omap_mcbsp_dai_shutdown,
	481	.trigger = omap_mcbsp_dai_trigger,
	482	.hw_params = omap_mcbsp_dai_hw_params,
	483	.set_fmt = omap_mcbsp_dai_set_dai_fmt,
	484	.set_clkdiv = omap_mcbsp_dai_set_clkdiv,
	485	.set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
	486	};
	487
8def464d JN	488	#define OMAP_MCBSP_DAI_BUILDER(link_id) \
8def464d JN	489	{ \
0c758bdd	490	.name = "omap-mcbsp-dai-"#link_id, \
8def464d	491	.id = (link_id), \
8def464d	492	.playback = { \
375e8a7c	493	.channels_min = 1, \
8def464d JN	494	.channels_max = 2, \
	495	.rates = OMAP_MCBSP_RATES, \
	496	.formats = SNDRV_PCM_FMTBIT_S16_LE, \
	497	}, \
	498	.capture = { \
375e8a7c	499	.channels_min = 1, \
8def464d JN	500	.channels_max = 2, \
	501	.rates = OMAP_MCBSP_RATES, \
	502	.formats = SNDRV_PCM_FMTBIT_S16_LE, \
	503	}, \
6335d055	504	.ops = &omap_mcbsp_dai_ops, \
8def464d JN	505	.private_data = &mcbsp_data[(link_id)].bus_id, \
	506	}
	507
	508	struct snd_soc_dai omap_mcbsp_dai[] = {
	509	OMAP_MCBSP_DAI_BUILDER(0),
	510	OMAP_MCBSP_DAI_BUILDER(1),
	511	#if NUM_LINKS >= 3
	512	OMAP_MCBSP_DAI_BUILDER(2),
	513	#endif
	514	#if NUM_LINKS == 5
	515	OMAP_MCBSP_DAI_BUILDER(3),
	516	OMAP_MCBSP_DAI_BUILDER(4),
	517	#endif
2e74796a	518	};
8def464d	519
2e74796a JN	520	EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
2e74796a JN	521
f73f2a6a	522	static int __init snd_omap_mcbsp_init(void)
3f4b783c MB	523	{
	524	return snd_soc_register_dais(omap_mcbsp_dai,
	525	ARRAY_SIZE(omap_mcbsp_dai));
	526	}
f73f2a6a	527	module_init(snd_omap_mcbsp_init);
3f4b783c	528
f73f2a6a	529	static void __exit snd_omap_mcbsp_exit(void)
3f4b783c MB	530	{
	531	snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
	532	}
f73f2a6a	533	module_exit(snd_omap_mcbsp_exit);
3f4b783c	534
2e74796a JN	535	MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
	536	MODULE_DESCRIPTION("OMAP I2S SoC Interface");
	537	MODULE_LICENSE("GPL");