Commit | Line | Data |
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2e74796a JN |
1 | /* |
2 | * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port | |
3 | * | |
4 | * Copyright (C) 2008 Nokia Corporation | |
5 | * | |
7ec41ee5 | 6 | * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com> |
56a87429 | 7 | * Peter Ujfalusi <peter.ujfalusi@ti.com> |
2e74796a JN |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <linux/init.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/device.h> | |
2ee65950 | 28 | #include <linux/pm_runtime.h> |
11dd5864 PU |
29 | #include <linux/of.h> |
30 | #include <linux/of_device.h> | |
2e74796a JN |
31 | #include <sound/core.h> |
32 | #include <sound/pcm.h> | |
33 | #include <sound/pcm_params.h> | |
34 | #include <sound/initval.h> | |
35 | #include <sound/soc.h> | |
09ae3aaf | 36 | #include <sound/dmaengine_pcm.h> |
2e74796a | 37 | |
2203747c | 38 | #include <linux/platform_data/asoc-ti-mcbsp.h> |
219f4316 | 39 | #include "mcbsp.h" |
2e74796a | 40 | #include "omap-mcbsp.h" |
2e74796a | 41 | |
0b604856 | 42 | #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000) |
2e74796a | 43 | |
83905c13 IK |
44 | #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \ |
45 | xhandler_get, xhandler_put) \ | |
46 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
47 | .info = omap_mcbsp_st_info_volsw, \ | |
48 | .get = xhandler_get, .put = xhandler_put, \ | |
49 | .private_value = (unsigned long) &(struct soc_mixer_control) \ | |
50 | {.min = xmin, .max = xmax} } | |
51 | ||
219f4316 PU |
52 | enum { |
53 | OMAP_MCBSP_WORD_8 = 0, | |
54 | OMAP_MCBSP_WORD_12, | |
55 | OMAP_MCBSP_WORD_16, | |
56 | OMAP_MCBSP_WORD_20, | |
57 | OMAP_MCBSP_WORD_24, | |
58 | OMAP_MCBSP_WORD_32, | |
59 | }; | |
60 | ||
2e74796a JN |
61 | /* |
62 | * Stream DMA parameters. DMA request line and port address are set runtime | |
63 | * since they are different between OMAP1 and later OMAPs | |
64 | */ | |
abe99370 LPC |
65 | static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream, |
66 | unsigned int packet_size) | |
caebc0cb EV |
67 | { |
68 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 69 | struct snd_soc_dai *cpu_dai = rtd->cpu_dai; |
45656b44 | 70 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
3f024039 | 71 | int words; |
a0a499c5 | 72 | |
778a17c3 PU |
73 | /* |
74 | * Configure McBSP threshold based on either: | |
75 | * packet_size, when the sDMA is in packet mode, or based on the | |
76 | * period size in THRESHOLD mode, otherwise use McBSP threshold = 1 | |
77 | * for mono streams. | |
78 | */ | |
abe99370 LPC |
79 | if (packet_size) |
80 | words = packet_size; | |
a0a499c5 | 81 | else |
3f024039 | 82 | words = 1; |
caebc0cb EV |
83 | |
84 | /* Configure McBSP internal buffer usage */ | |
85 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
45656b44 | 86 | omap_mcbsp_set_tx_threshold(mcbsp, words); |
caebc0cb | 87 | else |
45656b44 | 88 | omap_mcbsp_set_rx_threshold(mcbsp, words); |
caebc0cb EV |
89 | } |
90 | ||
ddc29b01 PU |
91 | static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params, |
92 | struct snd_pcm_hw_rule *rule) | |
93 | { | |
94 | struct snd_interval *buffer_size = hw_param_interval(params, | |
95 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE); | |
96 | struct snd_interval *channels = hw_param_interval(params, | |
97 | SNDRV_PCM_HW_PARAM_CHANNELS); | |
45656b44 | 98 | struct omap_mcbsp *mcbsp = rule->private; |
ddc29b01 PU |
99 | struct snd_interval frames; |
100 | int size; | |
101 | ||
102 | snd_interval_any(&frames); | |
cb40b63a | 103 | size = mcbsp->pdata->buffer_size; |
ddc29b01 PU |
104 | |
105 | frames.min = size / channels->min; | |
106 | frames.integer = 1; | |
107 | return snd_interval_refine(buffer_size, &frames); | |
108 | } | |
109 | ||
dee89c4d | 110 | static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream, |
f0fba2ad | 111 | struct snd_soc_dai *cpu_dai) |
2e74796a | 112 | { |
45656b44 | 113 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
2e74796a JN |
114 | int err = 0; |
115 | ||
caebc0cb | 116 | if (!cpu_dai->active) |
45656b44 | 117 | err = omap_mcbsp_request(mcbsp); |
caebc0cb | 118 | |
ddc29b01 PU |
119 | /* |
120 | * OMAP3 McBSP FIFO is word structured. | |
121 | * McBSP2 has 1024 + 256 = 1280 word long buffer, | |
122 | * McBSP1,3,4,5 has 128 word long buffer | |
123 | * This means that the size of the FIFO depends on the sample format. | |
124 | * For example on McBSP3: | |
125 | * 16bit samples: size is 128 * 2 = 256 bytes | |
126 | * 32bit samples: size is 128 * 4 = 512 bytes | |
127 | * It is simpler to place constraint for buffer and period based on | |
128 | * channels. | |
129 | * McBSP3 as example again (16 or 32 bit samples): | |
130 | * 1 channel (mono): size is 128 frames (128 words) | |
131 | * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words) | |
132 | * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words) | |
133 | */ | |
45656b44 | 134 | if (mcbsp->pdata->buffer_size) { |
6984992b | 135 | /* |
998a8a69 | 136 | * Rule for the buffer size. We should not allow |
ce37f5ea PU |
137 | * smaller buffer than the FIFO size to avoid underruns. |
138 | * This applies only for the playback stream. | |
ddc29b01 | 139 | */ |
ce37f5ea PU |
140 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
141 | snd_pcm_hw_rule_add(substream->runtime, 0, | |
142 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE, | |
143 | omap_mcbsp_hwrule_min_buffersize, | |
144 | mcbsp, | |
145 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
caebc0cb | 146 | |
998a8a69 PU |
147 | /* Make sure, that the period size is always even */ |
148 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
149 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); | |
6984992b JN |
150 | } |
151 | ||
2e74796a JN |
152 | return err; |
153 | } | |
154 | ||
dee89c4d | 155 | static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream, |
f0fba2ad | 156 | struct snd_soc_dai *cpu_dai) |
2e74796a | 157 | { |
45656b44 | 158 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
2e74796a JN |
159 | |
160 | if (!cpu_dai->active) { | |
45656b44 | 161 | omap_mcbsp_free(mcbsp); |
256d9c25 | 162 | mcbsp->configured = 0; |
2e74796a JN |
163 | } |
164 | } | |
165 | ||
dee89c4d | 166 | static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd, |
f0fba2ad | 167 | struct snd_soc_dai *cpu_dai) |
2e74796a | 168 | { |
45656b44 | 169 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
c12abc01 | 170 | int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
2e74796a JN |
171 | |
172 | switch (cmd) { | |
173 | case SNDRV_PCM_TRIGGER_START: | |
174 | case SNDRV_PCM_TRIGGER_RESUME: | |
175 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
256d9c25 | 176 | mcbsp->active++; |
45656b44 | 177 | omap_mcbsp_start(mcbsp, play, !play); |
2e74796a JN |
178 | break; |
179 | ||
180 | case SNDRV_PCM_TRIGGER_STOP: | |
181 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
182 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
45656b44 | 183 | omap_mcbsp_stop(mcbsp, play, !play); |
256d9c25 | 184 | mcbsp->active--; |
2e74796a JN |
185 | break; |
186 | default: | |
187 | err = -EINVAL; | |
188 | } | |
189 | ||
190 | return err; | |
191 | } | |
192 | ||
75581d24 PU |
193 | static snd_pcm_sframes_t omap_mcbsp_dai_delay( |
194 | struct snd_pcm_substream *substream, | |
195 | struct snd_soc_dai *dai) | |
196 | { | |
197 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 198 | struct snd_soc_dai *cpu_dai = rtd->cpu_dai; |
45656b44 | 199 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
75581d24 PU |
200 | u16 fifo_use; |
201 | snd_pcm_sframes_t delay; | |
202 | ||
203 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
45656b44 | 204 | fifo_use = omap_mcbsp_get_tx_delay(mcbsp); |
75581d24 | 205 | else |
45656b44 | 206 | fifo_use = omap_mcbsp_get_rx_delay(mcbsp); |
75581d24 PU |
207 | |
208 | /* | |
209 | * Divide the used locations with the channel count to get the | |
210 | * FIFO usage in samples (don't care about partial samples in the | |
211 | * buffer). | |
212 | */ | |
213 | delay = fifo_use / substream->runtime->channels; | |
214 | ||
215 | return delay; | |
216 | } | |
217 | ||
2e74796a | 218 | static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, |
dee89c4d | 219 | struct snd_pcm_hw_params *params, |
f0fba2ad | 220 | struct snd_soc_dai *cpu_dai) |
2e74796a | 221 | { |
45656b44 | 222 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
256d9c25 | 223 | struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; |
09ae3aaf | 224 | struct snd_dmaengine_dai_dma_data *dma_data; |
061fb36d | 225 | int wlen, channels, wpf; |
cf80e158 | 226 | int pkt_size = 0; |
5f63ef99 | 227 | unsigned int format, div, framesize, master; |
2e74796a | 228 | |
bcd6da7b | 229 | dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream); |
778a17c3 | 230 | channels = params_channels(params); |
2686e07b | 231 | |
d98508a1 SL |
232 | switch (params_format(params)) { |
233 | case SNDRV_PCM_FORMAT_S16_LE: | |
cf80e158 | 234 | wlen = 16; |
d98508a1 SL |
235 | break; |
236 | case SNDRV_PCM_FORMAT_S32_LE: | |
cf80e158 | 237 | wlen = 32; |
d98508a1 SL |
238 | break; |
239 | default: | |
240 | return -EINVAL; | |
241 | } | |
45656b44 | 242 | if (mcbsp->pdata->buffer_size) { |
cb40b63a | 243 | if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) { |
cf80e158 | 244 | int period_words, max_thrsh; |
dffb360e | 245 | int divider = 0; |
cf80e158 PU |
246 | |
247 | period_words = params_period_bytes(params) / (wlen / 8); | |
248 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
cb40b63a | 249 | max_thrsh = mcbsp->max_tx_thres; |
cf80e158 | 250 | else |
cb40b63a | 251 | max_thrsh = mcbsp->max_rx_thres; |
cf80e158 | 252 | /* |
dffb360e PU |
253 | * Use sDMA packet mode if McBSP is in threshold mode: |
254 | * If period words less than the FIFO size the packet | |
255 | * size is set to the number of period words, otherwise | |
256 | * Look for the biggest threshold value which divides | |
257 | * the period size evenly. | |
cf80e158 | 258 | */ |
dffb360e PU |
259 | divider = period_words / max_thrsh; |
260 | if (period_words % max_thrsh) | |
261 | divider++; | |
262 | while (period_words % divider && | |
263 | divider < period_words) | |
264 | divider++; | |
265 | if (divider == period_words) | |
266 | return -EINVAL; | |
267 | ||
268 | pkt_size = period_words / divider; | |
778a17c3 PU |
269 | } else if (channels > 1) { |
270 | /* Use packet mode for non mono streams */ | |
271 | pkt_size = channels; | |
cf80e158 | 272 | } |
abe99370 | 273 | omap_mcbsp_set_threshold(substream, pkt_size); |
15d01430 PU |
274 | } |
275 | ||
09ae3aaf | 276 | dma_data->maxburst = pkt_size; |
fd23b7de | 277 | |
256d9c25 | 278 | if (mcbsp->configured) { |
2e74796a JN |
279 | /* McBSP already configured by another stream */ |
280 | return 0; | |
281 | } | |
282 | ||
4dd04172 JN |
283 | regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7)); |
284 | regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7)); | |
285 | regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7)); | |
286 | regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7)); | |
256d9c25 | 287 | format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK; |
778a17c3 | 288 | wpf = channels; |
299a151f PU |
289 | if (channels == 2 && (format == SND_SOC_DAIFMT_I2S || |
290 | format == SND_SOC_DAIFMT_LEFT_J)) { | |
5f63ef99 GG |
291 | /* Use dual-phase frames */ |
292 | regs->rcr2 |= RPHASE; | |
293 | regs->xcr2 |= XPHASE; | |
294 | /* Set 1 word per (McBSP) frame for phase1 and phase2 */ | |
295 | wpf--; | |
296 | regs->rcr2 |= RFRLEN2(wpf - 1); | |
297 | regs->xcr2 |= XFRLEN2(wpf - 1); | |
2e74796a JN |
298 | } |
299 | ||
5f63ef99 GG |
300 | regs->rcr1 |= RFRLEN1(wpf - 1); |
301 | regs->xcr1 |= XFRLEN1(wpf - 1); | |
302 | ||
2e74796a JN |
303 | switch (params_format(params)) { |
304 | case SNDRV_PCM_FORMAT_S16_LE: | |
305 | /* Set word lengths */ | |
306 | regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16); | |
307 | regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16); | |
308 | regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16); | |
309 | regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16); | |
2e74796a | 310 | break; |
d98508a1 SL |
311 | case SNDRV_PCM_FORMAT_S32_LE: |
312 | /* Set word lengths */ | |
d98508a1 SL |
313 | regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32); |
314 | regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32); | |
315 | regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32); | |
316 | regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32); | |
317 | break; | |
2e74796a JN |
318 | default: |
319 | /* Unsupported PCM format */ | |
320 | return -EINVAL; | |
321 | } | |
322 | ||
5f63ef99 GG |
323 | /* In McBSP master modes, FRAME (i.e. sample rate) is generated |
324 | * by _counting_ BCLKs. Calculate frame size in BCLKs */ | |
256d9c25 | 325 | master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK; |
5f63ef99 | 326 | if (master == SND_SOC_DAIFMT_CBS_CFS) { |
256d9c25 PU |
327 | div = mcbsp->clk_div ? mcbsp->clk_div : 1; |
328 | framesize = (mcbsp->in_freq / div) / params_rate(params); | |
5f63ef99 GG |
329 | |
330 | if (framesize < wlen * channels) { | |
331 | printk(KERN_ERR "%s: not enough bandwidth for desired rate and " | |
332 | "channels\n", __func__); | |
333 | return -EINVAL; | |
334 | } | |
335 | } else | |
336 | framesize = wlen * channels; | |
337 | ||
ba9d0fd0 | 338 | /* Set FS period and length in terms of bit clock periods */ |
4dd04172 JN |
339 | regs->srgr2 &= ~FPER(0xfff); |
340 | regs->srgr1 &= ~FWID(0xff); | |
c29b206f | 341 | switch (format) { |
ba9d0fd0 | 342 | case SND_SOC_DAIFMT_I2S: |
299a151f | 343 | case SND_SOC_DAIFMT_LEFT_J: |
5f63ef99 GG |
344 | regs->srgr2 |= FPER(framesize - 1); |
345 | regs->srgr1 |= FWID((framesize >> 1) - 1); | |
ba9d0fd0 | 346 | break; |
3ba191ce | 347 | case SND_SOC_DAIFMT_DSP_A: |
bd25867a | 348 | case SND_SOC_DAIFMT_DSP_B: |
5f63ef99 | 349 | regs->srgr2 |= FPER(framesize - 1); |
36ce8582 | 350 | regs->srgr1 |= FWID(0); |
ba9d0fd0 JN |
351 | break; |
352 | } | |
353 | ||
256d9c25 PU |
354 | omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs); |
355 | mcbsp->wlen = wlen; | |
356 | mcbsp->configured = 1; | |
2e74796a JN |
357 | |
358 | return 0; | |
359 | } | |
360 | ||
361 | /* | |
362 | * This must be called before _set_clkdiv and _set_sysclk since McBSP register | |
363 | * cache is initialized here | |
364 | */ | |
8687eb8b | 365 | static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
2e74796a JN |
366 | unsigned int fmt) |
367 | { | |
45656b44 | 368 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
256d9c25 | 369 | struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; |
91a18ae8 | 370 | bool inv_fs = false; |
2e74796a | 371 | |
256d9c25 | 372 | if (mcbsp->configured) |
2e74796a JN |
373 | return 0; |
374 | ||
256d9c25 | 375 | mcbsp->fmt = fmt; |
2e74796a JN |
376 | memset(regs, 0, sizeof(*regs)); |
377 | /* Generic McBSP register settings */ | |
378 | regs->spcr2 |= XINTM(3) | FREE; | |
379 | regs->spcr1 |= RINTM(3); | |
dc26df52 PU |
380 | /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */ |
381 | if (!mcbsp->pdata->has_ccr) { | |
c721bbda EN |
382 | regs->rcr2 |= RFIG; |
383 | regs->xcr2 |= XFIG; | |
384 | } | |
dc26df52 PU |
385 | |
386 | /* Configure XCCR/RCCR only for revisions which have ccr registers */ | |
387 | if (mcbsp->pdata->has_ccr) { | |
32080af7 JN |
388 | regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE; |
389 | regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE; | |
ef390c0b | 390 | } |
2e74796a JN |
391 | |
392 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
393 | case SND_SOC_DAIFMT_I2S: | |
394 | /* 1-bit data delay */ | |
395 | regs->rcr2 |= RDATDLY(1); | |
396 | regs->xcr2 |= XDATDLY(1); | |
397 | break; | |
299a151f PU |
398 | case SND_SOC_DAIFMT_LEFT_J: |
399 | /* 0-bit data delay */ | |
400 | regs->rcr2 |= RDATDLY(0); | |
401 | regs->xcr2 |= XDATDLY(0); | |
402 | regs->spcr1 |= RJUST(2); | |
403 | /* Invert FS polarity configuration */ | |
91a18ae8 | 404 | inv_fs = true; |
299a151f | 405 | break; |
3ba191ce PU |
406 | case SND_SOC_DAIFMT_DSP_A: |
407 | /* 1-bit data delay */ | |
408 | regs->rcr2 |= RDATDLY(1); | |
409 | regs->xcr2 |= XDATDLY(1); | |
410 | /* Invert FS polarity configuration */ | |
91a18ae8 | 411 | inv_fs = true; |
3ba191ce | 412 | break; |
bd25867a | 413 | case SND_SOC_DAIFMT_DSP_B: |
3336c5b5 AK |
414 | /* 0-bit data delay */ |
415 | regs->rcr2 |= RDATDLY(0); | |
416 | regs->xcr2 |= XDATDLY(0); | |
36ce8582 | 417 | /* Invert FS polarity configuration */ |
91a18ae8 | 418 | inv_fs = true; |
3336c5b5 | 419 | break; |
2e74796a JN |
420 | default: |
421 | /* Unsupported data format */ | |
422 | return -EINVAL; | |
423 | } | |
424 | ||
425 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
426 | case SND_SOC_DAIFMT_CBS_CFS: | |
427 | /* McBSP master. Set FS and bit clocks as outputs */ | |
428 | regs->pcr0 |= FSXM | FSRM | | |
429 | CLKXM | CLKRM; | |
430 | /* Sample rate generator drives the FS */ | |
431 | regs->srgr2 |= FSGM; | |
432 | break; | |
6e20b0d7 MT |
433 | case SND_SOC_DAIFMT_CBM_CFS: |
434 | /* McBSP slave. FS clock as output */ | |
435 | regs->srgr2 |= FSGM; | |
436 | regs->pcr0 |= FSXM; | |
437 | break; | |
2e74796a JN |
438 | case SND_SOC_DAIFMT_CBM_CFM: |
439 | /* McBSP slave */ | |
440 | break; | |
441 | default: | |
442 | /* Unsupported master/slave configuration */ | |
443 | return -EINVAL; | |
444 | } | |
445 | ||
446 | /* Set bit clock (CLKX/CLKR) and FS polarities */ | |
91a18ae8 | 447 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
2e74796a JN |
448 | case SND_SOC_DAIFMT_NB_NF: |
449 | /* | |
450 | * Normal BCLK + FS. | |
451 | * FS active low. TX data driven on falling edge of bit clock | |
452 | * and RX data sampled on rising edge of bit clock. | |
453 | */ | |
454 | regs->pcr0 |= FSXP | FSRP | | |
455 | CLKXP | CLKRP; | |
456 | break; | |
457 | case SND_SOC_DAIFMT_NB_IF: | |
458 | regs->pcr0 |= CLKXP | CLKRP; | |
459 | break; | |
460 | case SND_SOC_DAIFMT_IB_NF: | |
461 | regs->pcr0 |= FSXP | FSRP; | |
462 | break; | |
463 | case SND_SOC_DAIFMT_IB_IF: | |
464 | break; | |
465 | default: | |
466 | return -EINVAL; | |
467 | } | |
91a18ae8 JN |
468 | if (inv_fs == true) |
469 | regs->pcr0 ^= FSXP | FSRP; | |
2e74796a JN |
470 | |
471 | return 0; | |
472 | } | |
473 | ||
8687eb8b | 474 | static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, |
2e74796a JN |
475 | int div_id, int div) |
476 | { | |
45656b44 | 477 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
256d9c25 | 478 | struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; |
2e74796a JN |
479 | |
480 | if (div_id != OMAP_MCBSP_CLKGDV) | |
481 | return -ENODEV; | |
482 | ||
256d9c25 | 483 | mcbsp->clk_div = div; |
4dd04172 | 484 | regs->srgr1 &= ~CLKGDV(0xff); |
2e74796a JN |
485 | regs->srgr1 |= CLKGDV(div - 1); |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
8687eb8b | 490 | static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
2e74796a JN |
491 | int clk_id, unsigned int freq, |
492 | int dir) | |
493 | { | |
45656b44 | 494 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
256d9c25 | 495 | struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; |
2e74796a JN |
496 | int err = 0; |
497 | ||
256d9c25 PU |
498 | if (mcbsp->active) { |
499 | if (freq == mcbsp->in_freq) | |
34c86985 JN |
500 | return 0; |
501 | else | |
502 | return -EBUSY; | |
141947e6 | 503 | } |
34c86985 | 504 | |
8fef6263 PU |
505 | mcbsp->in_freq = freq; |
506 | regs->srgr2 &= ~CLKSM; | |
507 | regs->pcr0 &= ~SCLKME; | |
5f63ef99 | 508 | |
2e74796a JN |
509 | switch (clk_id) { |
510 | case OMAP_MCBSP_SYSCLK_CLK: | |
511 | regs->srgr2 |= CLKSM; | |
512 | break; | |
513 | case OMAP_MCBSP_SYSCLK_CLKS_FCLK: | |
e650794a | 514 | if (mcbsp_omap1()) { |
d1358657 PW |
515 | err = -EINVAL; |
516 | break; | |
517 | } | |
45656b44 | 518 | err = omap2_mcbsp_set_clks_src(mcbsp, |
d1358657 PW |
519 | MCBSP_CLKS_PRCM_SRC); |
520 | break; | |
2e74796a | 521 | case OMAP_MCBSP_SYSCLK_CLKS_EXT: |
e650794a | 522 | if (mcbsp_omap1()) { |
d1358657 PW |
523 | err = 0; |
524 | break; | |
525 | } | |
45656b44 | 526 | err = omap2_mcbsp_set_clks_src(mcbsp, |
d1358657 | 527 | MCBSP_CLKS_PAD_SRC); |
2e74796a JN |
528 | break; |
529 | ||
530 | case OMAP_MCBSP_SYSCLK_CLKX_EXT: | |
531 | regs->srgr2 |= CLKSM; | |
532 | case OMAP_MCBSP_SYSCLK_CLKR_EXT: | |
533 | regs->pcr0 |= SCLKME; | |
534 | break; | |
535 | default: | |
536 | err = -ENODEV; | |
537 | } | |
538 | ||
539 | return err; | |
540 | } | |
541 | ||
85e7652d | 542 | static const struct snd_soc_dai_ops mcbsp_dai_ops = { |
6335d055 EM |
543 | .startup = omap_mcbsp_dai_startup, |
544 | .shutdown = omap_mcbsp_dai_shutdown, | |
545 | .trigger = omap_mcbsp_dai_trigger, | |
75581d24 | 546 | .delay = omap_mcbsp_dai_delay, |
6335d055 EM |
547 | .hw_params = omap_mcbsp_dai_hw_params, |
548 | .set_fmt = omap_mcbsp_dai_set_dai_fmt, | |
549 | .set_clkdiv = omap_mcbsp_dai_set_clkdiv, | |
550 | .set_sysclk = omap_mcbsp_dai_set_dai_sysclk, | |
551 | }; | |
552 | ||
2ee65950 PU |
553 | static int omap_mcbsp_probe(struct snd_soc_dai *dai) |
554 | { | |
555 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai); | |
556 | ||
557 | pm_runtime_enable(mcbsp->dev); | |
558 | ||
3fe856b3 PU |
559 | snd_soc_dai_init_dma_data(dai, |
560 | &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK], | |
561 | &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]); | |
562 | ||
2ee65950 PU |
563 | return 0; |
564 | } | |
565 | ||
566 | static int omap_mcbsp_remove(struct snd_soc_dai *dai) | |
567 | { | |
568 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai); | |
569 | ||
570 | pm_runtime_disable(mcbsp->dev); | |
571 | ||
572 | return 0; | |
573 | } | |
574 | ||
6179b772 | 575 | static struct snd_soc_dai_driver omap_mcbsp_dai = { |
2ee65950 PU |
576 | .probe = omap_mcbsp_probe, |
577 | .remove = omap_mcbsp_remove, | |
f0fba2ad LG |
578 | .playback = { |
579 | .channels_min = 1, | |
580 | .channels_max = 16, | |
581 | .rates = OMAP_MCBSP_RATES, | |
582 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, | |
583 | }, | |
584 | .capture = { | |
585 | .channels_min = 1, | |
586 | .channels_max = 16, | |
587 | .rates = OMAP_MCBSP_RATES, | |
588 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, | |
589 | }, | |
590 | .ops = &mcbsp_dai_ops, | |
2e74796a | 591 | }; |
8def464d | 592 | |
43cd814a KM |
593 | static const struct snd_soc_component_driver omap_mcbsp_component = { |
594 | .name = "omap-mcbsp", | |
595 | }; | |
596 | ||
3484457f | 597 | static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol, |
83905c13 IK |
598 | struct snd_ctl_elem_info *uinfo) |
599 | { | |
600 | struct soc_mixer_control *mc = | |
601 | (struct soc_mixer_control *)kcontrol->private_value; | |
602 | int max = mc->max; | |
603 | int min = mc->min; | |
604 | ||
605 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
606 | uinfo->count = 1; | |
607 | uinfo->value.integer.min = min; | |
608 | uinfo->value.integer.max = max; | |
609 | return 0; | |
610 | } | |
611 | ||
db615509 | 612 | #define OMAP_MCBSP_ST_CHANNEL_VOLUME(channel) \ |
83905c13 | 613 | static int \ |
db615509 | 614 | omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \ |
83905c13 IK |
615 | struct snd_ctl_elem_value *uc) \ |
616 | { \ | |
45656b44 PU |
617 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \ |
618 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \ | |
83905c13 IK |
619 | struct soc_mixer_control *mc = \ |
620 | (struct soc_mixer_control *)kc->private_value; \ | |
621 | int max = mc->max; \ | |
622 | int min = mc->min; \ | |
623 | int val = uc->value.integer.value[0]; \ | |
624 | \ | |
625 | if (val < min || val > max) \ | |
626 | return -EINVAL; \ | |
627 | \ | |
628 | /* OMAP McBSP implementation uses index values 0..4 */ \ | |
45656b44 | 629 | return omap_st_set_chgain(mcbsp, channel, val); \ |
db615509 PU |
630 | } \ |
631 | \ | |
83905c13 | 632 | static int \ |
db615509 | 633 | omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \ |
83905c13 IK |
634 | struct snd_ctl_elem_value *uc) \ |
635 | { \ | |
45656b44 PU |
636 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \ |
637 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \ | |
83905c13 IK |
638 | s16 chgain; \ |
639 | \ | |
45656b44 | 640 | if (omap_st_get_chgain(mcbsp, channel, &chgain)) \ |
83905c13 IK |
641 | return -EAGAIN; \ |
642 | \ | |
643 | uc->value.integer.value[0] = chgain; \ | |
644 | return 0; \ | |
645 | } | |
646 | ||
db615509 PU |
647 | OMAP_MCBSP_ST_CHANNEL_VOLUME(0) |
648 | OMAP_MCBSP_ST_CHANNEL_VOLUME(1) | |
83905c13 IK |
649 | |
650 | static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol, | |
651 | struct snd_ctl_elem_value *ucontrol) | |
652 | { | |
45656b44 PU |
653 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); |
654 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); | |
83905c13 IK |
655 | u8 value = ucontrol->value.integer.value[0]; |
656 | ||
45656b44 | 657 | if (value == omap_st_is_enabled(mcbsp)) |
83905c13 IK |
658 | return 0; |
659 | ||
660 | if (value) | |
45656b44 | 661 | omap_st_enable(mcbsp); |
83905c13 | 662 | else |
45656b44 | 663 | omap_st_disable(mcbsp); |
83905c13 IK |
664 | |
665 | return 1; | |
666 | } | |
667 | ||
668 | static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol, | |
669 | struct snd_ctl_elem_value *ucontrol) | |
670 | { | |
45656b44 PU |
671 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); |
672 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); | |
83905c13 | 673 | |
45656b44 | 674 | ucontrol->value.integer.value[0] = omap_st_is_enabled(mcbsp); |
83905c13 IK |
675 | return 0; |
676 | } | |
677 | ||
8996a31c PU |
678 | #define OMAP_MCBSP_ST_CONTROLS(port) \ |
679 | static const struct snd_kcontrol_new omap_mcbsp##port##_st_controls[] = { \ | |
680 | SOC_SINGLE_EXT("McBSP" #port " Sidetone Switch", 1, 0, 1, 0, \ | |
681 | omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode), \ | |
682 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 0 Volume", \ | |
683 | -32768, 32767, \ | |
684 | omap_mcbsp_get_st_ch0_volume, \ | |
685 | omap_mcbsp_set_st_ch0_volume), \ | |
686 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 1 Volume", \ | |
687 | -32768, 32767, \ | |
688 | omap_mcbsp_get_st_ch1_volume, \ | |
689 | omap_mcbsp_set_st_ch1_volume), \ | |
690 | } | |
83905c13 | 691 | |
8996a31c PU |
692 | OMAP_MCBSP_ST_CONTROLS(2); |
693 | OMAP_MCBSP_ST_CONTROLS(3); | |
83905c13 | 694 | |
45656b44 | 695 | int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd) |
83905c13 | 696 | { |
45656b44 PU |
697 | struct snd_soc_dai *cpu_dai = rtd->cpu_dai; |
698 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); | |
699 | ||
8a88df4c PU |
700 | if (!mcbsp->st_data) { |
701 | dev_warn(mcbsp->dev, "No sidetone data for port\n"); | |
702 | return 0; | |
703 | } | |
83905c13 | 704 | |
28739dfc | 705 | switch (mcbsp->id) { |
45656b44 PU |
706 | case 2: /* McBSP 2 */ |
707 | return snd_soc_add_dai_controls(cpu_dai, | |
708 | omap_mcbsp2_st_controls, | |
83905c13 | 709 | ARRAY_SIZE(omap_mcbsp2_st_controls)); |
45656b44 PU |
710 | case 3: /* McBSP 3 */ |
711 | return snd_soc_add_dai_controls(cpu_dai, | |
712 | omap_mcbsp3_st_controls, | |
83905c13 IK |
713 | ARRAY_SIZE(omap_mcbsp3_st_controls)); |
714 | default: | |
715 | break; | |
716 | } | |
717 | ||
718 | return -EINVAL; | |
719 | } | |
720 | EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls); | |
721 | ||
11dd5864 PU |
722 | static struct omap_mcbsp_platform_data omap2420_pdata = { |
723 | .reg_step = 4, | |
724 | .reg_size = 2, | |
725 | }; | |
726 | ||
727 | static struct omap_mcbsp_platform_data omap2430_pdata = { | |
728 | .reg_step = 4, | |
729 | .reg_size = 4, | |
730 | .has_ccr = true, | |
731 | }; | |
732 | ||
733 | static struct omap_mcbsp_platform_data omap3_pdata = { | |
734 | .reg_step = 4, | |
735 | .reg_size = 4, | |
736 | .has_ccr = true, | |
737 | .has_wakeup = true, | |
738 | }; | |
739 | ||
740 | static struct omap_mcbsp_platform_data omap4_pdata = { | |
741 | .reg_step = 4, | |
742 | .reg_size = 4, | |
743 | .has_ccr = true, | |
744 | .has_wakeup = true, | |
745 | }; | |
746 | ||
747 | static const struct of_device_id omap_mcbsp_of_match[] = { | |
748 | { | |
749 | .compatible = "ti,omap2420-mcbsp", | |
750 | .data = &omap2420_pdata, | |
751 | }, | |
752 | { | |
753 | .compatible = "ti,omap2430-mcbsp", | |
754 | .data = &omap2430_pdata, | |
755 | }, | |
756 | { | |
757 | .compatible = "ti,omap3-mcbsp", | |
758 | .data = &omap3_pdata, | |
759 | }, | |
760 | { | |
761 | .compatible = "ti,omap4-mcbsp", | |
762 | .data = &omap4_pdata, | |
763 | }, | |
764 | { }, | |
765 | }; | |
766 | MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match); | |
767 | ||
7ff60006 | 768 | static int asoc_mcbsp_probe(struct platform_device *pdev) |
f0fba2ad | 769 | { |
2ee65950 PU |
770 | struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev); |
771 | struct omap_mcbsp *mcbsp; | |
11dd5864 | 772 | const struct of_device_id *match; |
45656b44 PU |
773 | int ret; |
774 | ||
11dd5864 PU |
775 | match = of_match_device(omap_mcbsp_of_match, &pdev->dev); |
776 | if (match) { | |
777 | struct device_node *node = pdev->dev.of_node; | |
778 | int buffer_size; | |
779 | ||
780 | pdata = devm_kzalloc(&pdev->dev, | |
781 | sizeof(struct omap_mcbsp_platform_data), | |
782 | GFP_KERNEL); | |
783 | if (!pdata) | |
784 | return -ENOMEM; | |
785 | ||
786 | memcpy(pdata, match->data, sizeof(*pdata)); | |
787 | if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size)) | |
788 | pdata->buffer_size = buffer_size; | |
789 | } else if (!pdata) { | |
2ee65950 PU |
790 | dev_err(&pdev->dev, "missing platform data.\n"); |
791 | return -EINVAL; | |
792 | } | |
793 | mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL); | |
794 | if (!mcbsp) | |
795 | return -ENOMEM; | |
796 | ||
797 | mcbsp->id = pdev->id; | |
798 | mcbsp->pdata = pdata; | |
799 | mcbsp->dev = &pdev->dev; | |
800 | platform_set_drvdata(pdev, mcbsp); | |
801 | ||
802 | ret = omap_mcbsp_init(pdev); | |
45656b44 | 803 | if (!ret) |
43cd814a KM |
804 | return snd_soc_register_component(&pdev->dev, &omap_mcbsp_component, |
805 | &omap_mcbsp_dai, 1); | |
45656b44 PU |
806 | |
807 | return ret; | |
f0fba2ad LG |
808 | } |
809 | ||
7ff60006 | 810 | static int asoc_mcbsp_remove(struct platform_device *pdev) |
f0fba2ad | 811 | { |
2ee65950 PU |
812 | struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); |
813 | ||
43cd814a | 814 | snd_soc_unregister_component(&pdev->dev); |
2ee65950 PU |
815 | |
816 | if (mcbsp->pdata->ops && mcbsp->pdata->ops->free) | |
817 | mcbsp->pdata->ops->free(mcbsp->id); | |
818 | ||
819 | omap_mcbsp_sysfs_remove(mcbsp); | |
820 | ||
821 | clk_put(mcbsp->fclk); | |
822 | ||
f0fba2ad LG |
823 | return 0; |
824 | } | |
825 | ||
826 | static struct platform_driver asoc_mcbsp_driver = { | |
827 | .driver = { | |
45656b44 | 828 | .name = "omap-mcbsp", |
f0fba2ad | 829 | .owner = THIS_MODULE, |
11dd5864 | 830 | .of_match_table = omap_mcbsp_of_match, |
f0fba2ad LG |
831 | }, |
832 | ||
833 | .probe = asoc_mcbsp_probe, | |
7ff60006 | 834 | .remove = asoc_mcbsp_remove, |
f0fba2ad LG |
835 | }; |
836 | ||
beda5bf5 | 837 | module_platform_driver(asoc_mcbsp_driver); |
3f4b783c | 838 | |
7ec41ee5 | 839 | MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>"); |
2e74796a JN |
840 | MODULE_DESCRIPTION("OMAP I2S SoC Interface"); |
841 | MODULE_LICENSE("GPL"); | |
5e70b7fc | 842 | MODULE_ALIAS("platform:omap-mcbsp"); |