[deliverable/linux.git] / sound / soc / omap / omap-mcbsp.c

/*
 * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
 *
 * Copyright (C) 2008 Nokia Corporation
 *
 * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include <mach/control.h>
#include <mach/dma.h>
#include <mach/mcbsp.h>
#include "omap-mcbsp.h"
#include "omap-pcm.h"

#define OMAP_MCBSP_RATES	(SNDRV_PCM_RATE_44100 | \
				 SNDRV_PCM_RATE_48000 | \
				 SNDRV_PCM_RATE_KNOT)

struct omap_mcbsp_data {
	unsigned int			bus_id;
	struct omap_mcbsp_reg_cfg	regs;
	/*
	 * Flags indicating is the bus already activated and configured by
	 * another substream
	 */
	int				active;
	int				configured;
};

#define to_mcbsp(priv)	container_of((priv), struct omap_mcbsp_data, bus_id)

static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];

/*
 * Stream DMA parameters. DMA request line and port address are set runtime
 * since they are different between OMAP1 and later OMAPs
 */
static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2] = {
{
	{ .name		= "I2S PCM Stereo out", },
	{ .name		= "I2S PCM Stereo in", },
},
};

#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
static const int omap1_dma_reqs[][2] = {
	{ OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
	{ OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
	{ OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
};
static const unsigned long omap1_mcbsp_port[][2] = {
	{ OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	{ OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
	{ OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
};
#else
static const int omap1_dma_reqs[][2] = {};
static const unsigned long omap1_mcbsp_port[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
static const int omap24xx_dma_reqs[][2] = {
	{ OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
	{ OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
	{ OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
	{ OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
	{ OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
#endif
};
#else
static const int omap24xx_dma_reqs[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP2420)
static const unsigned long omap2420_mcbsp_port[][2] = {
	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
};
#else
static const unsigned long omap2420_mcbsp_port[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP2430)
static const unsigned long omap2430_mcbsp_port[][2] = {
	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
};
#else
static const unsigned long omap2430_mcbsp_port[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP34XX)
static const unsigned long omap34xx_mcbsp_port[][2] = {
	{ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
};
#else
static const unsigned long omap34xx_mcbsp_port[][2] = {};
#endif

static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	int err = 0;

	if (!cpu_dai->active)
		err = omap_mcbsp_request(mcbsp_data->bus_id);

	return err;
}

static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);

	if (!cpu_dai->active) {
		omap_mcbsp_free(mcbsp_data->bus_id);
		mcbsp_data->configured = 0;
	}
}

static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	int err = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (!mcbsp_data->active++)
			omap_mcbsp_start(mcbsp_data->bus_id);
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (!--mcbsp_data->active)
			omap_mcbsp_stop(mcbsp_data->bus_id);
		break;
	default:
		err = -EINVAL;
	}

	return err;
}

static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
	unsigned long port;

	if (cpu_class_is_omap1()) {
		dma = omap1_dma_reqs[bus_id][substream->stream];
		port = omap1_mcbsp_port[bus_id][substream->stream];
	} else if (cpu_is_omap2420()) {
		dma = omap24xx_dma_reqs[bus_id][substream->stream];
		port = omap2420_mcbsp_port[bus_id][substream->stream];
	} else if (cpu_is_omap2430()) {
		dma = omap24xx_dma_reqs[bus_id][substream->stream];
		port = omap2430_mcbsp_port[bus_id][substream->stream];
	} else if (cpu_is_omap343x()) {
		dma = omap24xx_dma_reqs[bus_id][substream->stream];
		port = omap34xx_mcbsp_port[bus_id][substream->stream];
	} else {
		return -ENODEV;
	}
	omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
	omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
	cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];

	if (mcbsp_data->configured) {
		/* McBSP already configured by another stream */
		return 0;
	}

	switch (params_channels(params)) {
	case 2:
		/* Set 1 word per (McBPSP) frame and use dual-phase frames */
		regs->rcr2	|= RFRLEN2(1 - 1) | RPHASE;
		regs->rcr1	|= RFRLEN1(1 - 1);
		regs->xcr2	|= XFRLEN2(1 - 1) | XPHASE;
		regs->xcr1	|= XFRLEN1(1 - 1);
		break;
	default:
		/* Unsupported number of channels */
		return -EINVAL;
	}

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		/* Set word lengths */
		regs->rcr2	|= RWDLEN2(OMAP_MCBSP_WORD_16);
		regs->rcr1	|= RWDLEN1(OMAP_MCBSP_WORD_16);
		regs->xcr2	|= XWDLEN2(OMAP_MCBSP_WORD_16);
		regs->xcr1	|= XWDLEN1(OMAP_MCBSP_WORD_16);
		/* Set FS period and length in terms of bit clock periods */
		regs->srgr2	|= FPER(16 * 2 - 1);
		regs->srgr1	|= FWID(16 - 1);
		break;
	default:
		/* Unsupported PCM format */
		return -EINVAL;
	}

	omap_mcbsp_config(bus_id, &mcbsp_data->regs);
	mcbsp_data->configured = 1;

	return 0;
}

/*
 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 * cache is initialized here
 */
static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
				      unsigned int fmt)
{
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;

	if (mcbsp_data->configured)
		return 0;

	memset(regs, 0, sizeof(*regs));
	/* Generic McBSP register settings */
	regs->spcr2	|= XINTM(3) | FREE;
	regs->spcr1	|= RINTM(3);
	regs->rcr2	|= RFIG;
	regs->xcr2	|= XFIG;

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		/* 1-bit data delay */
		regs->rcr2	|= RDATDLY(1);
		regs->xcr2	|= XDATDLY(1);
		break;
	case SND_SOC_DAIFMT_DSP_A:
		/* 0-bit data delay */
		regs->rcr2      |= RDATDLY(0);
		regs->xcr2      |= XDATDLY(0);
		break;
	default:
		/* Unsupported data format */
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* McBSP master. Set FS and bit clocks as outputs */
		regs->pcr0	|= FSXM | FSRM |
				   CLKXM | CLKRM;
		/* Sample rate generator drives the FS */
		regs->srgr2	|= FSGM;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		/* McBSP slave */
		break;
	default:
		/* Unsupported master/slave configuration */
		return -EINVAL;
	}

	/* Set bit clock (CLKX/CLKR) and FS polarities */
	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		/*
		 * Normal BCLK + FS.
		 * FS active low. TX data driven on falling edge of bit clock
		 * and RX data sampled on rising edge of bit clock.
		 */
		regs->pcr0	|= FSXP | FSRP |
				   CLKXP | CLKRP;
		break;
	case SND_SOC_DAIFMT_NB_IF:
		regs->pcr0	|= CLKXP | CLKRP;
		break;
	case SND_SOC_DAIFMT_IB_NF:
		regs->pcr0	|= FSXP | FSRP;
		break;
	case SND_SOC_DAIFMT_IB_IF:
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
				     int div_id, int div)
{
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;

	if (div_id != OMAP_MCBSP_CLKGDV)
		return -ENODEV;

	regs->srgr1	|= CLKGDV(div - 1);

	return 0;
}

static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
				       int clk_id)
{
	int sel_bit;
	u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;

	if (cpu_class_is_omap1()) {
		/* OMAP1's can use only external source clock */
		if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
			return -EINVAL;
		else
			return 0;
	}

	if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
		return -EINVAL;

	if (cpu_is_omap343x())
		reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;

	switch (mcbsp_data->bus_id) {
	case 0:
		reg = OMAP2_CONTROL_DEVCONF0;
		sel_bit = 2;
		break;
	case 1:
		reg = OMAP2_CONTROL_DEVCONF0;
		sel_bit = 6;
		break;
	case 2:
		reg = reg_devconf1;
		sel_bit = 0;
		break;
	case 3:
		reg = reg_devconf1;
		sel_bit = 2;
		break;
	case 4:
		reg = reg_devconf1;
		sel_bit = 4;
		break;
	default:
		return -EINVAL;
	}

	if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
		omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
	else
		omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);

	return 0;
}

static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
					 int clk_id, unsigned int freq,
					 int dir)
{
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	int err = 0;

	switch (clk_id) {
	case OMAP_MCBSP_SYSCLK_CLK:
		regs->srgr2	|= CLKSM;
		break;
	case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
	case OMAP_MCBSP_SYSCLK_CLKS_EXT:
		err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
		break;

	case OMAP_MCBSP_SYSCLK_CLKX_EXT:
		regs->srgr2	|= CLKSM;
	case OMAP_MCBSP_SYSCLK_CLKR_EXT:
		regs->pcr0	|= SCLKME;
		break;
	default:
		err = -ENODEV;
	}

	return err;
}

#define OMAP_MCBSP_DAI_BUILDER(link_id)				\
{								\
	.name = "omap-mcbsp-dai-(link_id)",			\
	.id = (link_id),					\
	.type = SND_SOC_DAI_I2S,				\
	.playback = {						\
		.channels_min = 2,				\
		.channels_max = 2,				\
		.rates = OMAP_MCBSP_RATES,			\
		.formats = SNDRV_PCM_FMTBIT_S16_LE,		\
	},							\
	.capture = {						\
		.channels_min = 2,				\
		.channels_max = 2,				\
		.rates = OMAP_MCBSP_RATES,			\
		.formats = SNDRV_PCM_FMTBIT_S16_LE,		\
	},							\
	.ops = {						\
		.startup = omap_mcbsp_dai_startup,		\
		.shutdown = omap_mcbsp_dai_shutdown,		\
		.trigger = omap_mcbsp_dai_trigger,		\
		.hw_params = omap_mcbsp_dai_hw_params,		\
	},							\
	.dai_ops = {						\
		.set_fmt = omap_mcbsp_dai_set_dai_fmt,		\
		.set_clkdiv = omap_mcbsp_dai_set_clkdiv,	\
		.set_sysclk = omap_mcbsp_dai_set_dai_sysclk,	\
	},							\
	.private_data = &mcbsp_data[(link_id)].bus_id,		\
}

struct snd_soc_dai omap_mcbsp_dai[] = {
	OMAP_MCBSP_DAI_BUILDER(0),
	OMAP_MCBSP_DAI_BUILDER(1),
#if NUM_LINKS >= 3
	OMAP_MCBSP_DAI_BUILDER(2),
#endif
#if NUM_LINKS == 5
	OMAP_MCBSP_DAI_BUILDER(3),
	OMAP_MCBSP_DAI_BUILDER(4),
#endif
};

EXPORT_SYMBOL_GPL(omap_mcbsp_dai);

MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
MODULE_DESCRIPTION("OMAP I2S SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
2e74796a JN	1	/*
	2	* omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
	3	*
	4	* Copyright (C) 2008 Nokia Corporation
	5	*
	6	* Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*
	22	*/
	23
	24	#include <linux/init.h>
	25	#include <linux/module.h>
	26	#include <linux/device.h>
	27	#include <sound/core.h>
	28	#include <sound/pcm.h>
	29	#include <sound/pcm_params.h>
	30	#include <sound/initval.h>
	31	#include <sound/soc.h>
	32
a09e64fb RK	33	#include <mach/control.h>
	34	#include <mach/dma.h>
	35	#include <mach/mcbsp.h>
2e74796a JN	36	#include "omap-mcbsp.h"
	37	#include "omap-pcm.h"
	38
	39	#define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_44100 \| \
	40	SNDRV_PCM_RATE_48000 \| \
	41	SNDRV_PCM_RATE_KNOT)
	42
	43	struct omap_mcbsp_data {
	44	unsigned int bus_id;
	45	struct omap_mcbsp_reg_cfg regs;
	46	/*
	47	* Flags indicating is the bus already activated and configured by
	48	* another substream
	49	*/
	50	int active;
	51	int configured;
	52	};
	53
	54	#define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
	55
	56	static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
	57
	58	/*
	59	* Stream DMA parameters. DMA request line and port address are set runtime
	60	* since they are different between OMAP1 and later OMAPs
	61	*/
	62	static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2] = {
	63	{
	64	{ .name = "I2S PCM Stereo out", },
	65	{ .name = "I2S PCM Stereo in", },
	66	},
	67	};
	68
	69	#if defined(CONFIG_ARCH_OMAP15XX) \|\| defined(CONFIG_ARCH_OMAP16XX)
	70	static const int omap1_dma_reqs[][2] = {
	71	{ OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
	72	{ OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
	73	{ OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
	74	};
	75	static const unsigned long omap1_mcbsp_port[][2] = {
	76	{ OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	77	OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	78	{ OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	79	OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
	80	{ OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
	81	OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
	82	};
	83	#else
	84	static const int omap1_dma_reqs[][2] = {};
	85	static const unsigned long omap1_mcbsp_port[][2] = {};
	86	#endif
406e2c48 JN	87
	88	#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
	89	static const int omap24xx_dma_reqs[][2] = {
2e74796a JN	90	{ OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
2e74796a JN	91	{ OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
406e2c48 JN	92	#if defined(CONFIG_ARCH_OMAP2430) \|\| defined(CONFIG_ARCH_OMAP34XX)
	93	{ OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
	94	{ OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
	95	{ OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
	96	#endif
2e74796a	97	};
406e2c48 JN	98	#else
	99	static const int omap24xx_dma_reqs[][2] = {};
	100	#endif
	101
	102	#if defined(CONFIG_ARCH_OMAP2420)
2e74796a JN	103	static const unsigned long omap2420_mcbsp_port[][2] = {
	104	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	105	OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	106	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	107	OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
	108	};
	109	#else
2e74796a JN	110	static const unsigned long omap2420_mcbsp_port[][2] = {};
	111	#endif
	112
406e2c48 JN	113	#if defined(CONFIG_ARCH_OMAP2430)
	114	static const unsigned long omap2430_mcbsp_port[][2] = {
	115	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	116	OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	117	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	118	OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	119	{ OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	120	OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	121	{ OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	122	OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	123	{ OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	124	OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
	125	};
	126	#else
	127	static const unsigned long omap2430_mcbsp_port[][2] = {};
	128	#endif
	129
	130	#if defined(CONFIG_ARCH_OMAP34XX)
	131	static const unsigned long omap34xx_mcbsp_port[][2] = {
	132	{ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	133	OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	134	{ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	135	OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	136	{ OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	137	OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	138	{ OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	139	OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	140	{ OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	141	OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
	142	};
	143	#else
	144	static const unsigned long omap34xx_mcbsp_port[][2] = {};
	145	#endif
	146
2e74796a JN	147	static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream)
	148	{
	149	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	150	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	151	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	152	int err = 0;
	153
	154	if (!cpu_dai->active)
	155	err = omap_mcbsp_request(mcbsp_data->bus_id);
	156
	157	return err;
	158	}
	159
	160	static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream)
	161	{
	162	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	163	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	164	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	165
	166	if (!cpu_dai->active) {
	167	omap_mcbsp_free(mcbsp_data->bus_id);
	168	mcbsp_data->configured = 0;
	169	}
	170	}
	171
	172	static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd)
	173	{
	174	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	175	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	176	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	177	int err = 0;
	178
	179	switch (cmd) {
	180	case SNDRV_PCM_TRIGGER_START:
	181	case SNDRV_PCM_TRIGGER_RESUME:
	182	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	183	if (!mcbsp_data->active++)
	184	omap_mcbsp_start(mcbsp_data->bus_id);
	185	break;
	186
	187	case SNDRV_PCM_TRIGGER_STOP:
	188	case SNDRV_PCM_TRIGGER_SUSPEND:
	189	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	190	if (!--mcbsp_data->active)
	191	omap_mcbsp_stop(mcbsp_data->bus_id);
	192	break;
	193	default:
	194	err = -EINVAL;
	195	}
	196
	197	return err;
	198	}
	199
	200	static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
	201	struct snd_pcm_hw_params *params)
	202	{
	203	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	204	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	205	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	206	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	207	int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
	208	unsigned long port;
	209
	210	if (cpu_class_is_omap1()) {
	211	dma = omap1_dma_reqs[bus_id][substream->stream];
	212	port = omap1_mcbsp_port[bus_id][substream->stream];
	213	} else if (cpu_is_omap2420()) {
406e2c48	214	dma = omap24xx_dma_reqs[bus_id][substream->stream];
2e74796a	215	port = omap2420_mcbsp_port[bus_id][substream->stream];
406e2c48 JN	216	} else if (cpu_is_omap2430()) {
	217	dma = omap24xx_dma_reqs[bus_id][substream->stream];
	218	port = omap2430_mcbsp_port[bus_id][substream->stream];
	219	} else if (cpu_is_omap343x()) {
	220	dma = omap24xx_dma_reqs[bus_id][substream->stream];
	221	port = omap34xx_mcbsp_port[bus_id][substream->stream];
2e74796a	222	} else {
2e74796a JN	223	return -ENODEV;
	224	}
	225	omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
	226	omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
	227	cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
	228
	229	if (mcbsp_data->configured) {
	230	/* McBSP already configured by another stream */
	231	return 0;
	232	}
	233
	234	switch (params_channels(params)) {
	235	case 2:
	236	/* Set 1 word per (McBPSP) frame and use dual-phase frames */
	237	regs->rcr2 \|= RFRLEN2(1 - 1) \| RPHASE;
	238	regs->rcr1 \|= RFRLEN1(1 - 1);
	239	regs->xcr2 \|= XFRLEN2(1 - 1) \| XPHASE;
	240	regs->xcr1 \|= XFRLEN1(1 - 1);
	241	break;
	242	default:
	243	/* Unsupported number of channels */
	244	return -EINVAL;
	245	}
	246
	247	switch (params_format(params)) {
	248	case SNDRV_PCM_FORMAT_S16_LE:
	249	/* Set word lengths */
	250	regs->rcr2 \|= RWDLEN2(OMAP_MCBSP_WORD_16);
	251	regs->rcr1 \|= RWDLEN1(OMAP_MCBSP_WORD_16);
	252	regs->xcr2 \|= XWDLEN2(OMAP_MCBSP_WORD_16);
	253	regs->xcr1 \|= XWDLEN1(OMAP_MCBSP_WORD_16);
	254	/* Set FS period and length in terms of bit clock periods */
	255	regs->srgr2 \|= FPER(16 * 2 - 1);
	256	regs->srgr1 \|= FWID(16 - 1);
	257	break;
	258	default:
	259	/* Unsupported PCM format */
	260	return -EINVAL;
	261	}
	262
	263	omap_mcbsp_config(bus_id, &mcbsp_data->regs);
	264	mcbsp_data->configured = 1;
	265
	266	return 0;
	267	}
	268
	269	/*
	270	* This must be called before _set_clkdiv and _set_sysclk since McBSP register
	271	* cache is initialized here
	272	*/
8687eb8b	273	static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
2e74796a JN	274	unsigned int fmt)
	275	{
	276	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	277	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	278
	279	if (mcbsp_data->configured)
	280	return 0;
	281
	282	memset(regs, 0, sizeof(*regs));
	283	/* Generic McBSP register settings */
	284	regs->spcr2 \|= XINTM(3) \| FREE;
	285	regs->spcr1 \|= RINTM(3);
	286	regs->rcr2 \|= RFIG;
	287	regs->xcr2 \|= XFIG;
	288
	289	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	290	case SND_SOC_DAIFMT_I2S:
	291	/* 1-bit data delay */
	292	regs->rcr2 \|= RDATDLY(1);
	293	regs->xcr2 \|= XDATDLY(1);
	294	break;
3336c5b5 AK	295	case SND_SOC_DAIFMT_DSP_A:
	296	/* 0-bit data delay */
	297	regs->rcr2 \|= RDATDLY(0);
	298	regs->xcr2 \|= XDATDLY(0);
	299	break;
2e74796a JN	300	default:
	301	/* Unsupported data format */
	302	return -EINVAL;
	303	}
	304
	305	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	306	case SND_SOC_DAIFMT_CBS_CFS:
	307	/* McBSP master. Set FS and bit clocks as outputs */
	308	regs->pcr0 \|= FSXM \| FSRM \|
	309	CLKXM \| CLKRM;
	310	/* Sample rate generator drives the FS */
	311	regs->srgr2 \|= FSGM;
	312	break;
	313	case SND_SOC_DAIFMT_CBM_CFM:
	314	/* McBSP slave */
	315	break;
	316	default:
	317	/* Unsupported master/slave configuration */
	318	return -EINVAL;
	319	}
	320
	321	/* Set bit clock (CLKX/CLKR) and FS polarities */
	322	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	323	case SND_SOC_DAIFMT_NB_NF:
	324	/*
	325	* Normal BCLK + FS.
	326	* FS active low. TX data driven on falling edge of bit clock
	327	* and RX data sampled on rising edge of bit clock.
	328	*/
	329	regs->pcr0 \|= FSXP \| FSRP \|
	330	CLKXP \| CLKRP;
	331	break;
	332	case SND_SOC_DAIFMT_NB_IF:
	333	regs->pcr0 \|= CLKXP \| CLKRP;
	334	break;
	335	case SND_SOC_DAIFMT_IB_NF:
	336	regs->pcr0 \|= FSXP \| FSRP;
	337	break;
	338	case SND_SOC_DAIFMT_IB_IF:
	339	break;
	340	default:
	341	return -EINVAL;
	342	}
	343
	344	return 0;
	345	}
	346
8687eb8b	347	static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
2e74796a JN	348	int div_id, int div)
	349	{
	350	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	351	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	352
	353	if (div_id != OMAP_MCBSP_CLKGDV)
	354	return -ENODEV;
	355
	356	regs->srgr1 \|= CLKGDV(div - 1);
	357
	358	return 0;
	359	}
	360
	361	static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
	362	int clk_id)
	363	{
	364	int sel_bit;
406e2c48	365	u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
2e74796a JN	366
	367	if (cpu_class_is_omap1()) {
	368	/* OMAP1's can use only external source clock */
	369	if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
	370	return -EINVAL;
	371	else
	372	return 0;
	373	}
	374
406e2c48 JN	375	if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
	376	return -EINVAL;
	377
	378	if (cpu_is_omap343x())
	379	reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
	380
2e74796a JN	381	switch (mcbsp_data->bus_id) {
	382	case 0:
	383	reg = OMAP2_CONTROL_DEVCONF0;
	384	sel_bit = 2;
	385	break;
	386	case 1:
	387	reg = OMAP2_CONTROL_DEVCONF0;
	388	sel_bit = 6;
	389	break;
406e2c48 JN	390	case 2:
	391	reg = reg_devconf1;
	392	sel_bit = 0;
	393	break;
	394	case 3:
	395	reg = reg_devconf1;
	396	sel_bit = 2;
	397	break;
	398	case 4:
	399	reg = reg_devconf1;
	400	sel_bit = 4;
	401	break;
2e74796a JN	402	default:
	403	return -EINVAL;
	404	}
	405
406e2c48 JN	406	if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
	407	omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
	408	else
	409	omap_ctrl_writel(omap_ctrl_readl(reg) \| (1 << sel_bit), reg);
2e74796a JN	410
	411	return 0;
	412	}
	413
8687eb8b	414	static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
2e74796a JN	415	int clk_id, unsigned int freq,
	416	int dir)
	417	{
	418	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	419	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	420	int err = 0;
	421
	422	switch (clk_id) {
	423	case OMAP_MCBSP_SYSCLK_CLK:
	424	regs->srgr2 \|= CLKSM;
	425	break;
	426	case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
	427	case OMAP_MCBSP_SYSCLK_CLKS_EXT:
	428	err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
	429	break;
	430
	431	case OMAP_MCBSP_SYSCLK_CLKX_EXT:
	432	regs->srgr2 \|= CLKSM;
	433	case OMAP_MCBSP_SYSCLK_CLKR_EXT:
	434	regs->pcr0 \|= SCLKME;
	435	break;
	436	default:
	437	err = -ENODEV;
	438	}
	439
	440	return err;
	441	}
	442
8def464d JN	443	#define OMAP_MCBSP_DAI_BUILDER(link_id) \
	444	{ \
	445	.name = "omap-mcbsp-dai-(link_id)", \
	446	.id = (link_id), \
	447	.type = SND_SOC_DAI_I2S, \
	448	.playback = { \
	449	.channels_min = 2, \
	450	.channels_max = 2, \
	451	.rates = OMAP_MCBSP_RATES, \
	452	.formats = SNDRV_PCM_FMTBIT_S16_LE, \
	453	}, \
	454	.capture = { \
	455	.channels_min = 2, \
	456	.channels_max = 2, \
	457	.rates = OMAP_MCBSP_RATES, \
	458	.formats = SNDRV_PCM_FMTBIT_S16_LE, \
	459	}, \
	460	.ops = { \
	461	.startup = omap_mcbsp_dai_startup, \
	462	.shutdown = omap_mcbsp_dai_shutdown, \
	463	.trigger = omap_mcbsp_dai_trigger, \
	464	.hw_params = omap_mcbsp_dai_hw_params, \
	465	}, \
	466	.dai_ops = { \
	467	.set_fmt = omap_mcbsp_dai_set_dai_fmt, \
	468	.set_clkdiv = omap_mcbsp_dai_set_clkdiv, \
	469	.set_sysclk = omap_mcbsp_dai_set_dai_sysclk, \
	470	}, \
	471	.private_data = &mcbsp_data[(link_id)].bus_id, \
	472	}
	473
	474	struct snd_soc_dai omap_mcbsp_dai[] = {
	475	OMAP_MCBSP_DAI_BUILDER(0),
	476	OMAP_MCBSP_DAI_BUILDER(1),
	477	#if NUM_LINKS >= 3
	478	OMAP_MCBSP_DAI_BUILDER(2),
	479	#endif
	480	#if NUM_LINKS == 5
	481	OMAP_MCBSP_DAI_BUILDER(3),
	482	OMAP_MCBSP_DAI_BUILDER(4),
	483	#endif
2e74796a	484	};
8def464d	485
2e74796a JN	486	EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
	487
	488	MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
	489	MODULE_DESCRIPTION("OMAP I2S SoC Interface");
	490	MODULE_LICENSE("GPL");