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OMAP3: McBSP: Add interface for FIFO caused delay query
[deliverable/linux.git] / sound / soc / omap / omap-mcbsp.c
CommitLineData
2e74796a
JN		 1/*
2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
3 *
4 * Copyright (C) 2008 Nokia Corporation
5 *
b08f7a62
JN		 6 * Contact: Jarkko Nikula <jhnikula@gmail.com>
7 * Peter Ujfalusi <peter.ujfalusi@nokia.com>
2e74796a
JN		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/device.h>
28#include <sound/core.h>
29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/initval.h>
32#include <sound/soc.h>
33
ce491cf8
TL		 34#include <plat/control.h>
35#include <plat/dma.h>
36#include <plat/mcbsp.h>
2e74796a
JN		 37#include "omap-mcbsp.h"
38#include "omap-pcm.h"
39
0b604856 40#define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
2e74796a 41
83905c13
IK		 42#define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
43 xhandler_get, xhandler_put) \
44{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
45 .info = omap_mcbsp_st_info_volsw, \
46 .get = xhandler_get, .put = xhandler_put, \
47 .private_value = (unsigned long) &(struct soc_mixer_control) \
48 {.min = xmin, .max = xmax} }
49
2e74796a
JN		 50struct omap_mcbsp_data {
51 unsigned int bus_id;
52 struct omap_mcbsp_reg_cfg regs;
ba9d0fd0 53 unsigned int fmt;
2e74796a
JN		 54 /*
55 * Flags indicating is the bus already activated and configured by
56 * another substream
57 */
58 int active;
59 int configured;
5f63ef99
GG		 60 unsigned int in_freq;
61 int clk_div;
2e74796a
JN		 62};
63
64#define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
65
66static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
67
68/*
69 * Stream DMA parameters. DMA request line and port address are set runtime
70 * since they are different between OMAP1 and later OMAPs
71 */
2e89713a 72static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
2e74796a
JN		 73
74#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
75static const int omap1_dma_reqs[][2] = {
76 { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
77 { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
78 { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
79};
80static const unsigned long omap1_mcbsp_port[][2] = {
81 { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
82 OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
83 { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
84 OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
85 { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
86 OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
87};
88#else
89static const int omap1_dma_reqs[][2] = {};
90static const unsigned long omap1_mcbsp_port[][2] = {};
91#endif
406e2c48 92
a8eb7ca0 93#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
406e2c48 94static const int omap24xx_dma_reqs[][2] = {
2e74796a
JN		 95 { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
96 { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
a8eb7ca0 97#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
406e2c48
JN		 98 { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
99 { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
100 { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
101#endif
2e74796a 102};
406e2c48
JN		 103#else
104static const int omap24xx_dma_reqs[][2] = {};
105#endif
106
107#if defined(CONFIG_ARCH_OMAP2420)
2e74796a
JN		 108static const unsigned long omap2420_mcbsp_port[][2] = {
109 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
110 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
111 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
112 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
113};
114#else
2e74796a
JN		 115static const unsigned long omap2420_mcbsp_port[][2] = {};
116#endif
117
406e2c48
JN		 118#if defined(CONFIG_ARCH_OMAP2430)
119static const unsigned long omap2430_mcbsp_port[][2] = {
120 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
121 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
122 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
123 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
124 { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
125 OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
126 { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
127 OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
128 { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
129 OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
130};
131#else
132static const unsigned long omap2430_mcbsp_port[][2] = {};
133#endif
134
a8eb7ca0 135#if defined(CONFIG_ARCH_OMAP3)
406e2c48
JN		 136static const unsigned long omap34xx_mcbsp_port[][2] = {
137 { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
138 OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
139 { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
140 OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
141 { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
142 OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
143 { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
144 OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
145 { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
146 OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
147};
148#else
149static const unsigned long omap34xx_mcbsp_port[][2] = {};
150#endif
151
caebc0cb
EV		 152static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
153{
154 struct snd_soc_pcm_runtime *rtd = substream->private_data;
155 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
156 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
a0a499c5
EV		 157 int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
158 int samples;
159
160 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
161 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
162 samples = snd_pcm_lib_period_bytes(substream) >> 1;
163 else
164 samples = 1;
caebc0cb
EV		 165
166 /* Configure McBSP internal buffer usage */
167 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
168 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, samples - 1);
169 else
170 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, samples - 1);
171}
172
dee89c4d
MB		 173static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
174 struct snd_soc_dai *dai)
2e74796a
JN		 175{
176 struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b 177 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a 178 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
caebc0cb 179 int bus_id = mcbsp_data->bus_id;
2e74796a
JN		 180 int err = 0;
181
caebc0cb
EV		 182 if (!cpu_dai->active)
183 err = omap_mcbsp_request(bus_id);
184
185 if (cpu_is_omap343x()) {
a0a499c5 186 int dma_op_mode = omap_mcbsp_get_dma_op_mode(bus_id);
caebc0cb
EV		 187 int max_period;
188
6984992b
JN		 189 /*
190 * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
191 * Set constraint for minimum buffer size to the same than FIFO
192 * size in order to avoid underruns in playback startup because
193 * HW is keeping the DMA request active until FIFO is filled.
194 */
caebc0cb
EV		 195 if (bus_id == 1)
196 snd_pcm_hw_constraint_minmax(substream->runtime,
197 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
198 4096, UINT_MAX);
199
200 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
201 max_period = omap_mcbsp_get_max_tx_threshold(bus_id);
202 else
203 max_period = omap_mcbsp_get_max_rx_threshold(bus_id);
204
205 max_period++;
206 max_period <<= 1;
207
a0a499c5
EV		 208 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
209 snd_pcm_hw_constraint_minmax(substream->runtime,
caebc0cb
EV		 210 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
211 32, max_period);
6984992b
JN		 212 }
213
2e74796a
JN		 214 return err;
215}
216
dee89c4d
MB		 217static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
218 struct snd_soc_dai *dai)
2e74796a
JN		 219{
220 struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b 221 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a
JN		 222 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
223
224 if (!cpu_dai->active) {
225 omap_mcbsp_free(mcbsp_data->bus_id);
226 mcbsp_data->configured = 0;
227 }
228}
229
dee89c4d
MB		 230static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
231 struct snd_soc_dai *dai)
2e74796a
JN		 232{
233 struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b 234 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a 235 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
c12abc01 236 int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
2e74796a
JN		 237
238 switch (cmd) {
239 case SNDRV_PCM_TRIGGER_START:
240 case SNDRV_PCM_TRIGGER_RESUME:
241 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
c12abc01
JN		 242 mcbsp_data->active++;
243 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
2e74796a
JN		 244 break;
245
246 case SNDRV_PCM_TRIGGER_STOP:
247 case SNDRV_PCM_TRIGGER_SUSPEND:
248 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
c12abc01
JN		 249 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
250 mcbsp_data->active--;
2e74796a
JN		 251 break;
252 default:
253 err = -EINVAL;
254 }
255
256 return err;
257}
258
259static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 260 struct snd_pcm_hw_params *params,
261 struct snd_soc_dai *dai)
2e74796a
JN		 262{
263 struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b 264 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a
JN		 265 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
266 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
267 int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
caebc0cb 268 int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
2e74796a 269 unsigned long port;
5f63ef99 270 unsigned int format, div, framesize, master;
2e74796a
JN		 271
272 if (cpu_class_is_omap1()) {
273 dma = omap1_dma_reqs[bus_id][substream->stream];
274 port = omap1_mcbsp_port[bus_id][substream->stream];
275 } else if (cpu_is_omap2420()) {
406e2c48 276 dma = omap24xx_dma_reqs[bus_id][substream->stream];
2e74796a 277 port = omap2420_mcbsp_port[bus_id][substream->stream];
406e2c48
JN		 278 } else if (cpu_is_omap2430()) {
279 dma = omap24xx_dma_reqs[bus_id][substream->stream];
280 port = omap2430_mcbsp_port[bus_id][substream->stream];
281 } else if (cpu_is_omap343x()) {
282 dma = omap24xx_dma_reqs[bus_id][substream->stream];
283 port = omap34xx_mcbsp_port[bus_id][substream->stream];
caebc0cb
EV		 284 omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold =
285 omap_mcbsp_set_threshold;
a0a499c5
EV		 286 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
287 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
288 MCBSP_DMA_MODE_THRESHOLD)
289 sync_mode = OMAP_DMA_SYNC_FRAME;
2e74796a 290 } else {
2e74796a
JN		 291 return -ENODEV;
292 }
2e89713a
JN		 293 omap_mcbsp_dai_dma_params[id][substream->stream].name =
294 substream->stream ? "Audio Capture" : "Audio Playback";
2e74796a
JN		 295 omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
296 omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
caebc0cb 297 omap_mcbsp_dai_dma_params[id][substream->stream].sync_mode = sync_mode;
e17dd32f
MLC		 298 omap_mcbsp_dai_dma_params[id][substream->stream].data_type =
299 OMAP_DMA_DATA_TYPE_S16;
2e74796a
JN		 300 cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
301
302 if (mcbsp_data->configured) {
303 /* McBSP already configured by another stream */
304 return 0;
305 }
306
c29b206f
PU		 307 format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
308 wpf = channels = params_channels(params);
5f63ef99
GG		 309 if (channels == 2 && format == SND_SOC_DAIFMT_I2S) {
310 /* Use dual-phase frames */
311 regs->rcr2 |= RPHASE;
312 regs->xcr2 |= XPHASE;
313 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
314 wpf--;
315 regs->rcr2 |= RFRLEN2(wpf - 1);
316 regs->xcr2 |= XFRLEN2(wpf - 1);
2e74796a
JN		 317 }
318
5f63ef99
GG		 319 regs->rcr1 |= RFRLEN1(wpf - 1);
320 regs->xcr1 |= XFRLEN1(wpf - 1);
321
2e74796a
JN		 322 switch (params_format(params)) {
323 case SNDRV_PCM_FORMAT_S16_LE:
324 /* Set word lengths */
ba9d0fd0 325 wlen = 16;
2e74796a
JN		 326 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
327 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
328 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
329 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
2e74796a
JN		 330 break;
331 default:
332 /* Unsupported PCM format */
333 return -EINVAL;
334 }
335
5f63ef99
GG		 336 /* In McBSP master modes, FRAME (i.e. sample rate) is generated
337 * by _counting_ BCLKs. Calculate frame size in BCLKs */
338 master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
339 if (master == SND_SOC_DAIFMT_CBS_CFS) {
340 div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
341 framesize = (mcbsp_data->in_freq / div) / params_rate(params);
342
343 if (framesize < wlen * channels) {
344 printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
345 "channels\n", __func__);
346 return -EINVAL;
347 }
348 } else
349 framesize = wlen * channels;
350
ba9d0fd0 351 /* Set FS period and length in terms of bit clock periods */
c29b206f 352 switch (format) {
ba9d0fd0 353 case SND_SOC_DAIFMT_I2S:
5f63ef99
GG		 354 regs->srgr2 |= FPER(framesize - 1);
355 regs->srgr1 |= FWID((framesize >> 1) - 1);
ba9d0fd0 356 break;
3ba191ce 357 case SND_SOC_DAIFMT_DSP_A:
bd25867a 358 case SND_SOC_DAIFMT_DSP_B:
5f63ef99 359 regs->srgr2 |= FPER(framesize - 1);
36ce8582 360 regs->srgr1 |= FWID(0);
ba9d0fd0
JN		 361 break;
362 }
363
2e74796a
JN		 364 omap_mcbsp_config(bus_id, &mcbsp_data->regs);
365 mcbsp_data->configured = 1;
366
367 return 0;
368}
369
370/*
371 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
372 * cache is initialized here
373 */
8687eb8b 374static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
2e74796a
JN		 375 unsigned int fmt)
376{
377 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
378 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
36ce8582 379 unsigned int temp_fmt = fmt;
2e74796a
JN		 380
381 if (mcbsp_data->configured)
382 return 0;
383
ba9d0fd0 384 mcbsp_data->fmt = fmt;
2e74796a
JN		 385 memset(regs, 0, sizeof(*regs));
386 /* Generic McBSP register settings */
387 regs->spcr2 |= XINTM(3) | FREE;
388 regs->spcr1 |= RINTM(3);
c721bbda
EN		 389 /* RFIG and XFIG are not defined in 34xx */
390 if (!cpu_is_omap34xx()) {
391 regs->rcr2 |= RFIG;
392 regs->xcr2 |= XFIG;
393 }
ef390c0b 394 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
32080af7
JN		 395 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
396 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
ef390c0b 397 }
2e74796a
JN		 398
399 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
400 case SND_SOC_DAIFMT_I2S:
401 /* 1-bit data delay */
402 regs->rcr2 |= RDATDLY(1);
403 regs->xcr2 |= XDATDLY(1);
404 break;
3ba191ce
PU		 405 case SND_SOC_DAIFMT_DSP_A:
406 /* 1-bit data delay */
407 regs->rcr2 |= RDATDLY(1);
408 regs->xcr2 |= XDATDLY(1);
409 /* Invert FS polarity configuration */
410 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
411 break;
bd25867a 412 case SND_SOC_DAIFMT_DSP_B:
3336c5b5
AK		 413 /* 0-bit data delay */
414 regs->rcr2 |= RDATDLY(0);
415 regs->xcr2 |= XDATDLY(0);
36ce8582
JN		 416 /* Invert FS polarity configuration */
417 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
3336c5b5 418 break;
2e74796a
JN		 419 default:
420 /* Unsupported data format */
421 return -EINVAL;
422 }
423
424 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
425 case SND_SOC_DAIFMT_CBS_CFS:
426 /* McBSP master. Set FS and bit clocks as outputs */
427 regs->pcr0 |= FSXM | FSRM |
428 CLKXM | CLKRM;
429 /* Sample rate generator drives the FS */
430 regs->srgr2 |= FSGM;
431 break;
432 case SND_SOC_DAIFMT_CBM_CFM:
433 /* McBSP slave */
434 break;
435 default:
436 /* Unsupported master/slave configuration */
437 return -EINVAL;
438 }
439
440 /* Set bit clock (CLKX/CLKR) and FS polarities */
36ce8582 441 switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
2e74796a
JN		 442 case SND_SOC_DAIFMT_NB_NF:
443 /*
444 * Normal BCLK + FS.
445 * FS active low. TX data driven on falling edge of bit clock
446 * and RX data sampled on rising edge of bit clock.
447 */
448 regs->pcr0 |= FSXP | FSRP |
449 CLKXP | CLKRP;
450 break;
451 case SND_SOC_DAIFMT_NB_IF:
452 regs->pcr0 |= CLKXP | CLKRP;
453 break;
454 case SND_SOC_DAIFMT_IB_NF:
455 regs->pcr0 |= FSXP | FSRP;
456 break;
457 case SND_SOC_DAIFMT_IB_IF:
458 break;
459 default:
460 return -EINVAL;
461 }
462
463 return 0;
464}
465
8687eb8b 466static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
2e74796a
JN		 467 int div_id, int div)
468{
469 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
470 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
471
472 if (div_id != OMAP_MCBSP_CLKGDV)
473 return -ENODEV;
474
5f63ef99 475 mcbsp_data->clk_div = div;
2e74796a
JN		 476 regs->srgr1 |= CLKGDV(div - 1);
477
478 return 0;
479}
480
481static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
482 int clk_id)
483{
484 int sel_bit;
406e2c48 485 u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
2e74796a
JN		 486
487 if (cpu_class_is_omap1()) {
488 /* OMAP1's can use only external source clock */
489 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
490 return -EINVAL;
491 else
492 return 0;
493 }
494
406e2c48
JN		 495 if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
496 return -EINVAL;
497
498 if (cpu_is_omap343x())
499 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
500
2e74796a
JN		 501 switch (mcbsp_data->bus_id) {
502 case 0:
503 reg = OMAP2_CONTROL_DEVCONF0;
504 sel_bit = 2;
505 break;
506 case 1:
507 reg = OMAP2_CONTROL_DEVCONF0;
508 sel_bit = 6;
509 break;
406e2c48
JN		 510 case 2:
511 reg = reg_devconf1;
512 sel_bit = 0;
513 break;
514 case 3:
515 reg = reg_devconf1;
516 sel_bit = 2;
517 break;
518 case 4:
519 reg = reg_devconf1;
520 sel_bit = 4;
521 break;
2e74796a
JN		 522 default:
523 return -EINVAL;
524 }
525
406e2c48
JN		 526 if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
527 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
528 else
529 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
2e74796a
JN		 530
531 return 0;
532}
533
d2c0bdaa
JN		 534static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data,
535 int clk_id)
536{
537 int sel_bit, set = 0;
538 u16 reg = OMAP2_CONTROL_DEVCONF0;
539
540 if (cpu_class_is_omap1())
541 return -EINVAL; /* TODO: Can this be implemented for OMAP1? */
542 if (mcbsp_data->bus_id != 0)
543 return -EINVAL;
544
545 switch (clk_id) {
546 case OMAP_MCBSP_CLKR_SRC_CLKX:
547 set = 1;
548 case OMAP_MCBSP_CLKR_SRC_CLKR:
549 sel_bit = 3;
550 break;
551 case OMAP_MCBSP_FSR_SRC_FSX:
552 set = 1;
553 case OMAP_MCBSP_FSR_SRC_FSR:
554 sel_bit = 4;
555 break;
556 default:
557 return -EINVAL;
558 }
559
560 if (set)
561 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
562 else
563 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
564
565 return 0;
566}
567
8687eb8b 568static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
2e74796a
JN		 569 int clk_id, unsigned int freq,
570 int dir)
571{
572 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
573 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
574 int err = 0;
575
5f63ef99
GG		 576 mcbsp_data->in_freq = freq;
577
2e74796a
JN		 578 switch (clk_id) {
579 case OMAP_MCBSP_SYSCLK_CLK:
580 regs->srgr2 |= CLKSM;
581 break;
582 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
583 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
584 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
585 break;
586
587 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
588 regs->srgr2 |= CLKSM;
589 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
590 regs->pcr0 |= SCLKME;
591 break;
d2c0bdaa
JN		 592
593 case OMAP_MCBSP_CLKR_SRC_CLKR:
594 case OMAP_MCBSP_CLKR_SRC_CLKX:
595 case OMAP_MCBSP_FSR_SRC_FSR:
596 case OMAP_MCBSP_FSR_SRC_FSX:
597 err = omap_mcbsp_dai_set_rcvr_src(mcbsp_data, clk_id);
598 break;
2e74796a
JN		 599 default:
600 err = -ENODEV;
601 }
602
603 return err;
604}
605
6335d055
EM		 606static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
607 .startup = omap_mcbsp_dai_startup,
608 .shutdown = omap_mcbsp_dai_shutdown,
609 .trigger = omap_mcbsp_dai_trigger,
610 .hw_params = omap_mcbsp_dai_hw_params,
611 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
612 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
613 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
614};
615
8def464d
JN		 616#define OMAP_MCBSP_DAI_BUILDER(link_id) \
617{ \
0c758bdd 618 .name = "omap-mcbsp-dai-"#link_id, \
8def464d 619 .id = (link_id), \
8def464d 620 .playback = { \
375e8a7c 621 .channels_min = 1, \
5f63ef99 622 .channels_max = 16, \
8def464d
JN		 623 .rates = OMAP_MCBSP_RATES, \
624 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
625 }, \
626 .capture = { \
375e8a7c 627 .channels_min = 1, \
5f63ef99 628 .channels_max = 16, \
8def464d
JN		 629 .rates = OMAP_MCBSP_RATES, \
630 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
631 }, \
6335d055 632 .ops = &omap_mcbsp_dai_ops, \
8def464d
JN		 633 .private_data = &mcbsp_data[(link_id)].bus_id, \
634}
635
636struct snd_soc_dai omap_mcbsp_dai[] = {
637 OMAP_MCBSP_DAI_BUILDER(0),
638 OMAP_MCBSP_DAI_BUILDER(1),
639#if NUM_LINKS >= 3
640 OMAP_MCBSP_DAI_BUILDER(2),
641#endif
642#if NUM_LINKS == 5
643 OMAP_MCBSP_DAI_BUILDER(3),
644 OMAP_MCBSP_DAI_BUILDER(4),
645#endif
2e74796a 646};
8def464d 647
2e74796a
JN		 648EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
649
83905c13
IK		 650int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
651 struct snd_ctl_elem_info *uinfo)
652{
653 struct soc_mixer_control *mc =
654 (struct soc_mixer_control *)kcontrol->private_value;
655 int max = mc->max;
656 int min = mc->min;
657
658 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
659 uinfo->count = 1;
660 uinfo->value.integer.min = min;
661 uinfo->value.integer.max = max;
662 return 0;
663}
664
665#define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel) \
666static int \
667omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
668 struct snd_ctl_elem_value *uc) \
669{ \
670 struct soc_mixer_control *mc = \
671 (struct soc_mixer_control *)kc->private_value; \
672 int max = mc->max; \
673 int min = mc->min; \
674 int val = uc->value.integer.value[0]; \
675 \
676 if (val < min || val > max) \
677 return -EINVAL; \
678 \
679 /* OMAP McBSP implementation uses index values 0..4 */ \
680 return omap_st_set_chgain((id)-1, channel, val); \
681}
682
683#define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel) \
684static int \
685omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
686 struct snd_ctl_elem_value *uc) \
687{ \
688 s16 chgain; \
689 \
690 if (omap_st_get_chgain((id)-1, channel, &chgain)) \
691 return -EAGAIN; \
692 \
693 uc->value.integer.value[0] = chgain; \
694 return 0; \
695}
696
697OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
698OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
699OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
700OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
701OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
702OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
703OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
704OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
705
706static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
707 struct snd_ctl_elem_value *ucontrol)
708{
709 struct soc_mixer_control *mc =
710 (struct soc_mixer_control *)kcontrol->private_value;
711 u8 value = ucontrol->value.integer.value[0];
712
713 if (value == omap_st_is_enabled(mc->reg))
714 return 0;
715
716 if (value)
717 omap_st_enable(mc->reg);
718 else
719 omap_st_disable(mc->reg);
720
721 return 1;
722}
723
724static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
725 struct snd_ctl_elem_value *ucontrol)
726{
727 struct soc_mixer_control *mc =
728 (struct soc_mixer_control *)kcontrol->private_value;
729
730 ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg);
731 return 0;
732}
733
734static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
735 SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
736 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
737 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
738 -32768, 32767,
739 omap_mcbsp2_get_st_ch0_volume,
740 omap_mcbsp2_set_st_ch0_volume),
741 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
742 -32768, 32767,
743 omap_mcbsp2_get_st_ch1_volume,
744 omap_mcbsp2_set_st_ch1_volume),
745};
746
747static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
748 SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
749 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
750 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
751 -32768, 32767,
752 omap_mcbsp3_get_st_ch0_volume,
753 omap_mcbsp3_set_st_ch0_volume),
754 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
755 -32768, 32767,
756 omap_mcbsp3_get_st_ch1_volume,
757 omap_mcbsp3_set_st_ch1_volume),
758};
759
760int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id)
761{
762 if (!cpu_is_omap34xx())
763 return -ENODEV;
764
765 switch (mcbsp_id) {
766 case 1: /* McBSP 2 */
767 return snd_soc_add_controls(codec, omap_mcbsp2_st_controls,
768 ARRAY_SIZE(omap_mcbsp2_st_controls));
769 case 2: /* McBSP 3 */
770 return snd_soc_add_controls(codec, omap_mcbsp3_st_controls,
771 ARRAY_SIZE(omap_mcbsp3_st_controls));
772 default:
773 break;
774 }
775
776 return -EINVAL;
777}
778EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
779
f73f2a6a 780static int __init snd_omap_mcbsp_init(void)
3f4b783c
MB		 781{
782 return snd_soc_register_dais(omap_mcbsp_dai,
783 ARRAY_SIZE(omap_mcbsp_dai));
784}
f73f2a6a 785module_init(snd_omap_mcbsp_init);
3f4b783c 786
f73f2a6a 787static void __exit snd_omap_mcbsp_exit(void)
3f4b783c
MB		 788{
789 snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
790}
f73f2a6a 791module_exit(snd_omap_mcbsp_exit);
3f4b783c 792
b08f7a62 793MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
2e74796a
JN		 794MODULE_DESCRIPTION("OMAP I2S SoC Interface");
795MODULE_LICENSE("GPL");
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