projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: McPDM: Use tabs for indentation
[deliverable/linux.git] / sound / soc / omap / omap-mcbsp.c
CommitLineData
2e74796a
JN		 1/*
2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
3 *
4 * Copyright (C) 2008 Nokia Corporation
5 *
b08f7a62
JN		 6 * Contact: Jarkko Nikula <jhnikula@gmail.com>
7 * Peter Ujfalusi <peter.ujfalusi@nokia.com>
2e74796a
JN		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/device.h>
28#include <sound/core.h>
29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/initval.h>
32#include <sound/soc.h>
33
ce491cf8
TL		 34#include <plat/control.h>
35#include <plat/dma.h>
36#include <plat/mcbsp.h>
2e74796a
JN		 37#include "omap-mcbsp.h"
38#include "omap-pcm.h"
39
0b604856 40#define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
2e74796a 41
83905c13
IK		 42#define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
43 xhandler_get, xhandler_put) \
44{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
45 .info = omap_mcbsp_st_info_volsw, \
46 .get = xhandler_get, .put = xhandler_put, \
47 .private_value = (unsigned long) &(struct soc_mixer_control) \
48 {.min = xmin, .max = xmax} }
49
2e74796a
JN		 50struct omap_mcbsp_data {
51 unsigned int bus_id;
52 struct omap_mcbsp_reg_cfg regs;
ba9d0fd0 53 unsigned int fmt;
2e74796a
JN		 54 /*
55 * Flags indicating is the bus already activated and configured by
56 * another substream
57 */
58 int active;
59 int configured;
5f63ef99
GG		 60 unsigned int in_freq;
61 int clk_div;
2e74796a
JN		 62};
63
64#define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
65
66static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
67
68/*
69 * Stream DMA parameters. DMA request line and port address are set runtime
70 * since they are different between OMAP1 and later OMAPs
71 */
2e89713a 72static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
2e74796a
JN		 73
74#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
75static const int omap1_dma_reqs[][2] = {
76 { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
77 { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
78 { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
79};
80static const unsigned long omap1_mcbsp_port[][2] = {
81 { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
82 OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
83 { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
84 OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
85 { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
86 OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
87};
88#else
89static const int omap1_dma_reqs[][2] = {};
90static const unsigned long omap1_mcbsp_port[][2] = {};
91#endif
406e2c48 92
a8eb7ca0 93#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
406e2c48 94static const int omap24xx_dma_reqs[][2] = {
2e74796a
JN		 95 { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
96 { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
a8eb7ca0 97#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
406e2c48
JN		 98 { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
99 { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
100 { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
101#endif
2e74796a 102};
406e2c48
JN		 103#else
104static const int omap24xx_dma_reqs[][2] = {};
105#endif
106
107#if defined(CONFIG_ARCH_OMAP2420)
2e74796a
JN		 108static const unsigned long omap2420_mcbsp_port[][2] = {
109 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
110 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
111 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
112 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
113};
114#else
2e74796a
JN		 115static const unsigned long omap2420_mcbsp_port[][2] = {};
116#endif
117
406e2c48
JN		 118#if defined(CONFIG_ARCH_OMAP2430)
119static const unsigned long omap2430_mcbsp_port[][2] = {
120 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
121 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
122 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
123 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
124 { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
125 OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
126 { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
127 OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
128 { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
129 OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
130};
131#else
132static const unsigned long omap2430_mcbsp_port[][2] = {};
133#endif
134
a8eb7ca0 135#if defined(CONFIG_ARCH_OMAP3)
406e2c48
JN		 136static const unsigned long omap34xx_mcbsp_port[][2] = {
137 { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
138 OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
139 { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
140 OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
141 { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
142 OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
143 { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
144 OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
145 { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
146 OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
147};
148#else
149static const unsigned long omap34xx_mcbsp_port[][2] = {};
150#endif
151
caebc0cb
EV		 152static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
153{
154 struct snd_soc_pcm_runtime *rtd = substream->private_data;
155 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
156 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
a0a499c5
EV		 157 int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
158 int samples;
159
160 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
161 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
162 samples = snd_pcm_lib_period_bytes(substream) >> 1;
163 else
164 samples = 1;
caebc0cb
EV		 165
166 /* Configure McBSP internal buffer usage */
167 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
168 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, samples - 1);
169 else
170 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, samples - 1);
171}
172
dee89c4d
MB		 173static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
174 struct snd_soc_dai *dai)
2e74796a
JN		 175{
176 struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b 177 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a 178 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
caebc0cb 179 int bus_id = mcbsp_data->bus_id;
2e74796a
JN		 180 int err = 0;
181
caebc0cb
EV		 182 if (!cpu_dai->active)
183 err = omap_mcbsp_request(bus_id);
184
185 if (cpu_is_omap343x()) {
a0a499c5 186 int dma_op_mode = omap_mcbsp_get_dma_op_mode(bus_id);
caebc0cb
EV		 187 int max_period;
188
6984992b
JN		 189 /*
190 * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
191 * Set constraint for minimum buffer size to the same than FIFO
192 * size in order to avoid underruns in playback startup because
193 * HW is keeping the DMA request active until FIFO is filled.
194 */
caebc0cb
EV		 195 if (bus_id == 1)
196 snd_pcm_hw_constraint_minmax(substream->runtime,
197 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
198 4096, UINT_MAX);
199
200 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
201 max_period = omap_mcbsp_get_max_tx_threshold(bus_id);
202 else
203 max_period = omap_mcbsp_get_max_rx_threshold(bus_id);
204
205 max_period++;
206 max_period <<= 1;
207
a0a499c5
EV		 208 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
209 snd_pcm_hw_constraint_minmax(substream->runtime,
caebc0cb
EV		 210 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
211 32, max_period);
6984992b
JN		 212 }
213
2e74796a
JN		 214 return err;
215}
216
dee89c4d
MB		 217static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
218 struct snd_soc_dai *dai)
2e74796a
JN		 219{
220 struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b 221 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a
JN		 222 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
223
224 if (!cpu_dai->active) {
225 omap_mcbsp_free(mcbsp_data->bus_id);
226 mcbsp_data->configured = 0;
227 }
228}
229
dee89c4d
MB		 230static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
231 struct snd_soc_dai *dai)
2e74796a
JN		 232{
233 struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b 234 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a 235 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
c12abc01 236 int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
2e74796a
JN		 237
238 switch (cmd) {
239 case SNDRV_PCM_TRIGGER_START:
240 case SNDRV_PCM_TRIGGER_RESUME:
241 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
c12abc01
JN		 242 mcbsp_data->active++;
243 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
2e74796a
JN		 244 break;
245
246 case SNDRV_PCM_TRIGGER_STOP:
247 case SNDRV_PCM_TRIGGER_SUSPEND:
248 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
c12abc01
JN		 249 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
250 mcbsp_data->active--;
2e74796a
JN		 251 break;
252 default:
253 err = -EINVAL;
254 }
255
256 return err;
257}
258
75581d24
PU		 259static snd_pcm_sframes_t omap_mcbsp_dai_delay(
260 struct snd_pcm_substream *substream,
261 struct snd_soc_dai *dai)
262{
263 struct snd_soc_pcm_runtime *rtd = substream->private_data;
264 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
265 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
266 u16 fifo_use;
267 snd_pcm_sframes_t delay;
268
269 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
270 fifo_use = omap_mcbsp_get_tx_delay(mcbsp_data->bus_id);
271 else
272 fifo_use = omap_mcbsp_get_rx_delay(mcbsp_data->bus_id);
273
274 /*
275 * Divide the used locations with the channel count to get the
276 * FIFO usage in samples (don't care about partial samples in the
277 * buffer).
278 */
279 delay = fifo_use / substream->runtime->channels;
280
281 return delay;
282}
283
2e74796a 284static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 285 struct snd_pcm_hw_params *params,
286 struct snd_soc_dai *dai)
2e74796a
JN		 287{
288 struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b 289 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a
JN		 290 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
291 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
292 int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
caebc0cb 293 int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
2e74796a 294 unsigned long port;
5f63ef99 295 unsigned int format, div, framesize, master;
2e74796a
JN		 296
297 if (cpu_class_is_omap1()) {
298 dma = omap1_dma_reqs[bus_id][substream->stream];
299 port = omap1_mcbsp_port[bus_id][substream->stream];
300 } else if (cpu_is_omap2420()) {
406e2c48 301 dma = omap24xx_dma_reqs[bus_id][substream->stream];
2e74796a 302 port = omap2420_mcbsp_port[bus_id][substream->stream];
406e2c48
JN		 303 } else if (cpu_is_omap2430()) {
304 dma = omap24xx_dma_reqs[bus_id][substream->stream];
305 port = omap2430_mcbsp_port[bus_id][substream->stream];
306 } else if (cpu_is_omap343x()) {
307 dma = omap24xx_dma_reqs[bus_id][substream->stream];
308 port = omap34xx_mcbsp_port[bus_id][substream->stream];
caebc0cb
EV		 309 omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold =
310 omap_mcbsp_set_threshold;
a0a499c5
EV		 311 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
312 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
313 MCBSP_DMA_MODE_THRESHOLD)
314 sync_mode = OMAP_DMA_SYNC_FRAME;
2e74796a 315 } else {
2e74796a
JN		 316 return -ENODEV;
317 }
2e89713a
JN		 318 omap_mcbsp_dai_dma_params[id][substream->stream].name =
319 substream->stream ? "Audio Capture" : "Audio Playback";
2e74796a
JN		 320 omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
321 omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
caebc0cb 322 omap_mcbsp_dai_dma_params[id][substream->stream].sync_mode = sync_mode;
e17dd32f
MLC		 323 omap_mcbsp_dai_dma_params[id][substream->stream].data_type =
324 OMAP_DMA_DATA_TYPE_S16;
2e74796a
JN		 325 cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
326
327 if (mcbsp_data->configured) {
328 /* McBSP already configured by another stream */
329 return 0;
330 }
331
c29b206f
PU		 332 format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
333 wpf = channels = params_channels(params);
5f63ef99
GG		 334 if (channels == 2 && format == SND_SOC_DAIFMT_I2S) {
335 /* Use dual-phase frames */
336 regs->rcr2 |= RPHASE;
337 regs->xcr2 |= XPHASE;
338 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
339 wpf--;
340 regs->rcr2 |= RFRLEN2(wpf - 1);
341 regs->xcr2 |= XFRLEN2(wpf - 1);
2e74796a
JN		 342 }
343
5f63ef99
GG		 344 regs->rcr1 |= RFRLEN1(wpf - 1);
345 regs->xcr1 |= XFRLEN1(wpf - 1);
346
2e74796a
JN		 347 switch (params_format(params)) {
348 case SNDRV_PCM_FORMAT_S16_LE:
349 /* Set word lengths */
ba9d0fd0 350 wlen = 16;
2e74796a
JN		 351 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
352 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
353 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
354 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
2e74796a
JN		 355 break;
356 default:
357 /* Unsupported PCM format */
358 return -EINVAL;
359 }
360
5f63ef99
GG		 361 /* In McBSP master modes, FRAME (i.e. sample rate) is generated
362 * by _counting_ BCLKs. Calculate frame size in BCLKs */
363 master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
364 if (master == SND_SOC_DAIFMT_CBS_CFS) {
365 div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
366 framesize = (mcbsp_data->in_freq / div) / params_rate(params);
367
368 if (framesize < wlen * channels) {
369 printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
370 "channels\n", __func__);
371 return -EINVAL;
372 }
373 } else
374 framesize = wlen * channels;
375
ba9d0fd0 376 /* Set FS period and length in terms of bit clock periods */
c29b206f 377 switch (format) {
ba9d0fd0 378 case SND_SOC_DAIFMT_I2S:
5f63ef99
GG		 379 regs->srgr2 |= FPER(framesize - 1);
380 regs->srgr1 |= FWID((framesize >> 1) - 1);
ba9d0fd0 381 break;
3ba191ce 382 case SND_SOC_DAIFMT_DSP_A:
bd25867a 383 case SND_SOC_DAIFMT_DSP_B:
5f63ef99 384 regs->srgr2 |= FPER(framesize - 1);
36ce8582 385 regs->srgr1 |= FWID(0);
ba9d0fd0
JN		 386 break;
387 }
388
2e74796a
JN		 389 omap_mcbsp_config(bus_id, &mcbsp_data->regs);
390 mcbsp_data->configured = 1;
391
392 return 0;
393}
394
395/*
396 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
397 * cache is initialized here
398 */
8687eb8b 399static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
2e74796a
JN		 400 unsigned int fmt)
401{
402 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
403 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
36ce8582 404 unsigned int temp_fmt = fmt;
2e74796a
JN		 405
406 if (mcbsp_data->configured)
407 return 0;
408
ba9d0fd0 409 mcbsp_data->fmt = fmt;
2e74796a
JN		 410 memset(regs, 0, sizeof(*regs));
411 /* Generic McBSP register settings */
412 regs->spcr2 |= XINTM(3) | FREE;
413 regs->spcr1 |= RINTM(3);
c721bbda
EN		 414 /* RFIG and XFIG are not defined in 34xx */
415 if (!cpu_is_omap34xx()) {
416 regs->rcr2 |= RFIG;
417 regs->xcr2 |= XFIG;
418 }
ef390c0b 419 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
32080af7
JN		 420 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
421 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
ef390c0b 422 }
2e74796a
JN		 423
424 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
425 case SND_SOC_DAIFMT_I2S:
426 /* 1-bit data delay */
427 regs->rcr2 |= RDATDLY(1);
428 regs->xcr2 |= XDATDLY(1);
429 break;
3ba191ce
PU		 430 case SND_SOC_DAIFMT_DSP_A:
431 /* 1-bit data delay */
432 regs->rcr2 |= RDATDLY(1);
433 regs->xcr2 |= XDATDLY(1);
434 /* Invert FS polarity configuration */
435 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
436 break;
bd25867a 437 case SND_SOC_DAIFMT_DSP_B:
3336c5b5
AK		 438 /* 0-bit data delay */
439 regs->rcr2 |= RDATDLY(0);
440 regs->xcr2 |= XDATDLY(0);
36ce8582
JN		 441 /* Invert FS polarity configuration */
442 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
3336c5b5 443 break;
2e74796a
JN		 444 default:
445 /* Unsupported data format */
446 return -EINVAL;
447 }
448
449 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
450 case SND_SOC_DAIFMT_CBS_CFS:
451 /* McBSP master. Set FS and bit clocks as outputs */
452 regs->pcr0 |= FSXM | FSRM |
453 CLKXM | CLKRM;
454 /* Sample rate generator drives the FS */
455 regs->srgr2 |= FSGM;
456 break;
457 case SND_SOC_DAIFMT_CBM_CFM:
458 /* McBSP slave */
459 break;
460 default:
461 /* Unsupported master/slave configuration */
462 return -EINVAL;
463 }
464
465 /* Set bit clock (CLKX/CLKR) and FS polarities */
36ce8582 466 switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
2e74796a
JN		 467 case SND_SOC_DAIFMT_NB_NF:
468 /*
469 * Normal BCLK + FS.
470 * FS active low. TX data driven on falling edge of bit clock
471 * and RX data sampled on rising edge of bit clock.
472 */
473 regs->pcr0 |= FSXP | FSRP |
474 CLKXP | CLKRP;
475 break;
476 case SND_SOC_DAIFMT_NB_IF:
477 regs->pcr0 |= CLKXP | CLKRP;
478 break;
479 case SND_SOC_DAIFMT_IB_NF:
480 regs->pcr0 |= FSXP | FSRP;
481 break;
482 case SND_SOC_DAIFMT_IB_IF:
483 break;
484 default:
485 return -EINVAL;
486 }
487
488 return 0;
489}
490
8687eb8b 491static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
2e74796a
JN		 492 int div_id, int div)
493{
494 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
495 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
496
497 if (div_id != OMAP_MCBSP_CLKGDV)
498 return -ENODEV;
499
5f63ef99 500 mcbsp_data->clk_div = div;
2e74796a
JN		 501 regs->srgr1 |= CLKGDV(div - 1);
502
503 return 0;
504}
505
506static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
507 int clk_id)
508{
509 int sel_bit;
406e2c48 510 u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
2e74796a
JN		 511
512 if (cpu_class_is_omap1()) {
513 /* OMAP1's can use only external source clock */
514 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
515 return -EINVAL;
516 else
517 return 0;
518 }
519
406e2c48
JN		 520 if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
521 return -EINVAL;
522
523 if (cpu_is_omap343x())
524 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
525
2e74796a
JN		 526 switch (mcbsp_data->bus_id) {
527 case 0:
528 reg = OMAP2_CONTROL_DEVCONF0;
529 sel_bit = 2;
530 break;
531 case 1:
532 reg = OMAP2_CONTROL_DEVCONF0;
533 sel_bit = 6;
534 break;
406e2c48
JN		 535 case 2:
536 reg = reg_devconf1;
537 sel_bit = 0;
538 break;
539 case 3:
540 reg = reg_devconf1;
541 sel_bit = 2;
542 break;
543 case 4:
544 reg = reg_devconf1;
545 sel_bit = 4;
546 break;
2e74796a
JN		 547 default:
548 return -EINVAL;
549 }
550
406e2c48
JN		 551 if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
552 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
553 else
554 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
2e74796a
JN		 555
556 return 0;
557}
558
d2c0bdaa
JN		 559static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data,
560 int clk_id)
561{
562 int sel_bit, set = 0;
563 u16 reg = OMAP2_CONTROL_DEVCONF0;
564
565 if (cpu_class_is_omap1())
566 return -EINVAL; /* TODO: Can this be implemented for OMAP1? */
567 if (mcbsp_data->bus_id != 0)
568 return -EINVAL;
569
570 switch (clk_id) {
571 case OMAP_MCBSP_CLKR_SRC_CLKX:
572 set = 1;
573 case OMAP_MCBSP_CLKR_SRC_CLKR:
574 sel_bit = 3;
575 break;
576 case OMAP_MCBSP_FSR_SRC_FSX:
577 set = 1;
578 case OMAP_MCBSP_FSR_SRC_FSR:
579 sel_bit = 4;
580 break;
581 default:
582 return -EINVAL;
583 }
584
585 if (set)
586 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
587 else
588 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
589
590 return 0;
591}
592
8687eb8b 593static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
2e74796a
JN		 594 int clk_id, unsigned int freq,
595 int dir)
596{
597 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
598 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
599 int err = 0;
600
5f63ef99
GG		 601 mcbsp_data->in_freq = freq;
602
2e74796a
JN		 603 switch (clk_id) {
604 case OMAP_MCBSP_SYSCLK_CLK:
605 regs->srgr2 |= CLKSM;
606 break;
607 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
608 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
609 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
610 break;
611
612 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
613 regs->srgr2 |= CLKSM;
614 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
615 regs->pcr0 |= SCLKME;
616 break;
d2c0bdaa
JN		 617
618 case OMAP_MCBSP_CLKR_SRC_CLKR:
619 case OMAP_MCBSP_CLKR_SRC_CLKX:
620 case OMAP_MCBSP_FSR_SRC_FSR:
621 case OMAP_MCBSP_FSR_SRC_FSX:
622 err = omap_mcbsp_dai_set_rcvr_src(mcbsp_data, clk_id);
623 break;
2e74796a
JN		 624 default:
625 err = -ENODEV;
626 }
627
628 return err;
629}
630
6335d055
EM		 631static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
632 .startup = omap_mcbsp_dai_startup,
633 .shutdown = omap_mcbsp_dai_shutdown,
634 .trigger = omap_mcbsp_dai_trigger,
75581d24 635 .delay = omap_mcbsp_dai_delay,
6335d055
EM		 636 .hw_params = omap_mcbsp_dai_hw_params,
637 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
638 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
639 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
640};
641
8def464d
JN		 642#define OMAP_MCBSP_DAI_BUILDER(link_id) \
643{ \
0c758bdd 644 .name = "omap-mcbsp-dai-"#link_id, \
8def464d 645 .id = (link_id), \
8def464d 646 .playback = { \
375e8a7c 647 .channels_min = 1, \
5f63ef99 648 .channels_max = 16, \
8def464d
JN		 649 .rates = OMAP_MCBSP_RATES, \
650 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
651 }, \
652 .capture = { \
375e8a7c 653 .channels_min = 1, \
5f63ef99 654 .channels_max = 16, \
8def464d
JN		 655 .rates = OMAP_MCBSP_RATES, \
656 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
657 }, \
6335d055 658 .ops = &omap_mcbsp_dai_ops, \
8def464d
JN		 659 .private_data = &mcbsp_data[(link_id)].bus_id, \
660}
661
662struct snd_soc_dai omap_mcbsp_dai[] = {
663 OMAP_MCBSP_DAI_BUILDER(0),
664 OMAP_MCBSP_DAI_BUILDER(1),
665#if NUM_LINKS >= 3
666 OMAP_MCBSP_DAI_BUILDER(2),
667#endif
668#if NUM_LINKS == 5
669 OMAP_MCBSP_DAI_BUILDER(3),
670 OMAP_MCBSP_DAI_BUILDER(4),
671#endif
2e74796a 672};
8def464d 673
2e74796a
JN		 674EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
675
83905c13
IK		 676int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
677 struct snd_ctl_elem_info *uinfo)
678{
679 struct soc_mixer_control *mc =
680 (struct soc_mixer_control *)kcontrol->private_value;
681 int max = mc->max;
682 int min = mc->min;
683
684 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
685 uinfo->count = 1;
686 uinfo->value.integer.min = min;
687 uinfo->value.integer.max = max;
688 return 0;
689}
690
691#define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel) \
692static int \
693omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
694 struct snd_ctl_elem_value *uc) \
695{ \
696 struct soc_mixer_control *mc = \
697 (struct soc_mixer_control *)kc->private_value; \
698 int max = mc->max; \
699 int min = mc->min; \
700 int val = uc->value.integer.value[0]; \
701 \
702 if (val < min || val > max) \
703 return -EINVAL; \
704 \
705 /* OMAP McBSP implementation uses index values 0..4 */ \
706 return omap_st_set_chgain((id)-1, channel, val); \
707}
708
709#define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel) \
710static int \
711omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
712 struct snd_ctl_elem_value *uc) \
713{ \
714 s16 chgain; \
715 \
716 if (omap_st_get_chgain((id)-1, channel, &chgain)) \
717 return -EAGAIN; \
718 \
719 uc->value.integer.value[0] = chgain; \
720 return 0; \
721}
722
723OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
724OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
725OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
726OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
727OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
728OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
729OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
730OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
731
732static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
733 struct snd_ctl_elem_value *ucontrol)
734{
735 struct soc_mixer_control *mc =
736 (struct soc_mixer_control *)kcontrol->private_value;
737 u8 value = ucontrol->value.integer.value[0];
738
739 if (value == omap_st_is_enabled(mc->reg))
740 return 0;
741
742 if (value)
743 omap_st_enable(mc->reg);
744 else
745 omap_st_disable(mc->reg);
746
747 return 1;
748}
749
750static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
751 struct snd_ctl_elem_value *ucontrol)
752{
753 struct soc_mixer_control *mc =
754 (struct soc_mixer_control *)kcontrol->private_value;
755
756 ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg);
757 return 0;
758}
759
760static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
761 SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
762 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
763 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
764 -32768, 32767,
765 omap_mcbsp2_get_st_ch0_volume,
766 omap_mcbsp2_set_st_ch0_volume),
767 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
768 -32768, 32767,
769 omap_mcbsp2_get_st_ch1_volume,
770 omap_mcbsp2_set_st_ch1_volume),
771};
772
773static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
774 SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
775 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
776 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
777 -32768, 32767,
778 omap_mcbsp3_get_st_ch0_volume,
779 omap_mcbsp3_set_st_ch0_volume),
780 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
781 -32768, 32767,
782 omap_mcbsp3_get_st_ch1_volume,
783 omap_mcbsp3_set_st_ch1_volume),
784};
785
786int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id)
787{
788 if (!cpu_is_omap34xx())
789 return -ENODEV;
790
791 switch (mcbsp_id) {
792 case 1: /* McBSP 2 */
793 return snd_soc_add_controls(codec, omap_mcbsp2_st_controls,
794 ARRAY_SIZE(omap_mcbsp2_st_controls));
795 case 2: /* McBSP 3 */
796 return snd_soc_add_controls(codec, omap_mcbsp3_st_controls,
797 ARRAY_SIZE(omap_mcbsp3_st_controls));
798 default:
799 break;
800 }
801
802 return -EINVAL;
803}
804EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
805
f73f2a6a 806static int __init snd_omap_mcbsp_init(void)
3f4b783c
MB		 807{
808 return snd_soc_register_dais(omap_mcbsp_dai,
809 ARRAY_SIZE(omap_mcbsp_dai));
810}
f73f2a6a 811module_init(snd_omap_mcbsp_init);
3f4b783c 812
f73f2a6a 813static void __exit snd_omap_mcbsp_exit(void)
3f4b783c
MB		 814{
815 snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
816}
f73f2a6a 817module_exit(snd_omap_mcbsp_exit);
3f4b783c 818
b08f7a62 819MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
2e74796a
JN		 820MODULE_DESCRIPTION("OMAP I2S SoC Interface");
821MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.142077 seconds and 5 git commands to generate.