[deliverable/linux.git] / sound / soc / omap / omap-mcbsp.c

/*
 * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
 *
 * Copyright (C) 2008 Nokia Corporation
 *
 * Contact: Jarkko Nikula <jhnikula@gmail.com>
 *          Peter Ujfalusi <peter.ujfalusi@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include <mach/control.h>
#include <mach/dma.h>
#include <mach/mcbsp.h>
#include "omap-mcbsp.h"
#include "omap-pcm.h"

#define OMAP_MCBSP_RATES	(SNDRV_PCM_RATE_8000_96000)

struct omap_mcbsp_data {
	unsigned int			bus_id;
	struct omap_mcbsp_reg_cfg	regs;
	unsigned int			fmt;
	/*
	 * Flags indicating is the bus already activated and configured by
	 * another substream
	 */
	int				active;
	int				configured;
};

#define to_mcbsp(priv)	container_of((priv), struct omap_mcbsp_data, bus_id)

static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];

/*
 * Stream DMA parameters. DMA request line and port address are set runtime
 * since they are different between OMAP1 and later OMAPs
 */
static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];

#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
static const int omap1_dma_reqs[][2] = {
	{ OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
	{ OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
	{ OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
};
static const unsigned long omap1_mcbsp_port[][2] = {
	{ OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	{ OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
	{ OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
};
#else
static const int omap1_dma_reqs[][2] = {};
static const unsigned long omap1_mcbsp_port[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
static const int omap24xx_dma_reqs[][2] = {
	{ OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
	{ OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
	{ OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
	{ OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
	{ OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
#endif
};
#else
static const int omap24xx_dma_reqs[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP2420)
static const unsigned long omap2420_mcbsp_port[][2] = {
	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
};
#else
static const unsigned long omap2420_mcbsp_port[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP2430)
static const unsigned long omap2430_mcbsp_port[][2] = {
	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
};
#else
static const unsigned long omap2430_mcbsp_port[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP34XX)
static const unsigned long omap34xx_mcbsp_port[][2] = {
	{ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
};
#else
static const unsigned long omap34xx_mcbsp_port[][2] = {};
#endif

static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	int samples = snd_pcm_lib_period_bytes(substream) >> 1;

	/* Configure McBSP internal buffer usage */
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, samples - 1);
	else
		omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, samples - 1);
}

static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	int bus_id = mcbsp_data->bus_id;
	int err = 0;

	if (!cpu_dai->active)
		err = omap_mcbsp_request(bus_id);

	if (cpu_is_omap343x()) {
		int max_period;

		/*
		 * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
		 * Set constraint for minimum buffer size to the same than FIFO
		 * size in order to avoid underruns in playback startup because
		 * HW is keeping the DMA request active until FIFO is filled.
		 */
		if (bus_id == 1)
			snd_pcm_hw_constraint_minmax(substream->runtime,
					SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
					4096, UINT_MAX);

		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			max_period = omap_mcbsp_get_max_tx_threshold(bus_id);
		else
			max_period = omap_mcbsp_get_max_rx_threshold(bus_id);

		max_period++;
		max_period <<= 1;

		snd_pcm_hw_constraint_minmax(substream->runtime,
						SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
						32, max_period);
	}

	return err;
}

static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
				    struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);

	if (!cpu_dai->active) {
		omap_mcbsp_free(mcbsp_data->bus_id);
		mcbsp_data->configured = 0;
	}
}

static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
				  struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		mcbsp_data->active++;
		omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
		/* Make sure data transfer is frame synchronized */
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			omap_mcbsp_xmit_enable(mcbsp_data->bus_id, 1);
		else
			omap_mcbsp_recv_enable(mcbsp_data->bus_id, 1);
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
		mcbsp_data->active--;
		break;
	default:
		err = -EINVAL;
	}

	return err;
}

static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
	int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
	unsigned long port;
	unsigned int format;

	if (cpu_class_is_omap1()) {
		dma = omap1_dma_reqs[bus_id][substream->stream];
		port = omap1_mcbsp_port[bus_id][substream->stream];
	} else if (cpu_is_omap2420()) {
		dma = omap24xx_dma_reqs[bus_id][substream->stream];
		port = omap2420_mcbsp_port[bus_id][substream->stream];
	} else if (cpu_is_omap2430()) {
		dma = omap24xx_dma_reqs[bus_id][substream->stream];
		port = omap2430_mcbsp_port[bus_id][substream->stream];
	} else if (cpu_is_omap343x()) {
		dma = omap24xx_dma_reqs[bus_id][substream->stream];
		port = omap34xx_mcbsp_port[bus_id][substream->stream];
		omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold =
						omap_mcbsp_set_threshold;
		sync_mode = OMAP_DMA_SYNC_FRAME;
	} else {
		return -ENODEV;
	}
	omap_mcbsp_dai_dma_params[id][substream->stream].name =
		substream->stream ? "Audio Capture" : "Audio Playback";
	omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
	omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
	omap_mcbsp_dai_dma_params[id][substream->stream].sync_mode = sync_mode;
	cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];

	if (mcbsp_data->configured) {
		/* McBSP already configured by another stream */
		return 0;
	}

	format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
	wpf = channels = params_channels(params);
	switch (channels) {
	case 2:
		if (format == SND_SOC_DAIFMT_I2S) {
			/* Use dual-phase frames */
			regs->rcr2	|= RPHASE;
			regs->xcr2	|= XPHASE;
			/* Set 1 word per (McBSP) frame for phase1 and phase2 */
			wpf--;
			regs->rcr2	|= RFRLEN2(wpf - 1);
			regs->xcr2	|= XFRLEN2(wpf - 1);
		}
	case 1:
	case 4:
		/* Set word per (McBSP) frame for phase1 */
		regs->rcr1	|= RFRLEN1(wpf - 1);
		regs->xcr1	|= XFRLEN1(wpf - 1);
		break;
	default:
		/* Unsupported number of channels */
		return -EINVAL;
	}

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		/* Set word lengths */
		wlen = 16;
		regs->rcr2	|= RWDLEN2(OMAP_MCBSP_WORD_16);
		regs->rcr1	|= RWDLEN1(OMAP_MCBSP_WORD_16);
		regs->xcr2	|= XWDLEN2(OMAP_MCBSP_WORD_16);
		regs->xcr1	|= XWDLEN1(OMAP_MCBSP_WORD_16);
		break;
	default:
		/* Unsupported PCM format */
		return -EINVAL;
	}

	/* Set FS period and length in terms of bit clock periods */
	switch (format) {
	case SND_SOC_DAIFMT_I2S:
		regs->srgr2	|= FPER(wlen * channels - 1);
		regs->srgr1	|= FWID(wlen - 1);
		break;
	case SND_SOC_DAIFMT_DSP_A:
	case SND_SOC_DAIFMT_DSP_B:
		regs->srgr2	|= FPER(wlen * channels - 1);
		regs->srgr1	|= FWID(0);
		break;
	}

	omap_mcbsp_config(bus_id, &mcbsp_data->regs);
	mcbsp_data->configured = 1;

	return 0;
}

/*
 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 * cache is initialized here
 */
static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
				      unsigned int fmt)
{
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	unsigned int temp_fmt = fmt;

	if (mcbsp_data->configured)
		return 0;

	mcbsp_data->fmt = fmt;
	memset(regs, 0, sizeof(*regs));
	/* Generic McBSP register settings */
	regs->spcr2	|= XINTM(3) | FREE;
	regs->spcr1	|= RINTM(3);
	/* RFIG and XFIG are not defined in 34xx */
	if (!cpu_is_omap34xx()) {
		regs->rcr2	|= RFIG;
		regs->xcr2	|= XFIG;
	}
	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
		regs->xccr = DXENDLY(1) | XDMAEN;
		regs->rccr = RFULL_CYCLE | RDMAEN;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		/* 1-bit data delay */
		regs->rcr2	|= RDATDLY(1);
		regs->xcr2	|= XDATDLY(1);
		regs->rccr	|= RFULL_CYCLE | RDMAEN | RDISABLE;
		regs->xccr	|= (DXENDLY(1) | XDMAEN | XDISABLE);
		break;
	case SND_SOC_DAIFMT_DSP_A:
		/* 1-bit data delay */
		regs->rcr2      |= RDATDLY(1);
		regs->xcr2      |= XDATDLY(1);
		regs->rccr	|= RFULL_CYCLE | RDMAEN | RDISABLE;
		regs->xccr	|= (DXENDLY(1) | XDMAEN | XDISABLE);
		/* Invert FS polarity configuration */
		temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
		break;
	case SND_SOC_DAIFMT_DSP_B:
		/* 0-bit data delay */
		regs->rcr2      |= RDATDLY(0);
		regs->xcr2      |= XDATDLY(0);
		/* Invert FS polarity configuration */
		temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
		break;
	default:
		/* Unsupported data format */
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* McBSP master. Set FS and bit clocks as outputs */
		regs->pcr0	|= FSXM | FSRM |
				   CLKXM | CLKRM;
		/* Sample rate generator drives the FS */
		regs->srgr2	|= FSGM;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		/* McBSP slave */
		break;
	default:
		/* Unsupported master/slave configuration */
		return -EINVAL;
	}

	/* Set bit clock (CLKX/CLKR) and FS polarities */
	switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		/*
		 * Normal BCLK + FS.
		 * FS active low. TX data driven on falling edge of bit clock
		 * and RX data sampled on rising edge of bit clock.
		 */
		regs->pcr0	|= FSXP | FSRP |
				   CLKXP | CLKRP;
		break;
	case SND_SOC_DAIFMT_NB_IF:
		regs->pcr0	|= CLKXP | CLKRP;
		break;
	case SND_SOC_DAIFMT_IB_NF:
		regs->pcr0	|= FSXP | FSRP;
		break;
	case SND_SOC_DAIFMT_IB_IF:
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
				     int div_id, int div)
{
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;

	if (div_id != OMAP_MCBSP_CLKGDV)
		return -ENODEV;

	regs->srgr1	|= CLKGDV(div - 1);

	return 0;
}

static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
				       int clk_id)
{
	int sel_bit;
	u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;

	if (cpu_class_is_omap1()) {
		/* OMAP1's can use only external source clock */
		if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
			return -EINVAL;
		else
			return 0;
	}

	if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
		return -EINVAL;

	if (cpu_is_omap343x())
		reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;

	switch (mcbsp_data->bus_id) {
	case 0:
		reg = OMAP2_CONTROL_DEVCONF0;
		sel_bit = 2;
		break;
	case 1:
		reg = OMAP2_CONTROL_DEVCONF0;
		sel_bit = 6;
		break;
	case 2:
		reg = reg_devconf1;
		sel_bit = 0;
		break;
	case 3:
		reg = reg_devconf1;
		sel_bit = 2;
		break;
	case 4:
		reg = reg_devconf1;
		sel_bit = 4;
		break;
	default:
		return -EINVAL;
	}

	if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
		omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
	else
		omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);

	return 0;
}

static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
					 int clk_id, unsigned int freq,
					 int dir)
{
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	int err = 0;

	switch (clk_id) {
	case OMAP_MCBSP_SYSCLK_CLK:
		regs->srgr2	|= CLKSM;
		break;
	case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
	case OMAP_MCBSP_SYSCLK_CLKS_EXT:
		err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
		break;

	case OMAP_MCBSP_SYSCLK_CLKX_EXT:
		regs->srgr2	|= CLKSM;
	case OMAP_MCBSP_SYSCLK_CLKR_EXT:
		regs->pcr0	|= SCLKME;
		break;
	default:
		err = -ENODEV;
	}

	return err;
}

static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
	.startup	= omap_mcbsp_dai_startup,
	.shutdown	= omap_mcbsp_dai_shutdown,
	.trigger	= omap_mcbsp_dai_trigger,
	.hw_params	= omap_mcbsp_dai_hw_params,
	.set_fmt	= omap_mcbsp_dai_set_dai_fmt,
	.set_clkdiv	= omap_mcbsp_dai_set_clkdiv,
	.set_sysclk	= omap_mcbsp_dai_set_dai_sysclk,
};

#define OMAP_MCBSP_DAI_BUILDER(link_id)				\
{								\
	.name = "omap-mcbsp-dai-"#link_id,			\
	.id = (link_id),					\
	.playback = {						\
		.channels_min = 1,				\
		.channels_max = 4,				\
		.rates = OMAP_MCBSP_RATES,			\
		.formats = SNDRV_PCM_FMTBIT_S16_LE,		\
	},							\
	.capture = {						\
		.channels_min = 1,				\
		.channels_max = 4,				\
		.rates = OMAP_MCBSP_RATES,			\
		.formats = SNDRV_PCM_FMTBIT_S16_LE,		\
	},							\
	.ops = &omap_mcbsp_dai_ops,				\
	.private_data = &mcbsp_data[(link_id)].bus_id,		\
}

struct snd_soc_dai omap_mcbsp_dai[] = {
	OMAP_MCBSP_DAI_BUILDER(0),
	OMAP_MCBSP_DAI_BUILDER(1),
#if NUM_LINKS >= 3
	OMAP_MCBSP_DAI_BUILDER(2),
#endif
#if NUM_LINKS == 5
	OMAP_MCBSP_DAI_BUILDER(3),
	OMAP_MCBSP_DAI_BUILDER(4),
#endif
};

EXPORT_SYMBOL_GPL(omap_mcbsp_dai);

static int __init snd_omap_mcbsp_init(void)
{
	return snd_soc_register_dais(omap_mcbsp_dai,
				     ARRAY_SIZE(omap_mcbsp_dai));
}
module_init(snd_omap_mcbsp_init);

static void __exit snd_omap_mcbsp_exit(void)
{
	snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
}
module_exit(snd_omap_mcbsp_exit);

MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
MODULE_DESCRIPTION("OMAP I2S SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
2e74796a JN	1	/*
	2	* omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
	3	*
	4	* Copyright (C) 2008 Nokia Corporation
	5	*
b08f7a62 JN	6	* Contact: Jarkko Nikula <jhnikula@gmail.com>
b08f7a62 JN	7	* Peter Ujfalusi <peter.ujfalusi@nokia.com>
2e74796a JN	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* version 2 as published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	16	* General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	21	* 02110-1301 USA
	22	*
	23	*/
	24
	25	#include <linux/init.h>
	26	#include <linux/module.h>
	27	#include <linux/device.h>
	28	#include <sound/core.h>
	29	#include <sound/pcm.h>
	30	#include <sound/pcm_params.h>
	31	#include <sound/initval.h>
	32	#include <sound/soc.h>
	33
a09e64fb RK	34	#include <mach/control.h>
	35	#include <mach/dma.h>
	36	#include <mach/mcbsp.h>
2e74796a JN	37	#include "omap-mcbsp.h"
	38	#include "omap-pcm.h"
	39
0b604856	40	#define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
2e74796a JN	41
	42	struct omap_mcbsp_data {
	43	unsigned int bus_id;
	44	struct omap_mcbsp_reg_cfg regs;
ba9d0fd0	45	unsigned int fmt;
2e74796a JN	46	/*
	47	* Flags indicating is the bus already activated and configured by
	48	* another substream
	49	*/
	50	int active;
	51	int configured;
	52	};
	53
	54	#define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
	55
	56	static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
	57
	58	/*
	59	* Stream DMA parameters. DMA request line and port address are set runtime
	60	* since they are different between OMAP1 and later OMAPs
	61	*/
2e89713a	62	static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
2e74796a JN	63
	64	#if defined(CONFIG_ARCH_OMAP15XX) \|\| defined(CONFIG_ARCH_OMAP16XX)
	65	static const int omap1_dma_reqs[][2] = {
	66	{ OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
	67	{ OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
	68	{ OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
	69	};
	70	static const unsigned long omap1_mcbsp_port[][2] = {
	71	{ OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	72	OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	73	{ OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	74	OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
	75	{ OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
	76	OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
	77	};
	78	#else
	79	static const int omap1_dma_reqs[][2] = {};
	80	static const unsigned long omap1_mcbsp_port[][2] = {};
	81	#endif
406e2c48 JN	82
	83	#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
	84	static const int omap24xx_dma_reqs[][2] = {
2e74796a JN	85	{ OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
2e74796a JN	86	{ OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
406e2c48 JN	87	#if defined(CONFIG_ARCH_OMAP2430) \|\| defined(CONFIG_ARCH_OMAP34XX)
	88	{ OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
	89	{ OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
	90	{ OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
	91	#endif
2e74796a	92	};
406e2c48 JN	93	#else
	94	static const int omap24xx_dma_reqs[][2] = {};
	95	#endif
	96
	97	#if defined(CONFIG_ARCH_OMAP2420)
2e74796a JN	98	static const unsigned long omap2420_mcbsp_port[][2] = {
	99	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	100	OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	101	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	102	OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
	103	};
	104	#else
2e74796a JN	105	static const unsigned long omap2420_mcbsp_port[][2] = {};
	106	#endif
	107
406e2c48 JN	108	#if defined(CONFIG_ARCH_OMAP2430)
	109	static const unsigned long omap2430_mcbsp_port[][2] = {
	110	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	111	OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	112	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	113	OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	114	{ OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	115	OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	116	{ OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	117	OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	118	{ OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	119	OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
	120	};
	121	#else
	122	static const unsigned long omap2430_mcbsp_port[][2] = {};
	123	#endif
	124
	125	#if defined(CONFIG_ARCH_OMAP34XX)
	126	static const unsigned long omap34xx_mcbsp_port[][2] = {
	127	{ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	128	OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	129	{ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	130	OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	131	{ OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	132	OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	133	{ OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	134	OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	135	{ OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	136	OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
	137	};
	138	#else
	139	static const unsigned long omap34xx_mcbsp_port[][2] = {};
	140	#endif
	141
caebc0cb EV	142	static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
	143	{
	144	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	145	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	146	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	147	int samples = snd_pcm_lib_period_bytes(substream) >> 1;
	148
	149	/* Configure McBSP internal buffer usage */
	150	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	151	omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, samples - 1);
	152	else
	153	omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, samples - 1);
	154	}
	155
dee89c4d MB	156	static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
dee89c4d MB	157	struct snd_soc_dai *dai)
2e74796a JN	158	{
2e74796a JN	159	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	160	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a	161	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
caebc0cb	162	int bus_id = mcbsp_data->bus_id;
2e74796a JN	163	int err = 0;
2e74796a JN	164
caebc0cb EV	165	if (!cpu_dai->active)
	166	err = omap_mcbsp_request(bus_id);
	167
	168	if (cpu_is_omap343x()) {
	169	int max_period;
	170
6984992b JN	171	/*
	172	* McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
	173	* Set constraint for minimum buffer size to the same than FIFO
	174	* size in order to avoid underruns in playback startup because
	175	* HW is keeping the DMA request active until FIFO is filled.
	176	*/
caebc0cb EV	177	if (bus_id == 1)
	178	snd_pcm_hw_constraint_minmax(substream->runtime,
	179	SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
	180	4096, UINT_MAX);
	181
	182	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	183	max_period = omap_mcbsp_get_max_tx_threshold(bus_id);
	184	else
	185	max_period = omap_mcbsp_get_max_rx_threshold(bus_id);
	186
	187	max_period++;
	188	max_period <<= 1;
	189
6984992b	190	snd_pcm_hw_constraint_minmax(substream->runtime,
caebc0cb EV	191	SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
caebc0cb EV	192	32, max_period);
6984992b JN	193	}
6984992b JN	194
2e74796a JN	195	return err;
	196	}
	197
dee89c4d MB	198	static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
dee89c4d MB	199	struct snd_soc_dai *dai)
2e74796a JN	200	{
2e74796a JN	201	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	202	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	203	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	204
	205	if (!cpu_dai->active) {
	206	omap_mcbsp_free(mcbsp_data->bus_id);
	207	mcbsp_data->configured = 0;
	208	}
	209	}
	210
dee89c4d MB	211	static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
dee89c4d MB	212	struct snd_soc_dai *dai)
2e74796a JN	213	{
2e74796a JN	214	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	215	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a	216	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
c12abc01	217	int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
2e74796a JN	218
	219	switch (cmd) {
	220	case SNDRV_PCM_TRIGGER_START:
	221	case SNDRV_PCM_TRIGGER_RESUME:
	222	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
c12abc01 JN	223	mcbsp_data->active++;
c12abc01 JN	224	omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
ca6e2ce0 EN	225	/* Make sure data transfer is frame synchronized */
	226	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	227	omap_mcbsp_xmit_enable(mcbsp_data->bus_id, 1);
	228	else
	229	omap_mcbsp_recv_enable(mcbsp_data->bus_id, 1);
2e74796a JN	230	break;
	231
	232	case SNDRV_PCM_TRIGGER_STOP:
	233	case SNDRV_PCM_TRIGGER_SUSPEND:
	234	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
c12abc01 JN	235	omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
c12abc01 JN	236	mcbsp_data->active--;
2e74796a JN	237	break;
	238	default:
	239	err = -EINVAL;
	240	}
	241
	242	return err;
	243	}
	244
	245	static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	246	struct snd_pcm_hw_params *params,
dee89c4d MB	247	struct snd_soc_dai *dai)
2e74796a JN	248	{
2e74796a JN	249	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	250	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	251	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	252	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	253	int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
caebc0cb	254	int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
2e74796a	255	unsigned long port;
c29b206f	256	unsigned int format;
2e74796a JN	257
	258	if (cpu_class_is_omap1()) {
	259	dma = omap1_dma_reqs[bus_id][substream->stream];
	260	port = omap1_mcbsp_port[bus_id][substream->stream];
	261	} else if (cpu_is_omap2420()) {
406e2c48	262	dma = omap24xx_dma_reqs[bus_id][substream->stream];
2e74796a	263	port = omap2420_mcbsp_port[bus_id][substream->stream];
406e2c48 JN	264	} else if (cpu_is_omap2430()) {
	265	dma = omap24xx_dma_reqs[bus_id][substream->stream];
	266	port = omap2430_mcbsp_port[bus_id][substream->stream];
	267	} else if (cpu_is_omap343x()) {
	268	dma = omap24xx_dma_reqs[bus_id][substream->stream];
	269	port = omap34xx_mcbsp_port[bus_id][substream->stream];
caebc0cb EV	270	omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold =
	271	omap_mcbsp_set_threshold;
	272	sync_mode = OMAP_DMA_SYNC_FRAME;
2e74796a	273	} else {
2e74796a JN	274	return -ENODEV;
2e74796a JN	275	}
2e89713a JN	276	omap_mcbsp_dai_dma_params[id][substream->stream].name =
2e89713a JN	277	substream->stream ? "Audio Capture" : "Audio Playback";
2e74796a JN	278	omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
2e74796a JN	279	omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
caebc0cb	280	omap_mcbsp_dai_dma_params[id][substream->stream].sync_mode = sync_mode;
2e74796a JN	281	cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
	282
	283	if (mcbsp_data->configured) {
	284	/* McBSP already configured by another stream */
	285	return 0;
	286	}
	287
c29b206f PU	288	format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
c29b206f PU	289	wpf = channels = params_channels(params);
375e8a7c	290	switch (channels) {
2e74796a	291	case 2:
c29b206f PU	292	if (format == SND_SOC_DAIFMT_I2S) {
	293	/* Use dual-phase frames */
	294	regs->rcr2 \|= RPHASE;
	295	regs->xcr2 \|= XPHASE;
	296	/* Set 1 word per (McBSP) frame for phase1 and phase2 */
	297	wpf--;
	298	regs->rcr2 \|= RFRLEN2(wpf - 1);
	299	regs->xcr2 \|= XFRLEN2(wpf - 1);
	300	}
375e8a7c	301	case 1:
31a00c6b	302	case 4:
c29b206f PU	303	/* Set word per (McBSP) frame for phase1 */
	304	regs->rcr1 \|= RFRLEN1(wpf - 1);
	305	regs->xcr1 \|= XFRLEN1(wpf - 1);
2e74796a JN	306	break;
	307	default:
	308	/* Unsupported number of channels */
	309	return -EINVAL;
	310	}
	311
	312	switch (params_format(params)) {
	313	case SNDRV_PCM_FORMAT_S16_LE:
	314	/* Set word lengths */
ba9d0fd0	315	wlen = 16;
2e74796a JN	316	regs->rcr2 \|= RWDLEN2(OMAP_MCBSP_WORD_16);
	317	regs->rcr1 \|= RWDLEN1(OMAP_MCBSP_WORD_16);
	318	regs->xcr2 \|= XWDLEN2(OMAP_MCBSP_WORD_16);
	319	regs->xcr1 \|= XWDLEN1(OMAP_MCBSP_WORD_16);
2e74796a JN	320	break;
	321	default:
	322	/* Unsupported PCM format */
	323	return -EINVAL;
	324	}
	325
ba9d0fd0	326	/* Set FS period and length in terms of bit clock periods */
c29b206f	327	switch (format) {
ba9d0fd0	328	case SND_SOC_DAIFMT_I2S:
c29b206f	329	regs->srgr2 \|= FPER(wlen * channels - 1);
ba9d0fd0 JN	330	regs->srgr1 \|= FWID(wlen - 1);
ba9d0fd0 JN	331	break;
3ba191ce	332	case SND_SOC_DAIFMT_DSP_A:
bd25867a	333	case SND_SOC_DAIFMT_DSP_B:
375e8a7c	334	regs->srgr2 \|= FPER(wlen * channels - 1);
36ce8582	335	regs->srgr1 \|= FWID(0);
ba9d0fd0 JN	336	break;
	337	}
	338
2e74796a JN	339	omap_mcbsp_config(bus_id, &mcbsp_data->regs);
	340	mcbsp_data->configured = 1;
	341
	342	return 0;
	343	}
	344
	345	/*
	346	* This must be called before _set_clkdiv and _set_sysclk since McBSP register
	347	* cache is initialized here
	348	*/
8687eb8b	349	static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
2e74796a JN	350	unsigned int fmt)
	351	{
	352	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	353	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
36ce8582	354	unsigned int temp_fmt = fmt;
2e74796a JN	355
	356	if (mcbsp_data->configured)
	357	return 0;
	358
ba9d0fd0	359	mcbsp_data->fmt = fmt;
2e74796a JN	360	memset(regs, 0, sizeof(*regs));
	361	/* Generic McBSP register settings */
	362	regs->spcr2 \|= XINTM(3) \| FREE;
	363	regs->spcr1 \|= RINTM(3);
c721bbda EN	364	/* RFIG and XFIG are not defined in 34xx */
	365	if (!cpu_is_omap34xx()) {
	366	regs->rcr2 \|= RFIG;
	367	regs->xcr2 \|= XFIG;
	368	}
ef390c0b MLC	369	if (cpu_is_omap2430() \|\| cpu_is_omap34xx()) {
	370	regs->xccr = DXENDLY(1) \| XDMAEN;
	371	regs->rccr = RFULL_CYCLE \| RDMAEN;
	372	}
2e74796a JN	373
	374	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	375	case SND_SOC_DAIFMT_I2S:
	376	/* 1-bit data delay */
	377	regs->rcr2 \|= RDATDLY(1);
	378	regs->xcr2 \|= XDATDLY(1);
ca6e2ce0 EN	379	regs->rccr \|= RFULL_CYCLE \| RDMAEN \| RDISABLE;
ca6e2ce0 EN	380	regs->xccr \|= (DXENDLY(1) \| XDMAEN \| XDISABLE);
2e74796a	381	break;
3ba191ce PU	382	case SND_SOC_DAIFMT_DSP_A:
	383	/* 1-bit data delay */
	384	regs->rcr2 \|= RDATDLY(1);
	385	regs->xcr2 \|= XDATDLY(1);
ca6e2ce0 EN	386	regs->rccr \|= RFULL_CYCLE \| RDMAEN \| RDISABLE;
ca6e2ce0 EN	387	regs->xccr \|= (DXENDLY(1) \| XDMAEN \| XDISABLE);
3ba191ce PU	388	/* Invert FS polarity configuration */
	389	temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
	390	break;
bd25867a	391	case SND_SOC_DAIFMT_DSP_B:
3336c5b5 AK	392	/* 0-bit data delay */
	393	regs->rcr2 \|= RDATDLY(0);
	394	regs->xcr2 \|= XDATDLY(0);
36ce8582 JN	395	/* Invert FS polarity configuration */
36ce8582 JN	396	temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
3336c5b5	397	break;
2e74796a JN	398	default:
	399	/* Unsupported data format */
	400	return -EINVAL;
	401	}
	402
	403	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	404	case SND_SOC_DAIFMT_CBS_CFS:
	405	/* McBSP master. Set FS and bit clocks as outputs */
	406	regs->pcr0 \|= FSXM \| FSRM \|
	407	CLKXM \| CLKRM;
	408	/* Sample rate generator drives the FS */
	409	regs->srgr2 \|= FSGM;
	410	break;
	411	case SND_SOC_DAIFMT_CBM_CFM:
	412	/* McBSP slave */
	413	break;
	414	default:
	415	/* Unsupported master/slave configuration */
	416	return -EINVAL;
	417	}
	418
	419	/* Set bit clock (CLKX/CLKR) and FS polarities */
36ce8582	420	switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
2e74796a JN	421	case SND_SOC_DAIFMT_NB_NF:
	422	/*
	423	* Normal BCLK + FS.
	424	* FS active low. TX data driven on falling edge of bit clock
	425	* and RX data sampled on rising edge of bit clock.
	426	*/
	427	regs->pcr0 \|= FSXP \| FSRP \|
	428	CLKXP \| CLKRP;
	429	break;
	430	case SND_SOC_DAIFMT_NB_IF:
	431	regs->pcr0 \|= CLKXP \| CLKRP;
	432	break;
	433	case SND_SOC_DAIFMT_IB_NF:
	434	regs->pcr0 \|= FSXP \| FSRP;
	435	break;
	436	case SND_SOC_DAIFMT_IB_IF:
	437	break;
	438	default:
	439	return -EINVAL;
	440	}
	441
	442	return 0;
	443	}
	444
8687eb8b	445	static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
2e74796a JN	446	int div_id, int div)
	447	{
	448	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	449	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	450
	451	if (div_id != OMAP_MCBSP_CLKGDV)
	452	return -ENODEV;
	453
	454	regs->srgr1 \|= CLKGDV(div - 1);
	455
	456	return 0;
	457	}
	458
	459	static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
	460	int clk_id)
	461	{
	462	int sel_bit;
406e2c48	463	u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
2e74796a JN	464
	465	if (cpu_class_is_omap1()) {
	466	/* OMAP1's can use only external source clock */
	467	if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
	468	return -EINVAL;
	469	else
	470	return 0;
	471	}
	472
406e2c48 JN	473	if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
	474	return -EINVAL;
	475
	476	if (cpu_is_omap343x())
	477	reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
	478
2e74796a JN	479	switch (mcbsp_data->bus_id) {
	480	case 0:
	481	reg = OMAP2_CONTROL_DEVCONF0;
	482	sel_bit = 2;
	483	break;
	484	case 1:
	485	reg = OMAP2_CONTROL_DEVCONF0;
	486	sel_bit = 6;
	487	break;
406e2c48 JN	488	case 2:
	489	reg = reg_devconf1;
	490	sel_bit = 0;
	491	break;
	492	case 3:
	493	reg = reg_devconf1;
	494	sel_bit = 2;
	495	break;
	496	case 4:
	497	reg = reg_devconf1;
	498	sel_bit = 4;
	499	break;
2e74796a JN	500	default:
	501	return -EINVAL;
	502	}
	503
406e2c48 JN	504	if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
	505	omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
	506	else
	507	omap_ctrl_writel(omap_ctrl_readl(reg) \| (1 << sel_bit), reg);
2e74796a JN	508
	509	return 0;
	510	}
	511
8687eb8b	512	static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
2e74796a JN	513	int clk_id, unsigned int freq,
	514	int dir)
	515	{
	516	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	517	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	518	int err = 0;
	519
	520	switch (clk_id) {
	521	case OMAP_MCBSP_SYSCLK_CLK:
	522	regs->srgr2 \|= CLKSM;
	523	break;
	524	case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
	525	case OMAP_MCBSP_SYSCLK_CLKS_EXT:
	526	err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
	527	break;
	528
	529	case OMAP_MCBSP_SYSCLK_CLKX_EXT:
	530	regs->srgr2 \|= CLKSM;
	531	case OMAP_MCBSP_SYSCLK_CLKR_EXT:
	532	regs->pcr0 \|= SCLKME;
	533	break;
	534	default:
	535	err = -ENODEV;
	536	}
	537
	538	return err;
	539	}
	540
6335d055 EM	541	static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
	542	.startup = omap_mcbsp_dai_startup,
	543	.shutdown = omap_mcbsp_dai_shutdown,
	544	.trigger = omap_mcbsp_dai_trigger,
	545	.hw_params = omap_mcbsp_dai_hw_params,
	546	.set_fmt = omap_mcbsp_dai_set_dai_fmt,
	547	.set_clkdiv = omap_mcbsp_dai_set_clkdiv,
	548	.set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
	549	};
	550
8def464d JN	551	#define OMAP_MCBSP_DAI_BUILDER(link_id) \
8def464d JN	552	{ \
0c758bdd	553	.name = "omap-mcbsp-dai-"#link_id, \
8def464d	554	.id = (link_id), \
8def464d	555	.playback = { \
375e8a7c	556	.channels_min = 1, \
31a00c6b	557	.channels_max = 4, \
8def464d JN	558	.rates = OMAP_MCBSP_RATES, \
	559	.formats = SNDRV_PCM_FMTBIT_S16_LE, \
	560	}, \
	561	.capture = { \
375e8a7c	562	.channels_min = 1, \
31a00c6b	563	.channels_max = 4, \
8def464d JN	564	.rates = OMAP_MCBSP_RATES, \
	565	.formats = SNDRV_PCM_FMTBIT_S16_LE, \
	566	}, \
6335d055	567	.ops = &omap_mcbsp_dai_ops, \
8def464d JN	568	.private_data = &mcbsp_data[(link_id)].bus_id, \
	569	}
	570
	571	struct snd_soc_dai omap_mcbsp_dai[] = {
	572	OMAP_MCBSP_DAI_BUILDER(0),
	573	OMAP_MCBSP_DAI_BUILDER(1),
	574	#if NUM_LINKS >= 3
	575	OMAP_MCBSP_DAI_BUILDER(2),
	576	#endif
	577	#if NUM_LINKS == 5
	578	OMAP_MCBSP_DAI_BUILDER(3),
	579	OMAP_MCBSP_DAI_BUILDER(4),
	580	#endif
2e74796a	581	};
8def464d	582
2e74796a JN	583	EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
2e74796a JN	584
f73f2a6a	585	static int __init snd_omap_mcbsp_init(void)
3f4b783c MB	586	{
	587	return snd_soc_register_dais(omap_mcbsp_dai,
	588	ARRAY_SIZE(omap_mcbsp_dai));
	589	}
f73f2a6a	590	module_init(snd_omap_mcbsp_init);
3f4b783c	591
f73f2a6a	592	static void __exit snd_omap_mcbsp_exit(void)
3f4b783c MB	593	{
	594	snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
	595	}
f73f2a6a	596	module_exit(snd_omap_mcbsp_exit);
3f4b783c	597
b08f7a62	598	MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
2e74796a JN	599	MODULE_DESCRIPTION("OMAP I2S SoC Interface");
2e74796a JN	600	MODULE_LICENSE("GPL");