Commit | Line | Data |
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2e74796a JN |
1 | /* |
2 | * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port | |
3 | * | |
4 | * Copyright (C) 2008 Nokia Corporation | |
5 | * | |
7ec41ee5 | 6 | * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com> |
56a87429 | 7 | * Peter Ujfalusi <peter.ujfalusi@ti.com> |
2e74796a JN |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <linux/init.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/device.h> | |
28 | #include <sound/core.h> | |
29 | #include <sound/pcm.h> | |
30 | #include <sound/pcm_params.h> | |
31 | #include <sound/initval.h> | |
32 | #include <sound/soc.h> | |
33 | ||
ce491cf8 TL |
34 | #include <plat/dma.h> |
35 | #include <plat/mcbsp.h> | |
219f4316 | 36 | #include "mcbsp.h" |
2e74796a JN |
37 | #include "omap-mcbsp.h" |
38 | #include "omap-pcm.h" | |
39 | ||
0b604856 | 40 | #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000) |
2e74796a | 41 | |
83905c13 IK |
42 | #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \ |
43 | xhandler_get, xhandler_put) \ | |
44 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
45 | .info = omap_mcbsp_st_info_volsw, \ | |
46 | .get = xhandler_get, .put = xhandler_put, \ | |
47 | .private_value = (unsigned long) &(struct soc_mixer_control) \ | |
48 | {.min = xmin, .max = xmax} } | |
49 | ||
219f4316 PU |
50 | enum { |
51 | OMAP_MCBSP_WORD_8 = 0, | |
52 | OMAP_MCBSP_WORD_12, | |
53 | OMAP_MCBSP_WORD_16, | |
54 | OMAP_MCBSP_WORD_20, | |
55 | OMAP_MCBSP_WORD_24, | |
56 | OMAP_MCBSP_WORD_32, | |
57 | }; | |
58 | ||
2e74796a JN |
59 | /* |
60 | * Stream DMA parameters. DMA request line and port address are set runtime | |
61 | * since they are different between OMAP1 and later OMAPs | |
62 | */ | |
caebc0cb EV |
63 | static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream) |
64 | { | |
65 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 66 | struct snd_soc_dai *cpu_dai = rtd->cpu_dai; |
45656b44 PU |
67 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
68 | struct omap_mcbsp_data *mcbsp_data = &mcbsp->mcbsp_data; | |
cf80e158 | 69 | struct omap_pcm_dma_data *dma_data; |
3f024039 | 70 | int words; |
a0a499c5 | 71 | |
f0fba2ad | 72 | dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream); |
cf80e158 | 73 | |
a0a499c5 | 74 | /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */ |
cb40b63a | 75 | if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) |
cf80e158 PU |
76 | /* |
77 | * Configure McBSP threshold based on either: | |
78 | * packet_size, when the sDMA is in packet mode, or | |
79 | * based on the period size. | |
80 | */ | |
81 | if (dma_data->packet_size) | |
82 | words = dma_data->packet_size; | |
83 | else | |
84 | words = snd_pcm_lib_period_bytes(substream) / | |
3f024039 | 85 | (mcbsp_data->wlen / 8); |
a0a499c5 | 86 | else |
3f024039 | 87 | words = 1; |
caebc0cb EV |
88 | |
89 | /* Configure McBSP internal buffer usage */ | |
90 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
45656b44 | 91 | omap_mcbsp_set_tx_threshold(mcbsp, words); |
caebc0cb | 92 | else |
45656b44 | 93 | omap_mcbsp_set_rx_threshold(mcbsp, words); |
caebc0cb EV |
94 | } |
95 | ||
ddc29b01 PU |
96 | static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params, |
97 | struct snd_pcm_hw_rule *rule) | |
98 | { | |
99 | struct snd_interval *buffer_size = hw_param_interval(params, | |
100 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE); | |
101 | struct snd_interval *channels = hw_param_interval(params, | |
102 | SNDRV_PCM_HW_PARAM_CHANNELS); | |
45656b44 | 103 | struct omap_mcbsp *mcbsp = rule->private; |
ddc29b01 PU |
104 | struct snd_interval frames; |
105 | int size; | |
106 | ||
107 | snd_interval_any(&frames); | |
cb40b63a | 108 | size = mcbsp->pdata->buffer_size; |
ddc29b01 PU |
109 | |
110 | frames.min = size / channels->min; | |
111 | frames.integer = 1; | |
112 | return snd_interval_refine(buffer_size, &frames); | |
113 | } | |
114 | ||
dee89c4d | 115 | static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream, |
f0fba2ad | 116 | struct snd_soc_dai *cpu_dai) |
2e74796a | 117 | { |
45656b44 | 118 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
2e74796a JN |
119 | int err = 0; |
120 | ||
caebc0cb | 121 | if (!cpu_dai->active) |
45656b44 | 122 | err = omap_mcbsp_request(mcbsp); |
caebc0cb | 123 | |
ddc29b01 PU |
124 | /* |
125 | * OMAP3 McBSP FIFO is word structured. | |
126 | * McBSP2 has 1024 + 256 = 1280 word long buffer, | |
127 | * McBSP1,3,4,5 has 128 word long buffer | |
128 | * This means that the size of the FIFO depends on the sample format. | |
129 | * For example on McBSP3: | |
130 | * 16bit samples: size is 128 * 2 = 256 bytes | |
131 | * 32bit samples: size is 128 * 4 = 512 bytes | |
132 | * It is simpler to place constraint for buffer and period based on | |
133 | * channels. | |
134 | * McBSP3 as example again (16 or 32 bit samples): | |
135 | * 1 channel (mono): size is 128 frames (128 words) | |
136 | * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words) | |
137 | * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words) | |
138 | */ | |
45656b44 | 139 | if (mcbsp->pdata->buffer_size) { |
6984992b | 140 | /* |
998a8a69 | 141 | * Rule for the buffer size. We should not allow |
ddc29b01 PU |
142 | * smaller buffer than the FIFO size to avoid underruns |
143 | */ | |
144 | snd_pcm_hw_rule_add(substream->runtime, 0, | |
145 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
146 | omap_mcbsp_hwrule_min_buffersize, | |
45656b44 | 147 | mcbsp, |
ddc29b01 | 148 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE, -1); |
caebc0cb | 149 | |
998a8a69 PU |
150 | /* Make sure, that the period size is always even */ |
151 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
152 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); | |
6984992b JN |
153 | } |
154 | ||
2e74796a JN |
155 | return err; |
156 | } | |
157 | ||
dee89c4d | 158 | static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream, |
f0fba2ad | 159 | struct snd_soc_dai *cpu_dai) |
2e74796a | 160 | { |
45656b44 PU |
161 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
162 | struct omap_mcbsp_data *mcbsp_data = &mcbsp->mcbsp_data; | |
2e74796a JN |
163 | |
164 | if (!cpu_dai->active) { | |
45656b44 | 165 | omap_mcbsp_free(mcbsp); |
2e74796a JN |
166 | mcbsp_data->configured = 0; |
167 | } | |
168 | } | |
169 | ||
dee89c4d | 170 | static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd, |
f0fba2ad | 171 | struct snd_soc_dai *cpu_dai) |
2e74796a | 172 | { |
45656b44 PU |
173 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
174 | struct omap_mcbsp_data *mcbsp_data = &mcbsp->mcbsp_data; | |
c12abc01 | 175 | int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
2e74796a JN |
176 | |
177 | switch (cmd) { | |
178 | case SNDRV_PCM_TRIGGER_START: | |
179 | case SNDRV_PCM_TRIGGER_RESUME: | |
180 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
c12abc01 | 181 | mcbsp_data->active++; |
45656b44 | 182 | omap_mcbsp_start(mcbsp, play, !play); |
2e74796a JN |
183 | break; |
184 | ||
185 | case SNDRV_PCM_TRIGGER_STOP: | |
186 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
187 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
45656b44 | 188 | omap_mcbsp_stop(mcbsp, play, !play); |
c12abc01 | 189 | mcbsp_data->active--; |
2e74796a JN |
190 | break; |
191 | default: | |
192 | err = -EINVAL; | |
193 | } | |
194 | ||
195 | return err; | |
196 | } | |
197 | ||
75581d24 PU |
198 | static snd_pcm_sframes_t omap_mcbsp_dai_delay( |
199 | struct snd_pcm_substream *substream, | |
200 | struct snd_soc_dai *dai) | |
201 | { | |
202 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 203 | struct snd_soc_dai *cpu_dai = rtd->cpu_dai; |
45656b44 | 204 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
75581d24 PU |
205 | u16 fifo_use; |
206 | snd_pcm_sframes_t delay; | |
207 | ||
208 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
45656b44 | 209 | fifo_use = omap_mcbsp_get_tx_delay(mcbsp); |
75581d24 | 210 | else |
45656b44 | 211 | fifo_use = omap_mcbsp_get_rx_delay(mcbsp); |
75581d24 PU |
212 | |
213 | /* | |
214 | * Divide the used locations with the channel count to get the | |
215 | * FIFO usage in samples (don't care about partial samples in the | |
216 | * buffer). | |
217 | */ | |
218 | delay = fifo_use / substream->runtime->channels; | |
219 | ||
220 | return delay; | |
221 | } | |
222 | ||
2e74796a | 223 | static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, |
dee89c4d | 224 | struct snd_pcm_hw_params *params, |
f0fba2ad | 225 | struct snd_soc_dai *cpu_dai) |
2e74796a | 226 | { |
45656b44 PU |
227 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
228 | struct omap_mcbsp_data *mcbsp_data = &mcbsp->mcbsp_data; | |
2e74796a | 229 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; |
81ec027e | 230 | struct omap_pcm_dma_data *dma_data; |
45656b44 | 231 | int dma; |
caebc0cb | 232 | int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT; |
cf80e158 | 233 | int pkt_size = 0; |
2e74796a | 234 | unsigned long port; |
5f63ef99 | 235 | unsigned int format, div, framesize, master; |
2e74796a | 236 | |
45656b44 | 237 | dma_data = &mcbsp_data->dma_data[substream->stream]; |
2686e07b | 238 | |
45656b44 PU |
239 | dma = omap_mcbsp_dma_ch_params(mcbsp, substream->stream); |
240 | port = omap_mcbsp_dma_reg_params(mcbsp, substream->stream); | |
2686e07b | 241 | |
d98508a1 SL |
242 | switch (params_format(params)) { |
243 | case SNDRV_PCM_FORMAT_S16_LE: | |
81ec027e | 244 | dma_data->data_type = OMAP_DMA_DATA_TYPE_S16; |
cf80e158 | 245 | wlen = 16; |
d98508a1 SL |
246 | break; |
247 | case SNDRV_PCM_FORMAT_S32_LE: | |
81ec027e | 248 | dma_data->data_type = OMAP_DMA_DATA_TYPE_S32; |
cf80e158 | 249 | wlen = 32; |
d98508a1 SL |
250 | break; |
251 | default: | |
252 | return -EINVAL; | |
253 | } | |
45656b44 | 254 | if (mcbsp->pdata->buffer_size) { |
15d01430 PU |
255 | dma_data->set_threshold = omap_mcbsp_set_threshold; |
256 | /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */ | |
cb40b63a | 257 | if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) { |
cf80e158 PU |
258 | int period_words, max_thrsh; |
259 | ||
260 | period_words = params_period_bytes(params) / (wlen / 8); | |
261 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
cb40b63a | 262 | max_thrsh = mcbsp->max_tx_thres; |
cf80e158 | 263 | else |
cb40b63a | 264 | max_thrsh = mcbsp->max_rx_thres; |
cf80e158 PU |
265 | /* |
266 | * If the period contains less or equal number of words, | |
267 | * we are using the original threshold mode setup: | |
268 | * McBSP threshold = sDMA frame size = period_size | |
269 | * Otherwise we switch to sDMA packet mode: | |
270 | * McBSP threshold = sDMA packet size | |
271 | * sDMA frame size = period size | |
272 | */ | |
273 | if (period_words > max_thrsh) { | |
274 | int divider = 0; | |
275 | ||
276 | /* | |
277 | * Look for the biggest threshold value, which | |
278 | * divides the period size evenly. | |
279 | */ | |
280 | divider = period_words / max_thrsh; | |
281 | if (period_words % max_thrsh) | |
282 | divider++; | |
283 | while (period_words % divider && | |
284 | divider < period_words) | |
285 | divider++; | |
286 | if (divider == period_words) | |
287 | return -EINVAL; | |
288 | ||
289 | pkt_size = period_words / divider; | |
290 | sync_mode = OMAP_DMA_SYNC_PACKET; | |
291 | } else { | |
292 | sync_mode = OMAP_DMA_SYNC_FRAME; | |
293 | } | |
294 | } | |
15d01430 PU |
295 | } |
296 | ||
297 | dma_data->name = substream->stream ? "Audio Capture" : "Audio Playback"; | |
298 | dma_data->dma_req = dma; | |
299 | dma_data->port_addr = port; | |
300 | dma_data->sync_mode = sync_mode; | |
cf80e158 | 301 | dma_data->packet_size = pkt_size; |
fd23b7de | 302 | |
81ec027e | 303 | snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data); |
2e74796a JN |
304 | |
305 | if (mcbsp_data->configured) { | |
306 | /* McBSP already configured by another stream */ | |
307 | return 0; | |
308 | } | |
309 | ||
4dd04172 JN |
310 | regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7)); |
311 | regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7)); | |
312 | regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7)); | |
313 | regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7)); | |
c29b206f PU |
314 | format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK; |
315 | wpf = channels = params_channels(params); | |
299a151f PU |
316 | if (channels == 2 && (format == SND_SOC_DAIFMT_I2S || |
317 | format == SND_SOC_DAIFMT_LEFT_J)) { | |
5f63ef99 GG |
318 | /* Use dual-phase frames */ |
319 | regs->rcr2 |= RPHASE; | |
320 | regs->xcr2 |= XPHASE; | |
321 | /* Set 1 word per (McBSP) frame for phase1 and phase2 */ | |
322 | wpf--; | |
323 | regs->rcr2 |= RFRLEN2(wpf - 1); | |
324 | regs->xcr2 |= XFRLEN2(wpf - 1); | |
2e74796a JN |
325 | } |
326 | ||
5f63ef99 GG |
327 | regs->rcr1 |= RFRLEN1(wpf - 1); |
328 | regs->xcr1 |= XFRLEN1(wpf - 1); | |
329 | ||
2e74796a JN |
330 | switch (params_format(params)) { |
331 | case SNDRV_PCM_FORMAT_S16_LE: | |
332 | /* Set word lengths */ | |
333 | regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16); | |
334 | regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16); | |
335 | regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16); | |
336 | regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16); | |
2e74796a | 337 | break; |
d98508a1 SL |
338 | case SNDRV_PCM_FORMAT_S32_LE: |
339 | /* Set word lengths */ | |
d98508a1 SL |
340 | regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32); |
341 | regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32); | |
342 | regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32); | |
343 | regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32); | |
344 | break; | |
2e74796a JN |
345 | default: |
346 | /* Unsupported PCM format */ | |
347 | return -EINVAL; | |
348 | } | |
349 | ||
5f63ef99 GG |
350 | /* In McBSP master modes, FRAME (i.e. sample rate) is generated |
351 | * by _counting_ BCLKs. Calculate frame size in BCLKs */ | |
352 | master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK; | |
353 | if (master == SND_SOC_DAIFMT_CBS_CFS) { | |
354 | div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1; | |
355 | framesize = (mcbsp_data->in_freq / div) / params_rate(params); | |
356 | ||
357 | if (framesize < wlen * channels) { | |
358 | printk(KERN_ERR "%s: not enough bandwidth for desired rate and " | |
359 | "channels\n", __func__); | |
360 | return -EINVAL; | |
361 | } | |
362 | } else | |
363 | framesize = wlen * channels; | |
364 | ||
ba9d0fd0 | 365 | /* Set FS period and length in terms of bit clock periods */ |
4dd04172 JN |
366 | regs->srgr2 &= ~FPER(0xfff); |
367 | regs->srgr1 &= ~FWID(0xff); | |
c29b206f | 368 | switch (format) { |
ba9d0fd0 | 369 | case SND_SOC_DAIFMT_I2S: |
299a151f | 370 | case SND_SOC_DAIFMT_LEFT_J: |
5f63ef99 GG |
371 | regs->srgr2 |= FPER(framesize - 1); |
372 | regs->srgr1 |= FWID((framesize >> 1) - 1); | |
ba9d0fd0 | 373 | break; |
3ba191ce | 374 | case SND_SOC_DAIFMT_DSP_A: |
bd25867a | 375 | case SND_SOC_DAIFMT_DSP_B: |
5f63ef99 | 376 | regs->srgr2 |= FPER(framesize - 1); |
36ce8582 | 377 | regs->srgr1 |= FWID(0); |
ba9d0fd0 JN |
378 | break; |
379 | } | |
380 | ||
45656b44 | 381 | omap_mcbsp_config(mcbsp, &mcbsp_data->regs); |
3f024039 | 382 | mcbsp_data->wlen = wlen; |
2e74796a JN |
383 | mcbsp_data->configured = 1; |
384 | ||
385 | return 0; | |
386 | } | |
387 | ||
388 | /* | |
389 | * This must be called before _set_clkdiv and _set_sysclk since McBSP register | |
390 | * cache is initialized here | |
391 | */ | |
8687eb8b | 392 | static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
2e74796a JN |
393 | unsigned int fmt) |
394 | { | |
45656b44 PU |
395 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
396 | struct omap_mcbsp_data *mcbsp_data = &mcbsp->mcbsp_data; | |
2e74796a | 397 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; |
91a18ae8 | 398 | bool inv_fs = false; |
2e74796a JN |
399 | |
400 | if (mcbsp_data->configured) | |
401 | return 0; | |
402 | ||
ba9d0fd0 | 403 | mcbsp_data->fmt = fmt; |
2e74796a JN |
404 | memset(regs, 0, sizeof(*regs)); |
405 | /* Generic McBSP register settings */ | |
406 | regs->spcr2 |= XINTM(3) | FREE; | |
407 | regs->spcr1 |= RINTM(3); | |
c721bbda | 408 | /* RFIG and XFIG are not defined in 34xx */ |
d4686c65 | 409 | if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) { |
c721bbda EN |
410 | regs->rcr2 |= RFIG; |
411 | regs->xcr2 |= XFIG; | |
412 | } | |
d4686c65 | 413 | if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
32080af7 JN |
414 | regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE; |
415 | regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE; | |
ef390c0b | 416 | } |
2e74796a JN |
417 | |
418 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
419 | case SND_SOC_DAIFMT_I2S: | |
420 | /* 1-bit data delay */ | |
421 | regs->rcr2 |= RDATDLY(1); | |
422 | regs->xcr2 |= XDATDLY(1); | |
423 | break; | |
299a151f PU |
424 | case SND_SOC_DAIFMT_LEFT_J: |
425 | /* 0-bit data delay */ | |
426 | regs->rcr2 |= RDATDLY(0); | |
427 | regs->xcr2 |= XDATDLY(0); | |
428 | regs->spcr1 |= RJUST(2); | |
429 | /* Invert FS polarity configuration */ | |
91a18ae8 | 430 | inv_fs = true; |
299a151f | 431 | break; |
3ba191ce PU |
432 | case SND_SOC_DAIFMT_DSP_A: |
433 | /* 1-bit data delay */ | |
434 | regs->rcr2 |= RDATDLY(1); | |
435 | regs->xcr2 |= XDATDLY(1); | |
436 | /* Invert FS polarity configuration */ | |
91a18ae8 | 437 | inv_fs = true; |
3ba191ce | 438 | break; |
bd25867a | 439 | case SND_SOC_DAIFMT_DSP_B: |
3336c5b5 AK |
440 | /* 0-bit data delay */ |
441 | regs->rcr2 |= RDATDLY(0); | |
442 | regs->xcr2 |= XDATDLY(0); | |
36ce8582 | 443 | /* Invert FS polarity configuration */ |
91a18ae8 | 444 | inv_fs = true; |
3336c5b5 | 445 | break; |
2e74796a JN |
446 | default: |
447 | /* Unsupported data format */ | |
448 | return -EINVAL; | |
449 | } | |
450 | ||
451 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
452 | case SND_SOC_DAIFMT_CBS_CFS: | |
453 | /* McBSP master. Set FS and bit clocks as outputs */ | |
454 | regs->pcr0 |= FSXM | FSRM | | |
455 | CLKXM | CLKRM; | |
456 | /* Sample rate generator drives the FS */ | |
457 | regs->srgr2 |= FSGM; | |
458 | break; | |
459 | case SND_SOC_DAIFMT_CBM_CFM: | |
460 | /* McBSP slave */ | |
461 | break; | |
462 | default: | |
463 | /* Unsupported master/slave configuration */ | |
464 | return -EINVAL; | |
465 | } | |
466 | ||
467 | /* Set bit clock (CLKX/CLKR) and FS polarities */ | |
91a18ae8 | 468 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
2e74796a JN |
469 | case SND_SOC_DAIFMT_NB_NF: |
470 | /* | |
471 | * Normal BCLK + FS. | |
472 | * FS active low. TX data driven on falling edge of bit clock | |
473 | * and RX data sampled on rising edge of bit clock. | |
474 | */ | |
475 | regs->pcr0 |= FSXP | FSRP | | |
476 | CLKXP | CLKRP; | |
477 | break; | |
478 | case SND_SOC_DAIFMT_NB_IF: | |
479 | regs->pcr0 |= CLKXP | CLKRP; | |
480 | break; | |
481 | case SND_SOC_DAIFMT_IB_NF: | |
482 | regs->pcr0 |= FSXP | FSRP; | |
483 | break; | |
484 | case SND_SOC_DAIFMT_IB_IF: | |
485 | break; | |
486 | default: | |
487 | return -EINVAL; | |
488 | } | |
91a18ae8 JN |
489 | if (inv_fs == true) |
490 | regs->pcr0 ^= FSXP | FSRP; | |
2e74796a JN |
491 | |
492 | return 0; | |
493 | } | |
494 | ||
8687eb8b | 495 | static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, |
2e74796a JN |
496 | int div_id, int div) |
497 | { | |
45656b44 PU |
498 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
499 | struct omap_mcbsp_data *mcbsp_data = &mcbsp->mcbsp_data; | |
2e74796a JN |
500 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; |
501 | ||
502 | if (div_id != OMAP_MCBSP_CLKGDV) | |
503 | return -ENODEV; | |
504 | ||
5f63ef99 | 505 | mcbsp_data->clk_div = div; |
4dd04172 | 506 | regs->srgr1 &= ~CLKGDV(0xff); |
2e74796a JN |
507 | regs->srgr1 |= CLKGDV(div - 1); |
508 | ||
509 | return 0; | |
510 | } | |
511 | ||
8687eb8b | 512 | static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
2e74796a JN |
513 | int clk_id, unsigned int freq, |
514 | int dir) | |
515 | { | |
45656b44 PU |
516 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); |
517 | struct omap_mcbsp_data *mcbsp_data = &mcbsp->mcbsp_data; | |
2e74796a JN |
518 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; |
519 | int err = 0; | |
520 | ||
141947e6 | 521 | if (mcbsp_data->active) { |
34c86985 JN |
522 | if (freq == mcbsp_data->in_freq) |
523 | return 0; | |
524 | else | |
525 | return -EBUSY; | |
141947e6 | 526 | } |
34c86985 | 527 | |
cf4c87ab PW |
528 | /* The McBSP signal muxing functions are only available on McBSP1 */ |
529 | if (clk_id == OMAP_MCBSP_CLKR_SRC_CLKR || | |
530 | clk_id == OMAP_MCBSP_CLKR_SRC_CLKX || | |
531 | clk_id == OMAP_MCBSP_FSR_SRC_FSR || | |
532 | clk_id == OMAP_MCBSP_FSR_SRC_FSX) | |
45656b44 | 533 | if (cpu_class_is_omap1() || cpu_dai->id != 1) |
cf4c87ab PW |
534 | return -EINVAL; |
535 | ||
5f63ef99 | 536 | mcbsp_data->in_freq = freq; |
4dd04172 JN |
537 | regs->srgr2 &= ~CLKSM; |
538 | regs->pcr0 &= ~SCLKME; | |
5f63ef99 | 539 | |
2e74796a JN |
540 | switch (clk_id) { |
541 | case OMAP_MCBSP_SYSCLK_CLK: | |
542 | regs->srgr2 |= CLKSM; | |
543 | break; | |
544 | case OMAP_MCBSP_SYSCLK_CLKS_FCLK: | |
d1358657 PW |
545 | if (cpu_class_is_omap1()) { |
546 | err = -EINVAL; | |
547 | break; | |
548 | } | |
45656b44 | 549 | err = omap2_mcbsp_set_clks_src(mcbsp, |
d1358657 PW |
550 | MCBSP_CLKS_PRCM_SRC); |
551 | break; | |
2e74796a | 552 | case OMAP_MCBSP_SYSCLK_CLKS_EXT: |
d1358657 PW |
553 | if (cpu_class_is_omap1()) { |
554 | err = 0; | |
555 | break; | |
556 | } | |
45656b44 | 557 | err = omap2_mcbsp_set_clks_src(mcbsp, |
d1358657 | 558 | MCBSP_CLKS_PAD_SRC); |
2e74796a JN |
559 | break; |
560 | ||
561 | case OMAP_MCBSP_SYSCLK_CLKX_EXT: | |
562 | regs->srgr2 |= CLKSM; | |
563 | case OMAP_MCBSP_SYSCLK_CLKR_EXT: | |
564 | regs->pcr0 |= SCLKME; | |
565 | break; | |
d2c0bdaa | 566 | |
cf4c87ab | 567 | |
d2c0bdaa | 568 | case OMAP_MCBSP_CLKR_SRC_CLKR: |
23353850 JK |
569 | if (cpu_class_is_omap1()) |
570 | break; | |
45656b44 | 571 | omap2_mcbsp1_mux_clkr_src(mcbsp, CLKR_SRC_CLKR); |
cf4c87ab | 572 | break; |
d2c0bdaa | 573 | case OMAP_MCBSP_CLKR_SRC_CLKX: |
23353850 JK |
574 | if (cpu_class_is_omap1()) |
575 | break; | |
45656b44 | 576 | omap2_mcbsp1_mux_clkr_src(mcbsp, CLKR_SRC_CLKX); |
cf4c87ab | 577 | break; |
d2c0bdaa | 578 | case OMAP_MCBSP_FSR_SRC_FSR: |
23353850 JK |
579 | if (cpu_class_is_omap1()) |
580 | break; | |
45656b44 | 581 | omap2_mcbsp1_mux_fsr_src(mcbsp, FSR_SRC_FSR); |
cf4c87ab | 582 | break; |
d2c0bdaa | 583 | case OMAP_MCBSP_FSR_SRC_FSX: |
23353850 JK |
584 | if (cpu_class_is_omap1()) |
585 | break; | |
45656b44 | 586 | omap2_mcbsp1_mux_fsr_src(mcbsp, FSR_SRC_FSX); |
d2c0bdaa | 587 | break; |
2e74796a JN |
588 | default: |
589 | err = -ENODEV; | |
590 | } | |
591 | ||
592 | return err; | |
593 | } | |
594 | ||
85e7652d | 595 | static const struct snd_soc_dai_ops mcbsp_dai_ops = { |
6335d055 EM |
596 | .startup = omap_mcbsp_dai_startup, |
597 | .shutdown = omap_mcbsp_dai_shutdown, | |
598 | .trigger = omap_mcbsp_dai_trigger, | |
75581d24 | 599 | .delay = omap_mcbsp_dai_delay, |
6335d055 EM |
600 | .hw_params = omap_mcbsp_dai_hw_params, |
601 | .set_fmt = omap_mcbsp_dai_set_dai_fmt, | |
602 | .set_clkdiv = omap_mcbsp_dai_set_clkdiv, | |
603 | .set_sysclk = omap_mcbsp_dai_set_dai_sysclk, | |
604 | }; | |
605 | ||
6179b772 | 606 | static struct snd_soc_dai_driver omap_mcbsp_dai = { |
f0fba2ad LG |
607 | .playback = { |
608 | .channels_min = 1, | |
609 | .channels_max = 16, | |
610 | .rates = OMAP_MCBSP_RATES, | |
611 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, | |
612 | }, | |
613 | .capture = { | |
614 | .channels_min = 1, | |
615 | .channels_max = 16, | |
616 | .rates = OMAP_MCBSP_RATES, | |
617 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, | |
618 | }, | |
619 | .ops = &mcbsp_dai_ops, | |
2e74796a | 620 | }; |
8def464d | 621 | |
3484457f | 622 | static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol, |
83905c13 IK |
623 | struct snd_ctl_elem_info *uinfo) |
624 | { | |
625 | struct soc_mixer_control *mc = | |
626 | (struct soc_mixer_control *)kcontrol->private_value; | |
627 | int max = mc->max; | |
628 | int min = mc->min; | |
629 | ||
630 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
631 | uinfo->count = 1; | |
632 | uinfo->value.integer.min = min; | |
633 | uinfo->value.integer.max = max; | |
634 | return 0; | |
635 | } | |
636 | ||
45656b44 | 637 | #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(channel) \ |
83905c13 | 638 | static int \ |
45656b44 | 639 | omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \ |
83905c13 IK |
640 | struct snd_ctl_elem_value *uc) \ |
641 | { \ | |
45656b44 PU |
642 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \ |
643 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \ | |
83905c13 IK |
644 | struct soc_mixer_control *mc = \ |
645 | (struct soc_mixer_control *)kc->private_value; \ | |
646 | int max = mc->max; \ | |
647 | int min = mc->min; \ | |
648 | int val = uc->value.integer.value[0]; \ | |
649 | \ | |
650 | if (val < min || val > max) \ | |
651 | return -EINVAL; \ | |
652 | \ | |
653 | /* OMAP McBSP implementation uses index values 0..4 */ \ | |
45656b44 | 654 | return omap_st_set_chgain(mcbsp, channel, val); \ |
83905c13 IK |
655 | } |
656 | ||
45656b44 | 657 | #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(channel) \ |
83905c13 | 658 | static int \ |
45656b44 | 659 | omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \ |
83905c13 IK |
660 | struct snd_ctl_elem_value *uc) \ |
661 | { \ | |
45656b44 PU |
662 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \ |
663 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \ | |
83905c13 IK |
664 | s16 chgain; \ |
665 | \ | |
45656b44 | 666 | if (omap_st_get_chgain(mcbsp, channel, &chgain)) \ |
83905c13 IK |
667 | return -EAGAIN; \ |
668 | \ | |
669 | uc->value.integer.value[0] = chgain; \ | |
670 | return 0; \ | |
671 | } | |
672 | ||
45656b44 PU |
673 | OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(0) |
674 | OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(1) | |
675 | OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(0) | |
676 | OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(1) | |
83905c13 IK |
677 | |
678 | static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol, | |
679 | struct snd_ctl_elem_value *ucontrol) | |
680 | { | |
45656b44 PU |
681 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); |
682 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); | |
83905c13 IK |
683 | u8 value = ucontrol->value.integer.value[0]; |
684 | ||
45656b44 | 685 | if (value == omap_st_is_enabled(mcbsp)) |
83905c13 IK |
686 | return 0; |
687 | ||
688 | if (value) | |
45656b44 | 689 | omap_st_enable(mcbsp); |
83905c13 | 690 | else |
45656b44 | 691 | omap_st_disable(mcbsp); |
83905c13 IK |
692 | |
693 | return 1; | |
694 | } | |
695 | ||
696 | static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol, | |
697 | struct snd_ctl_elem_value *ucontrol) | |
698 | { | |
45656b44 PU |
699 | struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); |
700 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); | |
83905c13 | 701 | |
45656b44 | 702 | ucontrol->value.integer.value[0] = omap_st_is_enabled(mcbsp); |
83905c13 IK |
703 | return 0; |
704 | } | |
705 | ||
706 | static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = { | |
707 | SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0, | |
708 | omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode), | |
709 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume", | |
710 | -32768, 32767, | |
45656b44 PU |
711 | omap_mcbsp_get_st_ch0_volume, |
712 | omap_mcbsp_set_st_ch0_volume), | |
83905c13 IK |
713 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume", |
714 | -32768, 32767, | |
45656b44 PU |
715 | omap_mcbsp_get_st_ch1_volume, |
716 | omap_mcbsp_set_st_ch1_volume), | |
83905c13 IK |
717 | }; |
718 | ||
719 | static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = { | |
720 | SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0, | |
721 | omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode), | |
722 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume", | |
723 | -32768, 32767, | |
45656b44 PU |
724 | omap_mcbsp_get_st_ch0_volume, |
725 | omap_mcbsp_set_st_ch0_volume), | |
83905c13 IK |
726 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume", |
727 | -32768, 32767, | |
45656b44 PU |
728 | omap_mcbsp_get_st_ch1_volume, |
729 | omap_mcbsp_set_st_ch1_volume), | |
83905c13 IK |
730 | }; |
731 | ||
45656b44 | 732 | int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd) |
83905c13 | 733 | { |
45656b44 PU |
734 | struct snd_soc_dai *cpu_dai = rtd->cpu_dai; |
735 | struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); | |
736 | ||
737 | if (!mcbsp->st_data) | |
83905c13 IK |
738 | return -ENODEV; |
739 | ||
45656b44 PU |
740 | switch (cpu_dai->id) { |
741 | case 2: /* McBSP 2 */ | |
742 | return snd_soc_add_dai_controls(cpu_dai, | |
743 | omap_mcbsp2_st_controls, | |
83905c13 | 744 | ARRAY_SIZE(omap_mcbsp2_st_controls)); |
45656b44 PU |
745 | case 3: /* McBSP 3 */ |
746 | return snd_soc_add_dai_controls(cpu_dai, | |
747 | omap_mcbsp3_st_controls, | |
83905c13 IK |
748 | ARRAY_SIZE(omap_mcbsp3_st_controls)); |
749 | default: | |
750 | break; | |
751 | } | |
752 | ||
753 | return -EINVAL; | |
754 | } | |
755 | EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls); | |
756 | ||
f0fba2ad LG |
757 | static __devinit int asoc_mcbsp_probe(struct platform_device *pdev) |
758 | { | |
45656b44 PU |
759 | int ret; |
760 | ||
761 | ret = omap_mcbsp_probe(pdev); | |
762 | if (!ret) | |
763 | return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai); | |
764 | ||
765 | return ret; | |
f0fba2ad LG |
766 | } |
767 | ||
768 | static int __devexit asoc_mcbsp_remove(struct platform_device *pdev) | |
769 | { | |
45656b44 | 770 | omap_mcbsp_remove(pdev); |
f0fba2ad LG |
771 | snd_soc_unregister_dai(&pdev->dev); |
772 | return 0; | |
773 | } | |
774 | ||
775 | static struct platform_driver asoc_mcbsp_driver = { | |
776 | .driver = { | |
45656b44 | 777 | .name = "omap-mcbsp", |
f0fba2ad LG |
778 | .owner = THIS_MODULE, |
779 | }, | |
780 | ||
781 | .probe = asoc_mcbsp_probe, | |
782 | .remove = __devexit_p(asoc_mcbsp_remove), | |
783 | }; | |
784 | ||
beda5bf5 | 785 | module_platform_driver(asoc_mcbsp_driver); |
3f4b783c | 786 | |
7ec41ee5 | 787 | MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>"); |
2e74796a JN |
788 | MODULE_DESCRIPTION("OMAP I2S SoC Interface"); |
789 | MODULE_LICENSE("GPL"); |