[deliverable/linux.git] / sound / soc / omap / omap-mcpdm.c

/*
 * omap-mcpdm.c  --  OMAP ALSA SoC DAI driver using McPDM port
 *
 * Copyright (C) 2009 - 2011 Texas Instruments
 *
 * Author: Misael Lopez Cruz <misael.lopez@ti.com>
 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
 *          Margarita Olaya <magi.olaya@ti.com>
 *          Peter Ujfalusi <peter.ujfalusi@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/of_device.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>

#include "omap-mcpdm.h"

struct mcpdm_link_config {
	u32 link_mask; /* channel mask for the direction */
	u32 threshold; /* FIFO threshold */
};

struct omap_mcpdm {
	struct device *dev;
	unsigned long phys_base;
	void __iomem *io_base;
	int irq;

	struct mutex mutex;

	/* Playback/Capture configuration */
	struct mcpdm_link_config config[2];

	/* McPDM dn offsets for rx1, and 2 channels */
	u32 dn_rx_offset;

	/* McPDM needs to be restarted due to runtime reconfiguration */
	bool restart;

	struct snd_dmaengine_dai_dma_data dma_data[2];
};

/*
 * Stream DMA parameters
 */

static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
{
	writel_relaxed(val, mcpdm->io_base + reg);
}

static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
{
	return readl_relaxed(mcpdm->io_base + reg);
}

#ifdef DEBUG
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
{
	dev_dbg(mcpdm->dev, "***********************\n");
	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	dev_dbg(mcpdm->dev, "IRQSTATUS:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	dev_dbg(mcpdm->dev, "DMAWAKEEN:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	dev_dbg(mcpdm->dev, "CTRL:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	dev_dbg(mcpdm->dev, "***********************\n");
}
#else
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
#endif

/*
 * Enables the transfer through the PDM interface to/from the Phoenix
 * codec by enabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl |= link_mask;
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
}

/*
 * Disables the transfer through the PDM interface to/from the Phoenix
 * codec by disabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK;

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(link_mask);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

}

/*
 * Is the physical McPDM interface active.
 */
static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
{
	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
					(MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
}

/*
 * Configures McPDM uplink, and downlink for audio.
 * This function should be called before omap_mcpdm_start.
 */
static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
{
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Enable DN RX1/2 offset cancellation feature, if configured */
	if (mcpdm->dn_rx_offset) {
		u32 dn_offset = mcpdm->dn_rx_offset;

		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
		dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	}

	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
			 mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
			 mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);

	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
			MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
}

/*
 * Cleans McPDM uplink, and downlink configuration.
 * This function should be called when the stream is closed.
 */
static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
{
	/* Disable irq request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);

	/* Disable DMA request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);

	/* Disable irq request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Disable DMA request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);

	/* Disable RX1/2 offset cancellation */
	if (mcpdm->dn_rx_offset)
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
}

static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
{
	struct omap_mcpdm *mcpdm = dev_id;
	int irq_status;

	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);

	/* Acknowledge irq event */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);

	if (irq_status & MCPDM_DN_IRQ_FULL)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");

	if (irq_status & MCPDM_DN_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");

	if (irq_status & MCPDM_DN_IRQ)
		dev_dbg(mcpdm->dev, "DN (playback) write request\n");

	if (irq_status & MCPDM_UP_IRQ_FULL)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");

	if (irq_status & MCPDM_UP_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");

	if (irq_status & MCPDM_UP_IRQ)
		dev_dbg(mcpdm->dev, "UP (capture) write request\n");

	return IRQ_HANDLED;
}

static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

		omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
		omap_mcpdm_open_streams(mcpdm);
	}
	mutex_unlock(&mcpdm->mutex);

	snd_soc_dai_set_dma_data(dai, substream,
				 &mcpdm->dma_data[substream->stream]);

	return 0;
}

static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		if (omap_mcpdm_active(mcpdm)) {
			omap_mcpdm_stop(mcpdm);
			omap_mcpdm_close_streams(mcpdm);
			mcpdm->config[0].link_mask = 0;
			mcpdm->config[1].link_mask = 0;
		}
	}

	mutex_unlock(&mcpdm->mutex);
}

static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int stream = substream->stream;
	struct snd_dmaengine_dai_dma_data *dma_data;
	u32 threshold;
	int channels;
	int link_mask = 0;

	channels = params_channels(params);
	switch (channels) {
	case 5:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 4;
	case 4:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 3;
	case 3:
		link_mask |= 1 << 2;
	case 2:
		link_mask |= 1 << 1;
	case 1:
		link_mask |= 1 << 0;
		break;
	default:
		/* unsupported number of channels */
		return -EINVAL;
	}

	dma_data = snd_soc_dai_get_dma_data(dai, substream);

	threshold = mcpdm->config[stream].threshold;
	/* Configure McPDM channels, and DMA packet size */
	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		link_mask <<= 3;

		/* If capture is not running assume a stereo stream to come */
		if (!mcpdm->config[!stream].link_mask)
			mcpdm->config[!stream].link_mask = 0x3;

		dma_data->maxburst =
				(MCPDM_DN_THRES_MAX - threshold) * channels;
	} else {
		/* If playback is not running assume a stereo stream to come */
		if (!mcpdm->config[!stream].link_mask)
			mcpdm->config[!stream].link_mask = (0x3 << 3);

		dma_data->maxburst = threshold * channels;
	}

	/* Check if we need to restart McPDM with this stream */
	if (mcpdm->config[stream].link_mask &&
	    mcpdm->config[stream].link_mask != link_mask)
		mcpdm->restart = true;

	mcpdm->config[stream].link_mask = link_mask;

	return 0;
}

static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	if (!omap_mcpdm_active(mcpdm)) {
		omap_mcpdm_start(mcpdm);
		omap_mcpdm_reg_dump(mcpdm);
	} else if (mcpdm->restart) {
		omap_mcpdm_stop(mcpdm);
		omap_mcpdm_start(mcpdm);
		mcpdm->restart = false;
		omap_mcpdm_reg_dump(mcpdm);
	}

	return 0;
}

static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
	.startup	= omap_mcpdm_dai_startup,
	.shutdown	= omap_mcpdm_dai_shutdown,
	.hw_params	= omap_mcpdm_dai_hw_params,
	.prepare	= omap_mcpdm_prepare,
};

static int omap_mcpdm_probe(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int ret;

	pm_runtime_enable(mcpdm->dev);

	/* Disable lines while request is ongoing */
	pm_runtime_get_sync(mcpdm->dev);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);

	ret = devm_request_irq(mcpdm->dev, mcpdm->irq, omap_mcpdm_irq_handler,
				0, "McPDM", (void *)mcpdm);

	pm_runtime_put_sync(mcpdm->dev);

	if (ret) {
		dev_err(mcpdm->dev, "Request for IRQ failed\n");
		pm_runtime_disable(mcpdm->dev);
	}

	/* Configure McPDM threshold values */
	mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
	mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
							MCPDM_UP_THRES_MAX - 3;
	return ret;
}

static int omap_mcpdm_remove(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	pm_runtime_disable(mcpdm->dev);

	return 0;
}

#define OMAP_MCPDM_RATES	(SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define OMAP_MCPDM_FORMATS	SNDRV_PCM_FMTBIT_S32_LE

static struct snd_soc_dai_driver omap_mcpdm_dai = {
	.probe = omap_mcpdm_probe,
	.remove = omap_mcpdm_remove,
	.probe_order = SND_SOC_COMP_ORDER_LATE,
	.remove_order = SND_SOC_COMP_ORDER_EARLY,
	.playback = {
		.channels_min = 1,
		.channels_max = 5,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.capture = {
		.channels_min = 1,
		.channels_max = 3,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.ops = &omap_mcpdm_dai_ops,
};

static const struct snd_soc_component_driver omap_mcpdm_component = {
	.name		= "omap-mcpdm",
};

void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
				    u8 rx1, u8 rx2)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);

	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
}
EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);

static int asoc_mcpdm_probe(struct platform_device *pdev)
{
	struct omap_mcpdm *mcpdm;
	struct resource *res;

	mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
	if (!mcpdm)
		return -ENOMEM;

	platform_set_drvdata(pdev, mcpdm);

	mutex_init(&mcpdm->mutex);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	if (res == NULL)
		return -ENOMEM;

	mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
	mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;

	mcpdm->dma_data[0].filter_data = "dn_link";
	mcpdm->dma_data[1].filter_data = "up_link";

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
	mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mcpdm->io_base))
		return PTR_ERR(mcpdm->io_base);

	mcpdm->irq = platform_get_irq(pdev, 0);
	if (mcpdm->irq < 0)
		return mcpdm->irq;

	mcpdm->dev = &pdev->dev;

	return devm_snd_soc_register_component(&pdev->dev,
					       &omap_mcpdm_component,
					       &omap_mcpdm_dai, 1);
}

static const struct of_device_id omap_mcpdm_of_match[] = {
	{ .compatible = "ti,omap4-mcpdm", },
	{ }
};
MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);

static struct platform_driver asoc_mcpdm_driver = {
	.driver = {
		.name	= "omap-mcpdm",
		.owner	= THIS_MODULE,
		.of_match_table = omap_mcpdm_of_match,
	},

	.probe	= asoc_mcpdm_probe,
};

module_platform_driver(asoc_mcpdm_driver);

MODULE_ALIAS("platform:omap-mcpdm");
MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
MODULE_DESCRIPTION("OMAP PDM SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
db72c2f8 MLC	1	/*
	2	* omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
	3	*
f5f9d7bf	4	* Copyright (C) 2009 - 2011 Texas Instruments
db72c2f8	5	*
f5f9d7bf	6	* Author: Misael Lopez Cruz <misael.lopez@ti.com>
db72c2f8 MLC	7	* Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
db72c2f8 MLC	8	* Margarita Olaya <magi.olaya@ti.com>
f5f9d7bf	9	* Peter Ujfalusi <peter.ujfalusi@ti.com>
db72c2f8 MLC	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License
	13	* version 2 as published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful, but
	16	* WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	23	* 02110-1301 USA
	24	*
	25	*/
	26
	27	#include <linux/init.h>
	28	#include <linux/module.h>
f5f9d7bf MLC	29	#include <linux/platform_device.h>
	30	#include <linux/interrupt.h>
	31	#include <linux/err.h>
	32	#include <linux/io.h>
	33	#include <linux/irq.h>
	34	#include <linux/slab.h>
	35	#include <linux/pm_runtime.h>
7cb8a1b5	36	#include <linux/of_device.h>
f5f9d7bf	37
db72c2f8 MLC	38	#include <sound/core.h>
	39	#include <sound/pcm.h>
	40	#include <sound/pcm_params.h>
db72c2f8	41	#include <sound/soc.h>
09ae3aaf	42	#include <sound/dmaengine_pcm.h>
db72c2f8	43
f5f9d7bf	44	#include "omap-mcpdm.h"
db72c2f8	45
62376631 PU	46	struct mcpdm_link_config {
	47	u32 link_mask; /* channel mask for the direction */
	48	u32 threshold; /* FIFO threshold */
	49	};
dbc04161	50
f5f9d7bf MLC	51	struct omap_mcpdm {
	52	struct device *dev;
	53	unsigned long phys_base;
	54	void __iomem *io_base;
	55	int irq;
db72c2f8	56
f5f9d7bf MLC	57	struct mutex mutex;
f5f9d7bf MLC	58
62376631 PU	59	/* Playback/Capture configuration */
62376631 PU	60	struct mcpdm_link_config config[2];
89b0d550 PU	61
	62	/* McPDM dn offsets for rx1, and 2 channels */
	63	u32 dn_rx_offset;
81054b22 PU	64
	65	/* McPDM needs to be restarted due to runtime reconfiguration */
	66	bool restart;
09ae3aaf LPC	67
09ae3aaf LPC	68	struct snd_dmaengine_dai_dma_data dma_data[2];
db72c2f8 MLC	69	};
	70
	71	/*
	72	* Stream DMA parameters
	73	*/
db72c2f8	74
f5f9d7bf	75	static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
db72c2f8	76	{
1b488a48	77	writel_relaxed(val, mcpdm->io_base + reg);
f5f9d7bf	78	}
db72c2f8	79
f5f9d7bf MLC	80	static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
f5f9d7bf MLC	81	{
1b488a48	82	return readl_relaxed(mcpdm->io_base + reg);
f5f9d7bf	83	}
db72c2f8	84
f5f9d7bf MLC	85	#ifdef DEBUG
	86	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
	87	{
	88	dev_dbg(mcpdm->dev, "***********************\n");
	89	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
	90	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	91	dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
	92	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	93	dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
	94	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	95	dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
	96	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	97	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
	98	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	99	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
	100	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	101	dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
	102	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	103	dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
	104	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	105	dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
	106	omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	107	dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
	108	omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	109	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
	110	omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	111	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
	112	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	113	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
	114	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	115	dev_dbg(mcpdm->dev, "***********************\n");
db72c2f8	116	}
f5f9d7bf MLC	117	#else
	118	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
	119	#endif
db72c2f8	120
f5f9d7bf MLC	121	/*
	122	* Enables the transfer through the PDM interface to/from the Phoenix
	123	* codec by enabling the corresponding UP or DN channels.
	124	*/
	125	static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
	126	{
	127	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
62376631	128	u32 link_mask = mcpdm->config[0].link_mask \| mcpdm->config[1].link_mask;
f5f9d7bf MLC	129
	130	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	131	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	132
62376631	133	ctrl \|= link_mask;
f5f9d7bf MLC	134	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	135
	136	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	137	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	138	}
	139
	140	/*
	141	* Disables the transfer through the PDM interface to/from the Phoenix
	142	* codec by disabling the corresponding UP or DN channels.
	143	*/
	144	static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
	145	{
	146	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
81054b22	147	u32 link_mask = MCPDM_PDM_DN_MASK \| MCPDM_PDM_UP_MASK;
f5f9d7bf MLC	148
	149	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	150	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	151
62376631	152	ctrl &= ~(link_mask);
f5f9d7bf MLC	153	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	154
	155	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	156	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	157
	158	}
	159
	160	/*
	161	* Is the physical McPDM interface active.
	162	*/
	163	static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
	164	{
	165	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
	166	(MCPDM_PDM_DN_MASK \| MCPDM_PDM_UP_MASK);
	167	}
	168
	169	/*
	170	* Configures McPDM uplink, and downlink for audio.
	171	* This function should be called before omap_mcpdm_start.
	172	*/
	173	static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
	174	{
	175	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
	176	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL \|
	177	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	178
89b0d550 PU	179	/* Enable DN RX1/2 offset cancellation feature, if configured */
	180	if (mcpdm->dn_rx_offset) {
	181	u32 dn_offset = mcpdm->dn_rx_offset;
	182
	183	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	184	dn_offset \|= (MCPDM_DN_OFST_RX1_EN \| MCPDM_DN_OFST_RX2_EN);
	185	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	186	}
	187
62376631 PU	188	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
	189	mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
	190	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
	191	mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);
f5f9d7bf MLC	192
	193	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
	194	MCPDM_DMA_DN_ENABLE \| MCPDM_DMA_UP_ENABLE);
	195	}
	196
	197	/*
	198	* Cleans McPDM uplink, and downlink configuration.
	199	* This function should be called when the stream is closed.
	200	*/
	201	static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
db72c2f8	202	{
f5f9d7bf MLC	203	/* Disable irq request generation for downlink */
	204	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	205	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL);
	206
	207	/* Disable DMA request generation for downlink */
	208	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
	209
	210	/* Disable irq request generation for uplink */
	211	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	212	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	213
	214	/* Disable DMA request generation for uplink */
	215	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
89b0d550 PU	216
	217	/* Disable RX1/2 offset cancellation */
	218	if (mcpdm->dn_rx_offset)
	219	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
f5f9d7bf MLC	220	}
	221
	222	static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
	223	{
	224	struct omap_mcpdm *mcpdm = dev_id;
	225	int irq_status;
	226
	227	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
	228
	229	/* Acknowledge irq event */
	230	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
	231
	232	if (irq_status & MCPDM_DN_IRQ_FULL)
	233	dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
	234
	235	if (irq_status & MCPDM_DN_IRQ_EMPTY)
	236	dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
	237
	238	if (irq_status & MCPDM_DN_IRQ)
	239	dev_dbg(mcpdm->dev, "DN (playback) write request\n");
	240
	241	if (irq_status & MCPDM_UP_IRQ_FULL)
	242	dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
	243
	244	if (irq_status & MCPDM_UP_IRQ_EMPTY)
	245	dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
	246
	247	if (irq_status & MCPDM_UP_IRQ)
	248	dev_dbg(mcpdm->dev, "UP (capture) write request\n");
	249
	250	return IRQ_HANDLED;
db72c2f8 MLC	251	}
db72c2f8 MLC	252
f5f9d7bf	253	static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
db72c2f8 MLC	254	struct snd_soc_dai *dai)
db72c2f8 MLC	255	{
f5f9d7bf	256	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	257
f5f9d7bf MLC	258	mutex_lock(&mcpdm->mutex);
	259
	260	if (!dai->active) {
68214d99	261	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
f5f9d7bf	262
68214d99	263	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl \| MCPDM_WD_EN);
f5f9d7bf	264	omap_mcpdm_open_streams(mcpdm);
db72c2f8	265	}
f5f9d7bf MLC	266	mutex_unlock(&mcpdm->mutex);
f5f9d7bf MLC	267
bcd6da7b	268	snd_soc_dai_set_dma_data(dai, substream,
09ae3aaf	269	&mcpdm->dma_data[substream->stream]);
bcd6da7b	270
f5f9d7bf MLC	271	return 0;
	272	}
	273
	274	static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
	275	struct snd_soc_dai *dai)
	276	{
	277	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	278
	279	mutex_lock(&mcpdm->mutex);
	280
	281	if (!dai->active) {
	282	if (omap_mcpdm_active(mcpdm)) {
	283	omap_mcpdm_stop(mcpdm);
	284	omap_mcpdm_close_streams(mcpdm);
81054b22 PU	285	mcpdm->config[0].link_mask = 0;
81054b22 PU	286	mcpdm->config[1].link_mask = 0;
f5f9d7bf	287	}
f5f9d7bf MLC	288	}
	289
	290	mutex_unlock(&mcpdm->mutex);
db72c2f8 MLC	291	}
	292
	293	static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
	294	struct snd_pcm_hw_params *params,
	295	struct snd_soc_dai *dai)
	296	{
f5f9d7bf	297	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	298	int stream = substream->stream;
09ae3aaf	299	struct snd_dmaengine_dai_dma_data *dma_data;
62376631	300	u32 threshold;
f5f9d7bf MLC	301	int channels;
f5f9d7bf MLC	302	int link_mask = 0;
db72c2f8	303
db72c2f8 MLC	304	channels = params_channels(params);
db72c2f8 MLC	305	switch (channels) {
3b5b516f PU	306	case 5:
	307	if (stream == SNDRV_PCM_STREAM_CAPTURE)
	308	/* up to 3 channels for capture */
	309	return -EINVAL;
	310	link_mask \|= 1 << 4;
db72c2f8 MLC	311	case 4:
db72c2f8 MLC	312	if (stream == SNDRV_PCM_STREAM_CAPTURE)
3b5b516f	313	/* up to 3 channels for capture */
db72c2f8 MLC	314	return -EINVAL;
	315	link_mask \|= 1 << 3;
	316	case 3:
db72c2f8 MLC	317	link_mask \|= 1 << 2;
	318	case 2:
	319	link_mask \|= 1 << 1;
	320	case 1:
	321	link_mask \|= 1 << 0;
	322	break;
	323	default:
	324	/* unsupported number of channels */
	325	return -EINVAL;
	326	}
	327
bcd6da7b	328	dma_data = snd_soc_dai_get_dma_data(dai, substream);
b199adfd	329
62376631	330	threshold = mcpdm->config[stream].threshold;
f5f9d7bf	331	/* Configure McPDM channels, and DMA packet size */
db72c2f8	332	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
62376631	333	link_mask <<= 3;
81054b22 PU	334
	335	/* If capture is not running assume a stereo stream to come */
	336	if (!mcpdm->config[!stream].link_mask)
	337	mcpdm->config[!stream].link_mask = 0x3;
	338
09ae3aaf	339	dma_data->maxburst =
62376631	340	(MCPDM_DN_THRES_MAX - threshold) * channels;
db72c2f8	341	} else {
81054b22 PU	342	/* If playback is not running assume a stereo stream to come */
	343	if (!mcpdm->config[!stream].link_mask)
	344	mcpdm->config[!stream].link_mask = (0x3 << 3);
	345
09ae3aaf	346	dma_data->maxburst = threshold * channels;
db72c2f8 MLC	347	}
db72c2f8 MLC	348
81054b22 PU	349	/* Check if we need to restart McPDM with this stream */
	350	if (mcpdm->config[stream].link_mask &&
	351	mcpdm->config[stream].link_mask != link_mask)
	352	mcpdm->restart = true;
	353
62376631	354	mcpdm->config[stream].link_mask = link_mask;
db72c2f8	355
f5f9d7bf	356	return 0;
db72c2f8 MLC	357	}
db72c2f8 MLC	358
f5f9d7bf	359	static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
db72c2f8 MLC	360	struct snd_soc_dai *dai)
db72c2f8 MLC	361	{
f5f9d7bf	362	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	363
f5f9d7bf MLC	364	if (!omap_mcpdm_active(mcpdm)) {
	365	omap_mcpdm_start(mcpdm);
	366	omap_mcpdm_reg_dump(mcpdm);
81054b22 PU	367	} else if (mcpdm->restart) {
	368	omap_mcpdm_stop(mcpdm);
	369	omap_mcpdm_start(mcpdm);
	370	mcpdm->restart = false;
	371	omap_mcpdm_reg_dump(mcpdm);
f5f9d7bf	372	}
db72c2f8	373
f5f9d7bf	374	return 0;
db72c2f8 MLC	375	}
db72c2f8 MLC	376
85e7652d	377	static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
db72c2f8 MLC	378	.startup = omap_mcpdm_dai_startup,
db72c2f8 MLC	379	.shutdown = omap_mcpdm_dai_shutdown,
db72c2f8	380	.hw_params = omap_mcpdm_dai_hw_params,
f5f9d7bf	381	.prepare = omap_mcpdm_prepare,
db72c2f8 MLC	382	};
db72c2f8 MLC	383
f5f9d7bf MLC	384	static int omap_mcpdm_probe(struct snd_soc_dai *dai)
	385	{
	386	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	387	int ret;
	388
	389	pm_runtime_enable(mcpdm->dev);
	390
	391	/* Disable lines while request is ongoing */
	392	pm_runtime_get_sync(mcpdm->dev);
	393	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
	394
ddd17531	395	ret = devm_request_irq(mcpdm->dev, mcpdm->irq, omap_mcpdm_irq_handler,
f5f9d7bf	396	0, "McPDM", (void *)mcpdm);
db72c2f8	397
f5f9d7bf MLC	398	pm_runtime_put_sync(mcpdm->dev);
	399
	400	if (ret) {
	401	dev_err(mcpdm->dev, "Request for IRQ failed\n");
	402	pm_runtime_disable(mcpdm->dev);
	403	}
	404
	405	/* Configure McPDM threshold values */
62376631 PU	406	mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
	407	mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
	408	MCPDM_UP_THRES_MAX - 3;
f5f9d7bf MLC	409	return ret;
	410	}
	411
	412	static int omap_mcpdm_remove(struct snd_soc_dai *dai)
f0fba2ad	413	{
f5f9d7bf MLC	414	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
f5f9d7bf MLC	415
f5f9d7bf MLC	416	pm_runtime_disable(mcpdm->dev);
f5f9d7bf MLC	417
f0fba2ad LG	418	return 0;
	419	}
	420
f5f9d7bf MLC	421	#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	422	#define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
	423
f0fba2ad	424	static struct snd_soc_dai_driver omap_mcpdm_dai = {
f5f9d7bf MLC	425	.probe = omap_mcpdm_probe,
	426	.remove = omap_mcpdm_remove,
	427	.probe_order = SND_SOC_COMP_ORDER_LATE,
	428	.remove_order = SND_SOC_COMP_ORDER_EARLY,
db72c2f8 MLC	429	.playback = {
db72c2f8 MLC	430	.channels_min = 1,
3b5b516f	431	.channels_max = 5,
db72c2f8 MLC	432	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	433	.formats = OMAP_MCPDM_FORMATS,
b4badd49	434	.sig_bits = 24,
db72c2f8 MLC	435	},
	436	.capture = {
	437	.channels_min = 1,
3b5b516f	438	.channels_max = 3,
db72c2f8 MLC	439	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	440	.formats = OMAP_MCPDM_FORMATS,
b4badd49	441	.sig_bits = 24,
db72c2f8 MLC	442	},
db72c2f8 MLC	443	.ops = &omap_mcpdm_dai_ops,
db72c2f8	444	};
f0fba2ad	445
58709a32 KM	446	static const struct snd_soc_component_driver omap_mcpdm_component = {
	447	.name = "omap-mcpdm",
	448	};
	449
89b0d550 PU	450	void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
	451	u8 rx1, u8 rx2)
	452	{
	453	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
	454
	455	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) \| MCPDM_DNOFST_RX2(rx2);
	456	}
	457	EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
	458
7ff60006	459	static int asoc_mcpdm_probe(struct platform_device *pdev)
f0fba2ad	460	{
f5f9d7bf MLC	461	struct omap_mcpdm *mcpdm;
f5f9d7bf MLC	462	struct resource *res;
f5f9d7bf	463
d77ae332	464	mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
f5f9d7bf MLC	465	if (!mcpdm)
	466	return -ENOMEM;
	467
	468	platform_set_drvdata(pdev, mcpdm);
	469
	470	mutex_init(&mcpdm->mutex);
	471
5a40c57a PU	472	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	473	if (res == NULL)
	474	return -ENOMEM;
	475
09ae3aaf LPC	476	mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
09ae3aaf LPC	477	mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;
5a40c57a	478
a8035f07 PU	479	mcpdm->dma_data[0].filter_data = "dn_link";
a8035f07 PU	480	mcpdm->dma_data[1].filter_data = "up_link";
5a40c57a PU	481
5a40c57a PU	482	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
77c641d3 SMP	483	mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
	484	if (IS_ERR(mcpdm->io_base))
	485	return PTR_ERR(mcpdm->io_base);
f5f9d7bf MLC	486
f5f9d7bf MLC	487	mcpdm->irq = platform_get_irq(pdev, 0);
d77ae332 PU	488	if (mcpdm->irq < 0)
d77ae332 PU	489	return mcpdm->irq;
f5f9d7bf MLC	490
f5f9d7bf MLC	491	mcpdm->dev = &pdev->dev;
f0fba2ad	492
6c3cc302 SK	493	return devm_snd_soc_register_component(&pdev->dev,
	494	&omap_mcpdm_component,
	495	&omap_mcpdm_dai, 1);
f0fba2ad LG	496	}
f0fba2ad LG	497
7cb8a1b5 PU	498	static const struct of_device_id omap_mcpdm_of_match[] = {
	499	{ .compatible = "ti,omap4-mcpdm", },
	500	{ }
	501	};
	502	MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
	503
f0fba2ad LG	504	static struct platform_driver asoc_mcpdm_driver = {
f0fba2ad LG	505	.driver = {
f5f9d7bf MLC	506	.name = "omap-mcpdm",
f5f9d7bf MLC	507	.owner = THIS_MODULE,
7cb8a1b5	508	.of_match_table = omap_mcpdm_of_match,
f0fba2ad LG	509	},
f0fba2ad LG	510
f5f9d7bf	511	.probe = asoc_mcpdm_probe,
f0fba2ad	512	};
db72c2f8	513
beda5bf5	514	module_platform_driver(asoc_mcpdm_driver);
db72c2f8	515
d66a547c	516	MODULE_ALIAS("platform:omap-mcpdm");
f5f9d7bf	517	MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
db72c2f8 MLC	518	MODULE_DESCRIPTION("OMAP PDM SoC Interface");
db72c2f8 MLC	519	MODULE_LICENSE("GPL");