[deliverable/linux.git] / sound / soc / omap / omap-mcpdm.c

/*
 * omap-mcpdm.c  --  OMAP ALSA SoC DAI driver using McPDM port
 *
 * Copyright (C) 2009 - 2011 Texas Instruments
 *
 * Author: Misael Lopez Cruz <misael.lopez@ti.com>
 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
 *          Margarita Olaya <magi.olaya@ti.com>
 *          Peter Ujfalusi <peter.ujfalusi@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/of_device.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
#include <sound/omap-pcm.h>

#include "omap-mcpdm.h"

struct mcpdm_link_config {
	u32 link_mask; /* channel mask for the direction */
	u32 threshold; /* FIFO threshold */
};

struct omap_mcpdm {
	struct device *dev;
	unsigned long phys_base;
	void __iomem *io_base;
	int irq;

	struct mutex mutex;

	/* Playback/Capture configuration */
	struct mcpdm_link_config config[2];

	/* McPDM dn offsets for rx1, and 2 channels */
	u32 dn_rx_offset;

	/* McPDM needs to be restarted due to runtime reconfiguration */
	bool restart;

	struct snd_dmaengine_dai_dma_data dma_data[2];
};

/*
 * Stream DMA parameters
 */

static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
{
	writel_relaxed(val, mcpdm->io_base + reg);
}

static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
{
	return readl_relaxed(mcpdm->io_base + reg);
}

#ifdef DEBUG
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
{
	dev_dbg(mcpdm->dev, "***********************\n");
	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	dev_dbg(mcpdm->dev, "IRQSTATUS:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	dev_dbg(mcpdm->dev, "DMAWAKEEN:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	dev_dbg(mcpdm->dev, "CTRL:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	dev_dbg(mcpdm->dev, "***********************\n");
}
#else
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
#endif

/*
 * Enables the transfer through the PDM interface to/from the Phoenix
 * codec by enabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl |= link_mask;
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
}

/*
 * Disables the transfer through the PDM interface to/from the Phoenix
 * codec by disabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK;

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(link_mask);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

}

/*
 * Is the physical McPDM interface active.
 */
static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
{
	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
					(MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
}

/*
 * Configures McPDM uplink, and downlink for audio.
 * This function should be called before omap_mcpdm_start.
 */
static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);

	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Enable DN RX1/2 offset cancellation feature, if configured */
	if (mcpdm->dn_rx_offset) {
		u32 dn_offset = mcpdm->dn_rx_offset;

		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
		dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	}

	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
			 mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
			 mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);

	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
			MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
}

/*
 * Cleans McPDM uplink, and downlink configuration.
 * This function should be called when the stream is closed.
 */
static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
{
	/* Disable irq request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);

	/* Disable DMA request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);

	/* Disable irq request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Disable DMA request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);

	/* Disable RX1/2 offset cancellation */
	if (mcpdm->dn_rx_offset)
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
}

static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
{
	struct omap_mcpdm *mcpdm = dev_id;
	int irq_status;

	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);

	/* Acknowledge irq event */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);

	if (irq_status & MCPDM_DN_IRQ_FULL)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");

	if (irq_status & MCPDM_DN_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");

	if (irq_status & MCPDM_DN_IRQ)
		dev_dbg(mcpdm->dev, "DN (playback) write request\n");

	if (irq_status & MCPDM_UP_IRQ_FULL)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");

	if (irq_status & MCPDM_UP_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");

	if (irq_status & MCPDM_UP_IRQ)
		dev_dbg(mcpdm->dev, "UP (capture) write request\n");

	return IRQ_HANDLED;
}

static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active)
		omap_mcpdm_open_streams(mcpdm);

	mutex_unlock(&mcpdm->mutex);

	return 0;
}

static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		if (omap_mcpdm_active(mcpdm)) {
			omap_mcpdm_stop(mcpdm);
			omap_mcpdm_close_streams(mcpdm);
			mcpdm->config[0].link_mask = 0;
			mcpdm->config[1].link_mask = 0;
		}
	}

	mutex_unlock(&mcpdm->mutex);
}

static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int stream = substream->stream;
	struct snd_dmaengine_dai_dma_data *dma_data;
	u32 threshold;
	int channels;
	int link_mask = 0;

	channels = params_channels(params);
	switch (channels) {
	case 5:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 4;
	case 4:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 3;
	case 3:
		link_mask |= 1 << 2;
	case 2:
		link_mask |= 1 << 1;
	case 1:
		link_mask |= 1 << 0;
		break;
	default:
		/* unsupported number of channels */
		return -EINVAL;
	}

	dma_data = snd_soc_dai_get_dma_data(dai, substream);

	threshold = mcpdm->config[stream].threshold;
	/* Configure McPDM channels, and DMA packet size */
	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		link_mask <<= 3;

		/* If capture is not running assume a stereo stream to come */
		if (!mcpdm->config[!stream].link_mask)
			mcpdm->config[!stream].link_mask = 0x3;

		dma_data->maxburst =
				(MCPDM_DN_THRES_MAX - threshold) * channels;
	} else {
		/* If playback is not running assume a stereo stream to come */
		if (!mcpdm->config[!stream].link_mask)
			mcpdm->config[!stream].link_mask = (0x3 << 3);

		dma_data->maxburst = threshold * channels;
	}

	/* Check if we need to restart McPDM with this stream */
	if (mcpdm->config[stream].link_mask &&
	    mcpdm->config[stream].link_mask != link_mask)
		mcpdm->restart = true;

	mcpdm->config[stream].link_mask = link_mask;

	return 0;
}

static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	if (!omap_mcpdm_active(mcpdm)) {
		omap_mcpdm_start(mcpdm);
		omap_mcpdm_reg_dump(mcpdm);
	} else if (mcpdm->restart) {
		omap_mcpdm_stop(mcpdm);
		omap_mcpdm_start(mcpdm);
		mcpdm->restart = false;
		omap_mcpdm_reg_dump(mcpdm);
	}

	return 0;
}

static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
	.startup	= omap_mcpdm_dai_startup,
	.shutdown	= omap_mcpdm_dai_shutdown,
	.hw_params	= omap_mcpdm_dai_hw_params,
	.prepare	= omap_mcpdm_prepare,
};

static int omap_mcpdm_probe(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int ret;

	pm_runtime_enable(mcpdm->dev);

	/* Disable lines while request is ongoing */
	pm_runtime_get_sync(mcpdm->dev);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);

	ret = devm_request_irq(mcpdm->dev, mcpdm->irq, omap_mcpdm_irq_handler,
				0, "McPDM", (void *)mcpdm);

	pm_runtime_put_sync(mcpdm->dev);

	if (ret) {
		dev_err(mcpdm->dev, "Request for IRQ failed\n");
		pm_runtime_disable(mcpdm->dev);
	}

	/* Configure McPDM threshold values */
	mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
	mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
							MCPDM_UP_THRES_MAX - 3;

	snd_soc_dai_init_dma_data(dai,
				  &mcpdm->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
				  &mcpdm->dma_data[SNDRV_PCM_STREAM_CAPTURE]);

	return ret;
}

static int omap_mcpdm_remove(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	pm_runtime_disable(mcpdm->dev);

	return 0;
}

#define OMAP_MCPDM_RATES	(SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define OMAP_MCPDM_FORMATS	SNDRV_PCM_FMTBIT_S32_LE

static struct snd_soc_dai_driver omap_mcpdm_dai = {
	.probe = omap_mcpdm_probe,
	.remove = omap_mcpdm_remove,
	.probe_order = SND_SOC_COMP_ORDER_LATE,
	.remove_order = SND_SOC_COMP_ORDER_EARLY,
	.playback = {
		.channels_min = 1,
		.channels_max = 5,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.capture = {
		.channels_min = 1,
		.channels_max = 3,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.ops = &omap_mcpdm_dai_ops,
};

static const struct snd_soc_component_driver omap_mcpdm_component = {
	.name		= "omap-mcpdm",
};

void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
				    u8 rx1, u8 rx2)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);

	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
}
EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);

static int asoc_mcpdm_probe(struct platform_device *pdev)
{
	struct omap_mcpdm *mcpdm;
	struct resource *res;
	int ret;

	mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
	if (!mcpdm)
		return -ENOMEM;

	platform_set_drvdata(pdev, mcpdm);

	mutex_init(&mcpdm->mutex);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	if (res == NULL)
		return -ENOMEM;

	mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
	mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;

	mcpdm->dma_data[0].filter_data = "dn_link";
	mcpdm->dma_data[1].filter_data = "up_link";

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
	mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mcpdm->io_base))
		return PTR_ERR(mcpdm->io_base);

	mcpdm->irq = platform_get_irq(pdev, 0);
	if (mcpdm->irq < 0)
		return mcpdm->irq;

	mcpdm->dev = &pdev->dev;

	ret =  devm_snd_soc_register_component(&pdev->dev,
					       &omap_mcpdm_component,
					       &omap_mcpdm_dai, 1);
	if (ret)
		return ret;

	return omap_pcm_platform_register(&pdev->dev);
}

static const struct of_device_id omap_mcpdm_of_match[] = {
	{ .compatible = "ti,omap4-mcpdm", },
	{ }
};
MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);

static struct platform_driver asoc_mcpdm_driver = {
	.driver = {
		.name	= "omap-mcpdm",
		.of_match_table = omap_mcpdm_of_match,
	},

	.probe	= asoc_mcpdm_probe,
};

module_platform_driver(asoc_mcpdm_driver);

MODULE_ALIAS("platform:omap-mcpdm");
MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
MODULE_DESCRIPTION("OMAP PDM SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
db72c2f8 MLC	1	/*
	2	* omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
	3	*
f5f9d7bf	4	* Copyright (C) 2009 - 2011 Texas Instruments
db72c2f8	5	*
f5f9d7bf	6	* Author: Misael Lopez Cruz <misael.lopez@ti.com>
db72c2f8 MLC	7	* Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
db72c2f8 MLC	8	* Margarita Olaya <magi.olaya@ti.com>
f5f9d7bf	9	* Peter Ujfalusi <peter.ujfalusi@ti.com>
db72c2f8 MLC	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License
	13	* version 2 as published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful, but
	16	* WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	23	* 02110-1301 USA
	24	*
	25	*/
	26
	27	#include <linux/init.h>
	28	#include <linux/module.h>
f5f9d7bf MLC	29	#include <linux/platform_device.h>
	30	#include <linux/interrupt.h>
	31	#include <linux/err.h>
	32	#include <linux/io.h>
	33	#include <linux/irq.h>
	34	#include <linux/slab.h>
	35	#include <linux/pm_runtime.h>
7cb8a1b5	36	#include <linux/of_device.h>
f5f9d7bf	37
db72c2f8 MLC	38	#include <sound/core.h>
	39	#include <sound/pcm.h>
	40	#include <sound/pcm_params.h>
db72c2f8	41	#include <sound/soc.h>
09ae3aaf	42	#include <sound/dmaengine_pcm.h>
87c19364	43	#include <sound/omap-pcm.h>
db72c2f8	44
f5f9d7bf	45	#include "omap-mcpdm.h"
db72c2f8	46
62376631 PU	47	struct mcpdm_link_config {
	48	u32 link_mask; /* channel mask for the direction */
	49	u32 threshold; /* FIFO threshold */
	50	};
dbc04161	51
f5f9d7bf MLC	52	struct omap_mcpdm {
	53	struct device *dev;
	54	unsigned long phys_base;
	55	void __iomem *io_base;
	56	int irq;
db72c2f8	57
f5f9d7bf MLC	58	struct mutex mutex;
f5f9d7bf MLC	59
62376631 PU	60	/* Playback/Capture configuration */
62376631 PU	61	struct mcpdm_link_config config[2];
89b0d550 PU	62
	63	/* McPDM dn offsets for rx1, and 2 channels */
	64	u32 dn_rx_offset;
81054b22 PU	65
	66	/* McPDM needs to be restarted due to runtime reconfiguration */
	67	bool restart;
09ae3aaf LPC	68
09ae3aaf LPC	69	struct snd_dmaengine_dai_dma_data dma_data[2];
db72c2f8 MLC	70	};
	71
	72	/*
	73	* Stream DMA parameters
	74	*/
db72c2f8	75
f5f9d7bf	76	static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
db72c2f8	77	{
1b488a48	78	writel_relaxed(val, mcpdm->io_base + reg);
f5f9d7bf	79	}
db72c2f8	80
f5f9d7bf MLC	81	static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
f5f9d7bf MLC	82	{
1b488a48	83	return readl_relaxed(mcpdm->io_base + reg);
f5f9d7bf	84	}
db72c2f8	85
f5f9d7bf MLC	86	#ifdef DEBUG
	87	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
	88	{
	89	dev_dbg(mcpdm->dev, "***********************\n");
	90	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
	91	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	92	dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
	93	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	94	dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
	95	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	96	dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
	97	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	98	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
	99	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	100	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
	101	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	102	dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
	103	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	104	dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
	105	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	106	dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
	107	omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	108	dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
	109	omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	110	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
	111	omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	112	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
	113	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	114	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
	115	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	116	dev_dbg(mcpdm->dev, "***********************\n");
db72c2f8	117	}
f5f9d7bf MLC	118	#else
	119	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
	120	#endif
db72c2f8	121
f5f9d7bf MLC	122	/*
	123	* Enables the transfer through the PDM interface to/from the Phoenix
	124	* codec by enabling the corresponding UP or DN channels.
	125	*/
	126	static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
	127	{
	128	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
62376631	129	u32 link_mask = mcpdm->config[0].link_mask \| mcpdm->config[1].link_mask;
f5f9d7bf MLC	130
	131	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	132	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	133
62376631	134	ctrl \|= link_mask;
f5f9d7bf MLC	135	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	136
	137	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	138	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	139	}
	140
	141	/*
	142	* Disables the transfer through the PDM interface to/from the Phoenix
	143	* codec by disabling the corresponding UP or DN channels.
	144	*/
	145	static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
	146	{
	147	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
81054b22	148	u32 link_mask = MCPDM_PDM_DN_MASK \| MCPDM_PDM_UP_MASK;
f5f9d7bf MLC	149
	150	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	151	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	152
62376631	153	ctrl &= ~(link_mask);
f5f9d7bf MLC	154	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	155
	156	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	157	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	158
	159	}
	160
	161	/*
	162	* Is the physical McPDM interface active.
	163	*/
	164	static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
	165	{
	166	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
	167	(MCPDM_PDM_DN_MASK \| MCPDM_PDM_UP_MASK);
	168	}
	169
	170	/*
	171	* Configures McPDM uplink, and downlink for audio.
	172	* This function should be called before omap_mcpdm_start.
	173	*/
	174	static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
	175	{
0efecc08 PU	176	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	177
	178	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl \| MCPDM_WD_EN);
	179
f5f9d7bf MLC	180	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
	181	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL \|
	182	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	183
89b0d550 PU	184	/* Enable DN RX1/2 offset cancellation feature, if configured */
	185	if (mcpdm->dn_rx_offset) {
	186	u32 dn_offset = mcpdm->dn_rx_offset;
	187
	188	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	189	dn_offset \|= (MCPDM_DN_OFST_RX1_EN \| MCPDM_DN_OFST_RX2_EN);
	190	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	191	}
	192
62376631 PU	193	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
	194	mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
	195	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
	196	mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);
f5f9d7bf MLC	197
	198	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
	199	MCPDM_DMA_DN_ENABLE \| MCPDM_DMA_UP_ENABLE);
	200	}
	201
	202	/*
	203	* Cleans McPDM uplink, and downlink configuration.
	204	* This function should be called when the stream is closed.
	205	*/
	206	static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
db72c2f8	207	{
f5f9d7bf MLC	208	/* Disable irq request generation for downlink */
	209	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	210	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL);
	211
	212	/* Disable DMA request generation for downlink */
	213	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
	214
	215	/* Disable irq request generation for uplink */
	216	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	217	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	218
	219	/* Disable DMA request generation for uplink */
	220	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
89b0d550 PU	221
	222	/* Disable RX1/2 offset cancellation */
	223	if (mcpdm->dn_rx_offset)
	224	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
f5f9d7bf MLC	225	}
	226
	227	static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
	228	{
	229	struct omap_mcpdm *mcpdm = dev_id;
	230	int irq_status;
	231
	232	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
	233
	234	/* Acknowledge irq event */
	235	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
	236
	237	if (irq_status & MCPDM_DN_IRQ_FULL)
	238	dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
	239
	240	if (irq_status & MCPDM_DN_IRQ_EMPTY)
	241	dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
	242
	243	if (irq_status & MCPDM_DN_IRQ)
	244	dev_dbg(mcpdm->dev, "DN (playback) write request\n");
	245
	246	if (irq_status & MCPDM_UP_IRQ_FULL)
	247	dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
	248
	249	if (irq_status & MCPDM_UP_IRQ_EMPTY)
	250	dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
	251
	252	if (irq_status & MCPDM_UP_IRQ)
	253	dev_dbg(mcpdm->dev, "UP (capture) write request\n");
	254
	255	return IRQ_HANDLED;
db72c2f8 MLC	256	}
db72c2f8 MLC	257
f5f9d7bf	258	static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
db72c2f8 MLC	259	struct snd_soc_dai *dai)
db72c2f8 MLC	260	{
f5f9d7bf	261	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	262
f5f9d7bf MLC	263	mutex_lock(&mcpdm->mutex);
f5f9d7bf MLC	264
0efecc08	265	if (!dai->active)
f5f9d7bf	266	omap_mcpdm_open_streams(mcpdm);
0efecc08	267
f5f9d7bf MLC	268	mutex_unlock(&mcpdm->mutex);
	269
	270	return 0;
	271	}
	272
	273	static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
	274	struct snd_soc_dai *dai)
	275	{
	276	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	277
	278	mutex_lock(&mcpdm->mutex);
	279
	280	if (!dai->active) {
	281	if (omap_mcpdm_active(mcpdm)) {
	282	omap_mcpdm_stop(mcpdm);
	283	omap_mcpdm_close_streams(mcpdm);
81054b22 PU	284	mcpdm->config[0].link_mask = 0;
81054b22 PU	285	mcpdm->config[1].link_mask = 0;
f5f9d7bf	286	}
f5f9d7bf MLC	287	}
	288
	289	mutex_unlock(&mcpdm->mutex);
db72c2f8 MLC	290	}
	291
	292	static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
	293	struct snd_pcm_hw_params *params,
	294	struct snd_soc_dai *dai)
	295	{
f5f9d7bf	296	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	297	int stream = substream->stream;
09ae3aaf	298	struct snd_dmaengine_dai_dma_data *dma_data;
62376631	299	u32 threshold;
f5f9d7bf MLC	300	int channels;
f5f9d7bf MLC	301	int link_mask = 0;
db72c2f8	302
db72c2f8 MLC	303	channels = params_channels(params);
db72c2f8 MLC	304	switch (channels) {
3b5b516f PU	305	case 5:
	306	if (stream == SNDRV_PCM_STREAM_CAPTURE)
	307	/* up to 3 channels for capture */
	308	return -EINVAL;
	309	link_mask \|= 1 << 4;
db72c2f8 MLC	310	case 4:
db72c2f8 MLC	311	if (stream == SNDRV_PCM_STREAM_CAPTURE)
3b5b516f	312	/* up to 3 channels for capture */
db72c2f8 MLC	313	return -EINVAL;
	314	link_mask \|= 1 << 3;
	315	case 3:
db72c2f8 MLC	316	link_mask \|= 1 << 2;
	317	case 2:
	318	link_mask \|= 1 << 1;
	319	case 1:
	320	link_mask \|= 1 << 0;
	321	break;
	322	default:
	323	/* unsupported number of channels */
	324	return -EINVAL;
	325	}
	326
bcd6da7b	327	dma_data = snd_soc_dai_get_dma_data(dai, substream);
b199adfd	328
62376631	329	threshold = mcpdm->config[stream].threshold;
f5f9d7bf	330	/* Configure McPDM channels, and DMA packet size */
db72c2f8	331	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
62376631	332	link_mask <<= 3;
81054b22 PU	333
	334	/* If capture is not running assume a stereo stream to come */
	335	if (!mcpdm->config[!stream].link_mask)
	336	mcpdm->config[!stream].link_mask = 0x3;
	337
09ae3aaf	338	dma_data->maxburst =
62376631	339	(MCPDM_DN_THRES_MAX - threshold) * channels;
db72c2f8	340	} else {
81054b22 PU	341	/* If playback is not running assume a stereo stream to come */
	342	if (!mcpdm->config[!stream].link_mask)
	343	mcpdm->config[!stream].link_mask = (0x3 << 3);
	344
09ae3aaf	345	dma_data->maxburst = threshold * channels;
db72c2f8 MLC	346	}
db72c2f8 MLC	347
81054b22 PU	348	/* Check if we need to restart McPDM with this stream */
	349	if (mcpdm->config[stream].link_mask &&
	350	mcpdm->config[stream].link_mask != link_mask)
	351	mcpdm->restart = true;
	352
62376631	353	mcpdm->config[stream].link_mask = link_mask;
db72c2f8	354
f5f9d7bf	355	return 0;
db72c2f8 MLC	356	}
db72c2f8 MLC	357
f5f9d7bf	358	static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
db72c2f8 MLC	359	struct snd_soc_dai *dai)
db72c2f8 MLC	360	{
f5f9d7bf	361	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	362
f5f9d7bf MLC	363	if (!omap_mcpdm_active(mcpdm)) {
	364	omap_mcpdm_start(mcpdm);
	365	omap_mcpdm_reg_dump(mcpdm);
81054b22 PU	366	} else if (mcpdm->restart) {
	367	omap_mcpdm_stop(mcpdm);
	368	omap_mcpdm_start(mcpdm);
	369	mcpdm->restart = false;
	370	omap_mcpdm_reg_dump(mcpdm);
f5f9d7bf	371	}
db72c2f8	372
f5f9d7bf	373	return 0;
db72c2f8 MLC	374	}
db72c2f8 MLC	375
85e7652d	376	static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
db72c2f8 MLC	377	.startup = omap_mcpdm_dai_startup,
db72c2f8 MLC	378	.shutdown = omap_mcpdm_dai_shutdown,
db72c2f8	379	.hw_params = omap_mcpdm_dai_hw_params,
f5f9d7bf	380	.prepare = omap_mcpdm_prepare,
db72c2f8 MLC	381	};
db72c2f8 MLC	382
f5f9d7bf MLC	383	static int omap_mcpdm_probe(struct snd_soc_dai *dai)
	384	{
	385	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	386	int ret;
	387
	388	pm_runtime_enable(mcpdm->dev);
	389
	390	/* Disable lines while request is ongoing */
	391	pm_runtime_get_sync(mcpdm->dev);
	392	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
	393
ddd17531	394	ret = devm_request_irq(mcpdm->dev, mcpdm->irq, omap_mcpdm_irq_handler,
f5f9d7bf	395	0, "McPDM", (void *)mcpdm);
db72c2f8	396
f5f9d7bf MLC	397	pm_runtime_put_sync(mcpdm->dev);
	398
	399	if (ret) {
	400	dev_err(mcpdm->dev, "Request for IRQ failed\n");
	401	pm_runtime_disable(mcpdm->dev);
	402	}
	403
	404	/* Configure McPDM threshold values */
62376631 PU	405	mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
	406	mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
	407	MCPDM_UP_THRES_MAX - 3;
f6563b31 PU	408
	409	snd_soc_dai_init_dma_data(dai,
	410	&mcpdm->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
	411	&mcpdm->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
	412
f5f9d7bf MLC	413	return ret;
	414	}
	415
	416	static int omap_mcpdm_remove(struct snd_soc_dai *dai)
f0fba2ad	417	{
f5f9d7bf MLC	418	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
f5f9d7bf MLC	419
f5f9d7bf MLC	420	pm_runtime_disable(mcpdm->dev);
f5f9d7bf MLC	421
f0fba2ad LG	422	return 0;
	423	}
	424
f5f9d7bf MLC	425	#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	426	#define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
	427
f0fba2ad	428	static struct snd_soc_dai_driver omap_mcpdm_dai = {
f5f9d7bf MLC	429	.probe = omap_mcpdm_probe,
	430	.remove = omap_mcpdm_remove,
	431	.probe_order = SND_SOC_COMP_ORDER_LATE,
	432	.remove_order = SND_SOC_COMP_ORDER_EARLY,
db72c2f8 MLC	433	.playback = {
db72c2f8 MLC	434	.channels_min = 1,
3b5b516f	435	.channels_max = 5,
db72c2f8 MLC	436	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	437	.formats = OMAP_MCPDM_FORMATS,
b4badd49	438	.sig_bits = 24,
db72c2f8 MLC	439	},
	440	.capture = {
	441	.channels_min = 1,
3b5b516f	442	.channels_max = 3,
db72c2f8 MLC	443	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	444	.formats = OMAP_MCPDM_FORMATS,
b4badd49	445	.sig_bits = 24,
db72c2f8 MLC	446	},
db72c2f8 MLC	447	.ops = &omap_mcpdm_dai_ops,
db72c2f8	448	};
f0fba2ad	449
58709a32 KM	450	static const struct snd_soc_component_driver omap_mcpdm_component = {
	451	.name = "omap-mcpdm",
	452	};
	453
89b0d550 PU	454	void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
	455	u8 rx1, u8 rx2)
	456	{
	457	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
	458
	459	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) \| MCPDM_DNOFST_RX2(rx2);
	460	}
	461	EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
	462
7ff60006	463	static int asoc_mcpdm_probe(struct platform_device *pdev)
f0fba2ad	464	{
f5f9d7bf MLC	465	struct omap_mcpdm *mcpdm;
f5f9d7bf MLC	466	struct resource *res;
335b0651	467	int ret;
f5f9d7bf	468
d77ae332	469	mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
f5f9d7bf MLC	470	if (!mcpdm)
	471	return -ENOMEM;
	472
	473	platform_set_drvdata(pdev, mcpdm);
	474
	475	mutex_init(&mcpdm->mutex);
	476
5a40c57a PU	477	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	478	if (res == NULL)
	479	return -ENOMEM;
	480
09ae3aaf LPC	481	mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
09ae3aaf LPC	482	mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;
5a40c57a	483
a8035f07 PU	484	mcpdm->dma_data[0].filter_data = "dn_link";
a8035f07 PU	485	mcpdm->dma_data[1].filter_data = "up_link";
5a40c57a PU	486
5a40c57a PU	487	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
77c641d3 SMP	488	mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
	489	if (IS_ERR(mcpdm->io_base))
	490	return PTR_ERR(mcpdm->io_base);
f5f9d7bf MLC	491
f5f9d7bf MLC	492	mcpdm->irq = platform_get_irq(pdev, 0);
d77ae332 PU	493	if (mcpdm->irq < 0)
d77ae332 PU	494	return mcpdm->irq;
f5f9d7bf MLC	495
f5f9d7bf MLC	496	mcpdm->dev = &pdev->dev;
f0fba2ad	497
335b0651	498	ret = devm_snd_soc_register_component(&pdev->dev,
6c3cc302 SK	499	&omap_mcpdm_component,
6c3cc302 SK	500	&omap_mcpdm_dai, 1);
335b0651 PU	501	if (ret)
	502	return ret;
	503
	504	return omap_pcm_platform_register(&pdev->dev);
f0fba2ad LG	505	}
f0fba2ad LG	506
7cb8a1b5 PU	507	static const struct of_device_id omap_mcpdm_of_match[] = {
	508	{ .compatible = "ti,omap4-mcpdm", },
	509	{ }
	510	};
	511	MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
	512
f0fba2ad LG	513	static struct platform_driver asoc_mcpdm_driver = {
f0fba2ad LG	514	.driver = {
f5f9d7bf	515	.name = "omap-mcpdm",
7cb8a1b5	516	.of_match_table = omap_mcpdm_of_match,
f0fba2ad LG	517	},
f0fba2ad LG	518
f5f9d7bf	519	.probe = asoc_mcpdm_probe,
f0fba2ad	520	};
db72c2f8	521
beda5bf5	522	module_platform_driver(asoc_mcpdm_driver);
db72c2f8	523
d66a547c	524	MODULE_ALIAS("platform:omap-mcpdm");
f5f9d7bf	525	MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
db72c2f8 MLC	526	MODULE_DESCRIPTION("OMAP PDM SoC Interface");
db72c2f8 MLC	527	MODULE_LICENSE("GPL");