[deliverable/linux.git] / sound / soc / omap / omap-mcpdm.c

/*
 * omap-mcpdm.c  --  OMAP ALSA SoC DAI driver using McPDM port
 *
 * Copyright (C) 2009 - 2011 Texas Instruments
 *
 * Author: Misael Lopez Cruz <misael.lopez@ti.com>
 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
 *          Margarita Olaya <magi.olaya@ti.com>
 *          Peter Ujfalusi <peter.ujfalusi@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/of_device.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include "omap-mcpdm.h"
#include "omap-pcm.h"

#define OMAP44XX_MCPDM_L3_BASE		0x49032000

struct omap_mcpdm {
	struct device *dev;
	unsigned long phys_base;
	void __iomem *io_base;
	int irq;

	struct mutex mutex;

	/* channel data */
	u32 dn_channels;
	u32 up_channels;

	/* McPDM FIFO thresholds */
	u32 dn_threshold;
	u32 up_threshold;

	/* McPDM dn offsets for rx1, and 2 channels */
	u32 dn_rx_offset;
};

/*
 * Stream DMA parameters
 */
static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
	{
		.name = "Audio playback",
	},
	{
		.name = "Audio capture",
	},
};

static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
{
	__raw_writel(val, mcpdm->io_base + reg);
}

static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
{
	return __raw_readl(mcpdm->io_base + reg);
}

#ifdef DEBUG
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
{
	dev_dbg(mcpdm->dev, "***********************\n");
	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	dev_dbg(mcpdm->dev, "IRQSTATUS:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	dev_dbg(mcpdm->dev, "DMAWAKEEN:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	dev_dbg(mcpdm->dev, "CTRL:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	dev_dbg(mcpdm->dev, "***********************\n");
}
#else
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
#endif

/*
 * Enables the transfer through the PDM interface to/from the Phoenix
 * codec by enabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl |= mcpdm->dn_channels | mcpdm->up_channels;
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
}

/*
 * Disables the transfer through the PDM interface to/from the Phoenix
 * codec by disabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(mcpdm->dn_channels | mcpdm->up_channels);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

}

/*
 * Is the physical McPDM interface active.
 */
static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
{
	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
					(MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
}

/*
 * Configures McPDM uplink, and downlink for audio.
 * This function should be called before omap_mcpdm_start.
 */
static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
{
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Enable DN RX1/2 offset cancellation feature, if configured */
	if (mcpdm->dn_rx_offset) {
		u32 dn_offset = mcpdm->dn_rx_offset;

		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
		dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	}

	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);

	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
			MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
}

/*
 * Cleans McPDM uplink, and downlink configuration.
 * This function should be called when the stream is closed.
 */
static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
{
	/* Disable irq request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);

	/* Disable DMA request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);

	/* Disable irq request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Disable DMA request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);

	/* Disable RX1/2 offset cancellation */
	if (mcpdm->dn_rx_offset)
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
}

static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
{
	struct omap_mcpdm *mcpdm = dev_id;
	int irq_status;

	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);

	/* Acknowledge irq event */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);

	if (irq_status & MCPDM_DN_IRQ_FULL)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");

	if (irq_status & MCPDM_DN_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");

	if (irq_status & MCPDM_DN_IRQ)
		dev_dbg(mcpdm->dev, "DN (playback) write request\n");

	if (irq_status & MCPDM_UP_IRQ_FULL)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");

	if (irq_status & MCPDM_UP_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");

	if (irq_status & MCPDM_UP_IRQ)
		dev_dbg(mcpdm->dev, "UP (capture) write request\n");

	return IRQ_HANDLED;
}

static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

		omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
		omap_mcpdm_open_streams(mcpdm);
	}
	mutex_unlock(&mcpdm->mutex);

	snd_soc_dai_set_dma_data(dai, substream,
				 &omap_mcpdm_dai_dma_params[substream->stream]);

	return 0;
}

static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		if (omap_mcpdm_active(mcpdm)) {
			omap_mcpdm_stop(mcpdm);
			omap_mcpdm_close_streams(mcpdm);
		}
	}

	mutex_unlock(&mcpdm->mutex);
}

static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int stream = substream->stream;
	struct omap_pcm_dma_data *dma_data;
	int channels;
	int link_mask = 0;

	channels = params_channels(params);
	switch (channels) {
	case 5:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 4;
	case 4:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 3;
	case 3:
		link_mask |= 1 << 2;
	case 2:
		link_mask |= 1 << 1;
	case 1:
		link_mask |= 1 << 0;
		break;
	default:
		/* unsupported number of channels */
		return -EINVAL;
	}

	dma_data = snd_soc_dai_get_dma_data(dai, substream);

	/* Configure McPDM channels, and DMA packet size */
	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		mcpdm->dn_channels = link_mask << 3;
		dma_data->packet_size =
			(MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
	} else {
		mcpdm->up_channels = link_mask << 0;
		dma_data->packet_size = mcpdm->up_threshold * channels;
	}

	return 0;
}

static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	if (!omap_mcpdm_active(mcpdm)) {
		omap_mcpdm_start(mcpdm);
		omap_mcpdm_reg_dump(mcpdm);
	}

	return 0;
}

static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
	.startup	= omap_mcpdm_dai_startup,
	.shutdown	= omap_mcpdm_dai_shutdown,
	.hw_params	= omap_mcpdm_dai_hw_params,
	.prepare	= omap_mcpdm_prepare,
};

static int omap_mcpdm_probe(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int ret;

	pm_runtime_enable(mcpdm->dev);

	/* Disable lines while request is ongoing */
	pm_runtime_get_sync(mcpdm->dev);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);

	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
				0, "McPDM", (void *)mcpdm);

	pm_runtime_put_sync(mcpdm->dev);

	if (ret) {
		dev_err(mcpdm->dev, "Request for IRQ failed\n");
		pm_runtime_disable(mcpdm->dev);
	}

	/* Configure McPDM threshold values */
	mcpdm->dn_threshold = 2;
	mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
	return ret;
}

static int omap_mcpdm_remove(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	free_irq(mcpdm->irq, (void *)mcpdm);
	pm_runtime_disable(mcpdm->dev);

	return 0;
}

#define OMAP_MCPDM_RATES	(SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define OMAP_MCPDM_FORMATS	SNDRV_PCM_FMTBIT_S32_LE

static struct snd_soc_dai_driver omap_mcpdm_dai = {
	.probe = omap_mcpdm_probe,
	.remove = omap_mcpdm_remove,
	.probe_order = SND_SOC_COMP_ORDER_LATE,
	.remove_order = SND_SOC_COMP_ORDER_EARLY,
	.playback = {
		.channels_min = 1,
		.channels_max = 5,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.capture = {
		.channels_min = 1,
		.channels_max = 3,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.ops = &omap_mcpdm_dai_ops,
};

void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
				    u8 rx1, u8 rx2)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);

	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
}
EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);

static int asoc_mcpdm_probe(struct platform_device *pdev)
{
	struct omap_mcpdm *mcpdm;
	struct resource *res;

	mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
	if (!mcpdm)
		return -ENOMEM;

	platform_set_drvdata(pdev, mcpdm);

	mutex_init(&mcpdm->mutex);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	if (res == NULL)
		return -ENOMEM;

	omap_mcpdm_dai_dma_params[0].port_addr = res->start + MCPDM_REG_DN_DATA;
	omap_mcpdm_dai_dma_params[1].port_addr = res->start + MCPDM_REG_UP_DATA;

	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "dn_link");
	if (!res)
		return -ENODEV;

	omap_mcpdm_dai_dma_params[0].dma_req = res->start;

	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "up_link");
	if (!res)
		return -ENODEV;

	omap_mcpdm_dai_dma_params[1].dma_req = res->start;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
	if (res == NULL)
		return -ENOMEM;

	if (!devm_request_mem_region(&pdev->dev, res->start,
				     resource_size(res), "McPDM"))
		return -EBUSY;

	mcpdm->io_base = devm_ioremap(&pdev->dev, res->start,
				      resource_size(res));
	if (!mcpdm->io_base)
		return -ENOMEM;

	mcpdm->irq = platform_get_irq(pdev, 0);
	if (mcpdm->irq < 0)
		return mcpdm->irq;

	mcpdm->dev = &pdev->dev;

	return snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
}

static int asoc_mcpdm_remove(struct platform_device *pdev)
{
	snd_soc_unregister_dai(&pdev->dev);
	return 0;
}

static const struct of_device_id omap_mcpdm_of_match[] = {
	{ .compatible = "ti,omap4-mcpdm", },
	{ }
};
MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);

static struct platform_driver asoc_mcpdm_driver = {
	.driver = {
		.name	= "omap-mcpdm",
		.owner	= THIS_MODULE,
		.of_match_table = omap_mcpdm_of_match,
	},

	.probe	= asoc_mcpdm_probe,
	.remove	= asoc_mcpdm_remove,
};

module_platform_driver(asoc_mcpdm_driver);

MODULE_ALIAS("platform:omap-mcpdm");
MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
MODULE_DESCRIPTION("OMAP PDM SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
db72c2f8 MLC	1	/*
	2	* omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
	3	*
f5f9d7bf	4	* Copyright (C) 2009 - 2011 Texas Instruments
db72c2f8	5	*
f5f9d7bf	6	* Author: Misael Lopez Cruz <misael.lopez@ti.com>
db72c2f8 MLC	7	* Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
db72c2f8 MLC	8	* Margarita Olaya <magi.olaya@ti.com>
f5f9d7bf	9	* Peter Ujfalusi <peter.ujfalusi@ti.com>
db72c2f8 MLC	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License
	13	* version 2 as published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful, but
	16	* WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	23	* 02110-1301 USA
	24	*
	25	*/
	26
	27	#include <linux/init.h>
	28	#include <linux/module.h>
f5f9d7bf MLC	29	#include <linux/platform_device.h>
	30	#include <linux/interrupt.h>
	31	#include <linux/err.h>
	32	#include <linux/io.h>
	33	#include <linux/irq.h>
	34	#include <linux/slab.h>
	35	#include <linux/pm_runtime.h>
7cb8a1b5	36	#include <linux/of_device.h>
f5f9d7bf	37
db72c2f8 MLC	38	#include <sound/core.h>
	39	#include <sound/pcm.h>
	40	#include <sound/pcm_params.h>
db72c2f8 MLC	41	#include <sound/soc.h>
db72c2f8 MLC	42
f5f9d7bf	43	#include "omap-mcpdm.h"
db72c2f8 MLC	44	#include "omap-pcm.h"
db72c2f8 MLC	45
dbc04161 TL	46	#define OMAP44XX_MCPDM_L3_BASE 0x49032000
dbc04161 TL	47
f5f9d7bf MLC	48	struct omap_mcpdm {
	49	struct device *dev;
	50	unsigned long phys_base;
	51	void __iomem *io_base;
	52	int irq;
db72c2f8	53
f5f9d7bf MLC	54	struct mutex mutex;
	55
	56	/* channel data */
	57	u32 dn_channels;
	58	u32 up_channels;
db72c2f8	59
f5f9d7bf MLC	60	/* McPDM FIFO thresholds */
	61	u32 dn_threshold;
	62	u32 up_threshold;
89b0d550 PU	63
	64	/* McPDM dn offsets for rx1, and 2 channels */
	65	u32 dn_rx_offset;
db72c2f8 MLC	66	};
	67
	68	/*
	69	* Stream DMA parameters
	70	*/
	71	static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
	72	{
	73	.name = "Audio playback",
db72c2f8 MLC	74	},
	75	{
	76	.name = "Audio capture",
db72c2f8 MLC	77	},
	78	};
	79
f5f9d7bf	80	static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
db72c2f8	81	{
f5f9d7bf MLC	82	__raw_writel(val, mcpdm->io_base + reg);
f5f9d7bf MLC	83	}
db72c2f8	84
f5f9d7bf MLC	85	static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
	86	{
	87	return __raw_readl(mcpdm->io_base + reg);
	88	}
db72c2f8	89
f5f9d7bf MLC	90	#ifdef DEBUG
	91	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
	92	{
	93	dev_dbg(mcpdm->dev, "***********************\n");
	94	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
	95	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	96	dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
	97	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	98	dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
	99	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	100	dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
	101	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	102	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
	103	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	104	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
	105	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	106	dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
	107	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	108	dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
	109	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	110	dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
	111	omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	112	dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
	113	omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	114	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
	115	omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	116	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
	117	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	118	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
	119	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	120	dev_dbg(mcpdm->dev, "***********************\n");
db72c2f8	121	}
f5f9d7bf MLC	122	#else
	123	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
	124	#endif
db72c2f8	125
f5f9d7bf MLC	126	/*
	127	* Enables the transfer through the PDM interface to/from the Phoenix
	128	* codec by enabling the corresponding UP or DN channels.
	129	*/
	130	static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
	131	{
	132	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	133
	134	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	135	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	136
	137	ctrl \|= mcpdm->dn_channels \| mcpdm->up_channels;
	138	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	139
	140	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	141	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	142	}
	143
	144	/*
	145	* Disables the transfer through the PDM interface to/from the Phoenix
	146	* codec by disabling the corresponding UP or DN channels.
	147	*/
	148	static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
	149	{
	150	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	151
	152	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	153	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	154
	155	ctrl &= ~(mcpdm->dn_channels \| mcpdm->up_channels);
	156	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	157
	158	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	159	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	160
	161	}
	162
	163	/*
	164	* Is the physical McPDM interface active.
	165	*/
	166	static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
	167	{
	168	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
	169	(MCPDM_PDM_DN_MASK \| MCPDM_PDM_UP_MASK);
	170	}
	171
	172	/*
	173	* Configures McPDM uplink, and downlink for audio.
	174	* This function should be called before omap_mcpdm_start.
	175	*/
	176	static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
	177	{
	178	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
	179	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL \|
	180	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	181
89b0d550 PU	182	/* Enable DN RX1/2 offset cancellation feature, if configured */
	183	if (mcpdm->dn_rx_offset) {
	184	u32 dn_offset = mcpdm->dn_rx_offset;
	185
	186	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	187	dn_offset \|= (MCPDM_DN_OFST_RX1_EN \| MCPDM_DN_OFST_RX2_EN);
	188	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	189	}
	190
f5f9d7bf MLC	191	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
	192	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);
	193
	194	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
	195	MCPDM_DMA_DN_ENABLE \| MCPDM_DMA_UP_ENABLE);
	196	}
	197
	198	/*
	199	* Cleans McPDM uplink, and downlink configuration.
	200	* This function should be called when the stream is closed.
	201	*/
	202	static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
db72c2f8	203	{
f5f9d7bf MLC	204	/* Disable irq request generation for downlink */
	205	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	206	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL);
	207
	208	/* Disable DMA request generation for downlink */
	209	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
	210
	211	/* Disable irq request generation for uplink */
	212	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	213	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	214
	215	/* Disable DMA request generation for uplink */
	216	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
89b0d550 PU	217
	218	/* Disable RX1/2 offset cancellation */
	219	if (mcpdm->dn_rx_offset)
	220	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
f5f9d7bf MLC	221	}
	222
	223	static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
	224	{
	225	struct omap_mcpdm *mcpdm = dev_id;
	226	int irq_status;
	227
	228	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
	229
	230	/* Acknowledge irq event */
	231	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
	232
	233	if (irq_status & MCPDM_DN_IRQ_FULL)
	234	dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
	235
	236	if (irq_status & MCPDM_DN_IRQ_EMPTY)
	237	dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
	238
	239	if (irq_status & MCPDM_DN_IRQ)
	240	dev_dbg(mcpdm->dev, "DN (playback) write request\n");
	241
	242	if (irq_status & MCPDM_UP_IRQ_FULL)
	243	dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
	244
	245	if (irq_status & MCPDM_UP_IRQ_EMPTY)
	246	dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
	247
	248	if (irq_status & MCPDM_UP_IRQ)
	249	dev_dbg(mcpdm->dev, "UP (capture) write request\n");
	250
	251	return IRQ_HANDLED;
db72c2f8 MLC	252	}
db72c2f8 MLC	253
f5f9d7bf	254	static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
db72c2f8 MLC	255	struct snd_soc_dai *dai)
db72c2f8 MLC	256	{
f5f9d7bf	257	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	258
f5f9d7bf MLC	259	mutex_lock(&mcpdm->mutex);
	260
	261	if (!dai->active) {
68214d99	262	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
f5f9d7bf	263
68214d99	264	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl \| MCPDM_WD_EN);
f5f9d7bf	265	omap_mcpdm_open_streams(mcpdm);
db72c2f8	266	}
f5f9d7bf MLC	267	mutex_unlock(&mcpdm->mutex);
f5f9d7bf MLC	268
bcd6da7b PU	269	snd_soc_dai_set_dma_data(dai, substream,
	270	&omap_mcpdm_dai_dma_params[substream->stream]);
	271
f5f9d7bf MLC	272	return 0;
	273	}
	274
	275	static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
	276	struct snd_soc_dai *dai)
	277	{
	278	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	279
	280	mutex_lock(&mcpdm->mutex);
	281
	282	if (!dai->active) {
	283	if (omap_mcpdm_active(mcpdm)) {
	284	omap_mcpdm_stop(mcpdm);
	285	omap_mcpdm_close_streams(mcpdm);
	286	}
f5f9d7bf MLC	287	}
	288
	289	mutex_unlock(&mcpdm->mutex);
db72c2f8 MLC	290	}
	291
	292	static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
	293	struct snd_pcm_hw_params *params,
	294	struct snd_soc_dai *dai)
	295	{
f5f9d7bf	296	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	297	int stream = substream->stream;
f5f9d7bf MLC	298	struct omap_pcm_dma_data *dma_data;
	299	int channels;
	300	int link_mask = 0;
db72c2f8	301
db72c2f8 MLC	302	channels = params_channels(params);
db72c2f8 MLC	303	switch (channels) {
3b5b516f PU	304	case 5:
	305	if (stream == SNDRV_PCM_STREAM_CAPTURE)
	306	/* up to 3 channels for capture */
	307	return -EINVAL;
	308	link_mask \|= 1 << 4;
db72c2f8 MLC	309	case 4:
db72c2f8 MLC	310	if (stream == SNDRV_PCM_STREAM_CAPTURE)
3b5b516f	311	/* up to 3 channels for capture */
db72c2f8 MLC	312	return -EINVAL;
	313	link_mask \|= 1 << 3;
	314	case 3:
db72c2f8 MLC	315	link_mask \|= 1 << 2;
	316	case 2:
	317	link_mask \|= 1 << 1;
	318	case 1:
	319	link_mask \|= 1 << 0;
	320	break;
	321	default:
	322	/* unsupported number of channels */
	323	return -EINVAL;
	324	}
	325
bcd6da7b	326	dma_data = snd_soc_dai_get_dma_data(dai, substream);
b199adfd	327
f5f9d7bf	328	/* Configure McPDM channels, and DMA packet size */
db72c2f8	329	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
f5f9d7bf MLC	330	mcpdm->dn_channels = link_mask << 3;
	331	dma_data->packet_size =
	332	(MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
db72c2f8	333	} else {
f5f9d7bf MLC	334	mcpdm->up_channels = link_mask << 0;
f5f9d7bf MLC	335	dma_data->packet_size = mcpdm->up_threshold * channels;
db72c2f8 MLC	336	}
db72c2f8 MLC	337
f5f9d7bf	338	return 0;
db72c2f8 MLC	339	}
db72c2f8 MLC	340
f5f9d7bf	341	static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
db72c2f8 MLC	342	struct snd_soc_dai *dai)
db72c2f8 MLC	343	{
f5f9d7bf	344	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	345
f5f9d7bf MLC	346	if (!omap_mcpdm_active(mcpdm)) {
	347	omap_mcpdm_start(mcpdm);
	348	omap_mcpdm_reg_dump(mcpdm);
	349	}
db72c2f8	350
f5f9d7bf	351	return 0;
db72c2f8 MLC	352	}
db72c2f8 MLC	353
85e7652d	354	static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
db72c2f8 MLC	355	.startup = omap_mcpdm_dai_startup,
db72c2f8 MLC	356	.shutdown = omap_mcpdm_dai_shutdown,
db72c2f8	357	.hw_params = omap_mcpdm_dai_hw_params,
f5f9d7bf	358	.prepare = omap_mcpdm_prepare,
db72c2f8 MLC	359	};
db72c2f8 MLC	360
f5f9d7bf MLC	361	static int omap_mcpdm_probe(struct snd_soc_dai *dai)
	362	{
	363	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	364	int ret;
	365
	366	pm_runtime_enable(mcpdm->dev);
	367
	368	/* Disable lines while request is ongoing */
	369	pm_runtime_get_sync(mcpdm->dev);
	370	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
	371
	372	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
	373	0, "McPDM", (void *)mcpdm);
db72c2f8	374
f5f9d7bf MLC	375	pm_runtime_put_sync(mcpdm->dev);
	376
	377	if (ret) {
	378	dev_err(mcpdm->dev, "Request for IRQ failed\n");
	379	pm_runtime_disable(mcpdm->dev);
	380	}
	381
	382	/* Configure McPDM threshold values */
	383	mcpdm->dn_threshold = 2;
	384	mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
	385	return ret;
	386	}
	387
	388	static int omap_mcpdm_remove(struct snd_soc_dai *dai)
f0fba2ad	389	{
f5f9d7bf MLC	390	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	391
	392	free_irq(mcpdm->irq, (void *)mcpdm);
	393	pm_runtime_disable(mcpdm->dev);
	394
f0fba2ad LG	395	return 0;
	396	}
	397
f5f9d7bf MLC	398	#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	399	#define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
	400
f0fba2ad	401	static struct snd_soc_dai_driver omap_mcpdm_dai = {
f5f9d7bf MLC	402	.probe = omap_mcpdm_probe,
	403	.remove = omap_mcpdm_remove,
	404	.probe_order = SND_SOC_COMP_ORDER_LATE,
	405	.remove_order = SND_SOC_COMP_ORDER_EARLY,
db72c2f8 MLC	406	.playback = {
db72c2f8 MLC	407	.channels_min = 1,
3b5b516f	408	.channels_max = 5,
db72c2f8 MLC	409	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	410	.formats = OMAP_MCPDM_FORMATS,
b4badd49	411	.sig_bits = 24,
db72c2f8 MLC	412	},
	413	.capture = {
	414	.channels_min = 1,
3b5b516f	415	.channels_max = 3,
db72c2f8 MLC	416	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	417	.formats = OMAP_MCPDM_FORMATS,
b4badd49	418	.sig_bits = 24,
db72c2f8 MLC	419	},
db72c2f8 MLC	420	.ops = &omap_mcpdm_dai_ops,
db72c2f8	421	};
f0fba2ad	422
89b0d550 PU	423	void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
	424	u8 rx1, u8 rx2)
	425	{
	426	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
	427
	428	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) \| MCPDM_DNOFST_RX2(rx2);
	429	}
	430	EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
	431
7ff60006	432	static int asoc_mcpdm_probe(struct platform_device *pdev)
f0fba2ad	433	{
f5f9d7bf MLC	434	struct omap_mcpdm *mcpdm;
f5f9d7bf MLC	435	struct resource *res;
f5f9d7bf	436
d77ae332	437	mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
f5f9d7bf MLC	438	if (!mcpdm)
	439	return -ENOMEM;
	440
	441	platform_set_drvdata(pdev, mcpdm);
	442
	443	mutex_init(&mcpdm->mutex);
	444
5a40c57a PU	445	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	446	if (res == NULL)
	447	return -ENOMEM;
	448
	449	omap_mcpdm_dai_dma_params[0].port_addr = res->start + MCPDM_REG_DN_DATA;
	450	omap_mcpdm_dai_dma_params[1].port_addr = res->start + MCPDM_REG_UP_DATA;
	451
5a40c57a PU	452	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "dn_link");
	453	if (!res)
	454	return -ENODEV;
f5f9d7bf	455
5a40c57a PU	456	omap_mcpdm_dai_dma_params[0].dma_req = res->start;
	457
	458	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "up_link");
	459	if (!res)
	460	return -ENODEV;
	461
	462	omap_mcpdm_dai_dma_params[1].dma_req = res->start;
	463
	464	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
	465	if (res == NULL)
	466	return -ENOMEM;
	467
d77ae332 PU	468	if (!devm_request_mem_region(&pdev->dev, res->start,
	469	resource_size(res), "McPDM"))
	470	return -EBUSY;
f5f9d7bf	471
d77ae332 PU	472	mcpdm->io_base = devm_ioremap(&pdev->dev, res->start,
	473	resource_size(res));
	474	if (!mcpdm->io_base)
	475	return -ENOMEM;
f5f9d7bf MLC	476
f5f9d7bf MLC	477	mcpdm->irq = platform_get_irq(pdev, 0);
d77ae332 PU	478	if (mcpdm->irq < 0)
d77ae332 PU	479	return mcpdm->irq;
f5f9d7bf MLC	480
f5f9d7bf MLC	481	mcpdm->dev = &pdev->dev;
f0fba2ad	482
d77ae332	483	return snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
f0fba2ad LG	484	}
f0fba2ad LG	485
7ff60006	486	static int asoc_mcpdm_remove(struct platform_device *pdev)
f0fba2ad LG	487	{
f0fba2ad LG	488	snd_soc_unregister_dai(&pdev->dev);
f0fba2ad LG	489	return 0;
	490	}
	491
7cb8a1b5 PU	492	static const struct of_device_id omap_mcpdm_of_match[] = {
	493	{ .compatible = "ti,omap4-mcpdm", },
	494	{ }
	495	};
	496	MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
	497
f0fba2ad LG	498	static struct platform_driver asoc_mcpdm_driver = {
f0fba2ad LG	499	.driver = {
f5f9d7bf MLC	500	.name = "omap-mcpdm",
f5f9d7bf MLC	501	.owner = THIS_MODULE,
7cb8a1b5	502	.of_match_table = omap_mcpdm_of_match,
f0fba2ad LG	503	},
f0fba2ad LG	504
f5f9d7bf	505	.probe = asoc_mcpdm_probe,
7ff60006	506	.remove = asoc_mcpdm_remove,
f0fba2ad	507	};
db72c2f8	508
beda5bf5	509	module_platform_driver(asoc_mcpdm_driver);
db72c2f8	510
d66a547c	511	MODULE_ALIAS("platform:omap-mcpdm");
f5f9d7bf	512	MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
db72c2f8 MLC	513	MODULE_DESCRIPTION("OMAP PDM SoC Interface");
db72c2f8 MLC	514	MODULE_LICENSE("GPL");