[deliverable/linux.git] / sound / soc / omap / omap-mcpdm.c

/*
 * omap-mcpdm.c  --  OMAP ALSA SoC DAI driver using McPDM port
 *
 * Copyright (C) 2009 - 2011 Texas Instruments
 *
 * Author: Misael Lopez Cruz <misael.lopez@ti.com>
 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
 *          Margarita Olaya <magi.olaya@ti.com>
 *          Peter Ujfalusi <peter.ujfalusi@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/of_device.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include <plat/dma.h>
#include <plat/omap_hwmod.h>
#include "omap-mcpdm.h"
#include "omap-pcm.h"

struct omap_mcpdm {
	struct device *dev;
	unsigned long phys_base;
	void __iomem *io_base;
	int irq;

	struct mutex mutex;

	/* channel data */
	u32 dn_channels;
	u32 up_channels;

	/* McPDM FIFO thresholds */
	u32 dn_threshold;
	u32 up_threshold;

	/* McPDM dn offsets for rx1, and 2 channels */
	u32 dn_rx_offset;
};

/*
 * Stream DMA parameters
 */
static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
	{
		.name = "Audio playback",
		.data_type = OMAP_DMA_DATA_TYPE_S32,
	},
	{
		.name = "Audio capture",
		.data_type = OMAP_DMA_DATA_TYPE_S32,
	},
};

static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
{
	__raw_writel(val, mcpdm->io_base + reg);
}

static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
{
	return __raw_readl(mcpdm->io_base + reg);
}

#ifdef DEBUG
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
{
	dev_dbg(mcpdm->dev, "***********************\n");
	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	dev_dbg(mcpdm->dev, "IRQSTATUS:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	dev_dbg(mcpdm->dev, "DMAWAKEEN:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	dev_dbg(mcpdm->dev, "CTRL:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	dev_dbg(mcpdm->dev, "***********************\n");
}
#else
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
#endif

/*
 * Enables the transfer through the PDM interface to/from the Phoenix
 * codec by enabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl |= mcpdm->dn_channels | mcpdm->up_channels;
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
}

/*
 * Disables the transfer through the PDM interface to/from the Phoenix
 * codec by disabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(mcpdm->dn_channels | mcpdm->up_channels);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

}

/*
 * Is the physical McPDM interface active.
 */
static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
{
	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
					(MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
}

/*
 * Configures McPDM uplink, and downlink for audio.
 * This function should be called before omap_mcpdm_start.
 */
static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
{
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Enable DN RX1/2 offset cancellation feature, if configured */
	if (mcpdm->dn_rx_offset) {
		u32 dn_offset = mcpdm->dn_rx_offset;

		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
		dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	}

	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);

	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
			MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
}

/*
 * Cleans McPDM uplink, and downlink configuration.
 * This function should be called when the stream is closed.
 */
static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
{
	/* Disable irq request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);

	/* Disable DMA request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);

	/* Disable irq request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Disable DMA request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);

	/* Disable RX1/2 offset cancellation */
	if (mcpdm->dn_rx_offset)
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
}

static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
{
	struct omap_mcpdm *mcpdm = dev_id;
	int irq_status;

	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);

	/* Acknowledge irq event */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);

	if (irq_status & MCPDM_DN_IRQ_FULL)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");

	if (irq_status & MCPDM_DN_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");

	if (irq_status & MCPDM_DN_IRQ)
		dev_dbg(mcpdm->dev, "DN (playback) write request\n");

	if (irq_status & MCPDM_UP_IRQ_FULL)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");

	if (irq_status & MCPDM_UP_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");

	if (irq_status & MCPDM_UP_IRQ)
		dev_dbg(mcpdm->dev, "UP (capture) write request\n");

	return IRQ_HANDLED;
}

static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		/* Enable watch dog for ES above ES 1.0 to avoid saturation */
		if (omap_rev() != OMAP4430_REV_ES1_0) {
			u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

			omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL,
					 ctrl | MCPDM_WD_EN);
		}
		omap_mcpdm_open_streams(mcpdm);
	}

	mutex_unlock(&mcpdm->mutex);

	return 0;
}

static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		if (omap_mcpdm_active(mcpdm)) {
			omap_mcpdm_stop(mcpdm);
			omap_mcpdm_close_streams(mcpdm);
		}
	}

	mutex_unlock(&mcpdm->mutex);
}

static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int stream = substream->stream;
	struct omap_pcm_dma_data *dma_data;
	int channels;
	int link_mask = 0;

	channels = params_channels(params);
	switch (channels) {
	case 5:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 4;
	case 4:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 3;
	case 3:
		link_mask |= 1 << 2;
	case 2:
		link_mask |= 1 << 1;
	case 1:
		link_mask |= 1 << 0;
		break;
	default:
		/* unsupported number of channels */
		return -EINVAL;
	}

	dma_data = &omap_mcpdm_dai_dma_params[stream];

	/* Configure McPDM channels, and DMA packet size */
	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		mcpdm->dn_channels = link_mask << 3;
		dma_data->packet_size =
			(MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
	} else {
		mcpdm->up_channels = link_mask << 0;
		dma_data->packet_size = mcpdm->up_threshold * channels;
	}

	snd_soc_dai_set_dma_data(dai, substream, dma_data);

	return 0;
}

static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	if (!omap_mcpdm_active(mcpdm)) {
		omap_mcpdm_start(mcpdm);
		omap_mcpdm_reg_dump(mcpdm);
	}

	return 0;
}

static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
	.startup	= omap_mcpdm_dai_startup,
	.shutdown	= omap_mcpdm_dai_shutdown,
	.hw_params	= omap_mcpdm_dai_hw_params,
	.prepare	= omap_mcpdm_prepare,
};

static int omap_mcpdm_probe(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int ret;

	pm_runtime_enable(mcpdm->dev);

	/* Disable lines while request is ongoing */
	pm_runtime_get_sync(mcpdm->dev);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);

	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
				0, "McPDM", (void *)mcpdm);

	pm_runtime_put_sync(mcpdm->dev);

	if (ret) {
		dev_err(mcpdm->dev, "Request for IRQ failed\n");
		pm_runtime_disable(mcpdm->dev);
	}

	/* Configure McPDM threshold values */
	mcpdm->dn_threshold = 2;
	mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
	return ret;
}

static int omap_mcpdm_remove(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	free_irq(mcpdm->irq, (void *)mcpdm);
	pm_runtime_disable(mcpdm->dev);

	return 0;
}

#define OMAP_MCPDM_RATES	(SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define OMAP_MCPDM_FORMATS	SNDRV_PCM_FMTBIT_S32_LE

static struct snd_soc_dai_driver omap_mcpdm_dai = {
	.probe = omap_mcpdm_probe,
	.remove = omap_mcpdm_remove,
	.probe_order = SND_SOC_COMP_ORDER_LATE,
	.remove_order = SND_SOC_COMP_ORDER_EARLY,
	.playback = {
		.channels_min = 1,
		.channels_max = 5,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.capture = {
		.channels_min = 1,
		.channels_max = 3,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.ops = &omap_mcpdm_dai_ops,
};

void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
				    u8 rx1, u8 rx2)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);

	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
}
EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);

static __devinit int asoc_mcpdm_probe(struct platform_device *pdev)
{
	struct omap_mcpdm *mcpdm;
	struct resource *res;

	mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
	if (!mcpdm)
		return -ENOMEM;

	platform_set_drvdata(pdev, mcpdm);

	mutex_init(&mcpdm->mutex);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	if (res == NULL)
		return -ENOMEM;

	omap_mcpdm_dai_dma_params[0].port_addr = res->start + MCPDM_REG_DN_DATA;
	omap_mcpdm_dai_dma_params[1].port_addr = res->start + MCPDM_REG_UP_DATA;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res == NULL)
		return -ENOMEM;

	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "dn_link");
	if (!res)
		return -ENODEV;

	omap_mcpdm_dai_dma_params[0].dma_req = res->start;

	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "up_link");
	if (!res)
		return -ENODEV;

	omap_mcpdm_dai_dma_params[1].dma_req = res->start;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
	if (res == NULL)
		return -ENOMEM;

	if (!devm_request_mem_region(&pdev->dev, res->start,
				     resource_size(res), "McPDM"))
		return -EBUSY;

	mcpdm->io_base = devm_ioremap(&pdev->dev, res->start,
				      resource_size(res));
	if (!mcpdm->io_base)
		return -ENOMEM;

	mcpdm->irq = platform_get_irq(pdev, 0);
	if (mcpdm->irq < 0)
		return mcpdm->irq;

	mcpdm->dev = &pdev->dev;

	return snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
}

static int __devexit asoc_mcpdm_remove(struct platform_device *pdev)
{
	snd_soc_unregister_dai(&pdev->dev);
	return 0;
}

static const struct of_device_id omap_mcpdm_of_match[] = {
	{ .compatible = "ti,omap4-mcpdm", },
	{ }
};
MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);

static struct platform_driver asoc_mcpdm_driver = {
	.driver = {
		.name	= "omap-mcpdm",
		.owner	= THIS_MODULE,
		.of_match_table = omap_mcpdm_of_match,
	},

	.probe	= asoc_mcpdm_probe,
	.remove	= __devexit_p(asoc_mcpdm_remove),
};

module_platform_driver(asoc_mcpdm_driver);

MODULE_ALIAS("platform:omap-mcpdm");
MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
MODULE_DESCRIPTION("OMAP PDM SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
db72c2f8 MLC	1	/*
	2	* omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
	3	*
f5f9d7bf	4	* Copyright (C) 2009 - 2011 Texas Instruments
db72c2f8	5	*
f5f9d7bf	6	* Author: Misael Lopez Cruz <misael.lopez@ti.com>
db72c2f8 MLC	7	* Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
db72c2f8 MLC	8	* Margarita Olaya <magi.olaya@ti.com>
f5f9d7bf	9	* Peter Ujfalusi <peter.ujfalusi@ti.com>
db72c2f8 MLC	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License
	13	* version 2 as published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful, but
	16	* WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	23	* 02110-1301 USA
	24	*
	25	*/
	26
	27	#include <linux/init.h>
	28	#include <linux/module.h>
f5f9d7bf MLC	29	#include <linux/platform_device.h>
	30	#include <linux/interrupt.h>
	31	#include <linux/err.h>
	32	#include <linux/io.h>
	33	#include <linux/irq.h>
	34	#include <linux/slab.h>
	35	#include <linux/pm_runtime.h>
7cb8a1b5	36	#include <linux/of_device.h>
f5f9d7bf	37
db72c2f8 MLC	38	#include <sound/core.h>
	39	#include <sound/pcm.h>
	40	#include <sound/pcm_params.h>
db72c2f8 MLC	41	#include <sound/soc.h>
db72c2f8 MLC	42
db72c2f8	43	#include <plat/dma.h>
f5f9d7bf MLC	44	#include <plat/omap_hwmod.h>
f5f9d7bf MLC	45	#include "omap-mcpdm.h"
db72c2f8 MLC	46	#include "omap-pcm.h"
db72c2f8 MLC	47
f5f9d7bf MLC	48	struct omap_mcpdm {
	49	struct device *dev;
	50	unsigned long phys_base;
	51	void __iomem *io_base;
	52	int irq;
db72c2f8	53
f5f9d7bf MLC	54	struct mutex mutex;
	55
	56	/* channel data */
	57	u32 dn_channels;
	58	u32 up_channels;
db72c2f8	59
f5f9d7bf MLC	60	/* McPDM FIFO thresholds */
	61	u32 dn_threshold;
	62	u32 up_threshold;
89b0d550 PU	63
	64	/* McPDM dn offsets for rx1, and 2 channels */
	65	u32 dn_rx_offset;
db72c2f8 MLC	66	};
	67
	68	/*
	69	* Stream DMA parameters
	70	*/
	71	static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
	72	{
	73	.name = "Audio playback",
db72c2f8	74	.data_type = OMAP_DMA_DATA_TYPE_S32,
db72c2f8 MLC	75	},
	76	{
	77	.name = "Audio capture",
db72c2f8	78	.data_type = OMAP_DMA_DATA_TYPE_S32,
db72c2f8 MLC	79	},
	80	};
	81
f5f9d7bf	82	static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
db72c2f8	83	{
f5f9d7bf MLC	84	__raw_writel(val, mcpdm->io_base + reg);
f5f9d7bf MLC	85	}
db72c2f8	86
f5f9d7bf MLC	87	static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
	88	{
	89	return __raw_readl(mcpdm->io_base + reg);
	90	}
db72c2f8	91
f5f9d7bf MLC	92	#ifdef DEBUG
	93	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
	94	{
	95	dev_dbg(mcpdm->dev, "***********************\n");
	96	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
	97	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	98	dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
	99	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	100	dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
	101	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	102	dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
	103	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	104	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
	105	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	106	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
	107	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	108	dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
	109	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	110	dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
	111	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	112	dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
	113	omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	114	dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
	115	omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	116	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
	117	omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	118	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
	119	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	120	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
	121	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	122	dev_dbg(mcpdm->dev, "***********************\n");
db72c2f8	123	}
f5f9d7bf MLC	124	#else
	125	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
	126	#endif
db72c2f8	127
f5f9d7bf MLC	128	/*
	129	* Enables the transfer through the PDM interface to/from the Phoenix
	130	* codec by enabling the corresponding UP or DN channels.
	131	*/
	132	static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
	133	{
	134	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	135
	136	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	137	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	138
	139	ctrl \|= mcpdm->dn_channels \| mcpdm->up_channels;
	140	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	141
	142	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	143	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	144	}
	145
	146	/*
	147	* Disables the transfer through the PDM interface to/from the Phoenix
	148	* codec by disabling the corresponding UP or DN channels.
	149	*/
	150	static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
	151	{
	152	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	153
	154	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	155	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	156
	157	ctrl &= ~(mcpdm->dn_channels \| mcpdm->up_channels);
	158	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	159
	160	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	161	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	162
	163	}
	164
	165	/*
	166	* Is the physical McPDM interface active.
	167	*/
	168	static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
	169	{
	170	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
	171	(MCPDM_PDM_DN_MASK \| MCPDM_PDM_UP_MASK);
	172	}
	173
	174	/*
	175	* Configures McPDM uplink, and downlink for audio.
	176	* This function should be called before omap_mcpdm_start.
	177	*/
	178	static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
	179	{
	180	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
	181	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL \|
	182	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	183
89b0d550 PU	184	/* Enable DN RX1/2 offset cancellation feature, if configured */
	185	if (mcpdm->dn_rx_offset) {
	186	u32 dn_offset = mcpdm->dn_rx_offset;
	187
	188	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	189	dn_offset \|= (MCPDM_DN_OFST_RX1_EN \| MCPDM_DN_OFST_RX2_EN);
	190	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	191	}
	192
f5f9d7bf MLC	193	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
	194	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);
	195
	196	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
	197	MCPDM_DMA_DN_ENABLE \| MCPDM_DMA_UP_ENABLE);
	198	}
	199
	200	/*
	201	* Cleans McPDM uplink, and downlink configuration.
	202	* This function should be called when the stream is closed.
	203	*/
	204	static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
db72c2f8	205	{
f5f9d7bf MLC	206	/* Disable irq request generation for downlink */
	207	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	208	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL);
	209
	210	/* Disable DMA request generation for downlink */
	211	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
	212
	213	/* Disable irq request generation for uplink */
	214	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	215	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	216
	217	/* Disable DMA request generation for uplink */
	218	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
89b0d550 PU	219
	220	/* Disable RX1/2 offset cancellation */
	221	if (mcpdm->dn_rx_offset)
	222	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
f5f9d7bf MLC	223	}
	224
	225	static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
	226	{
	227	struct omap_mcpdm *mcpdm = dev_id;
	228	int irq_status;
	229
	230	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
	231
	232	/* Acknowledge irq event */
	233	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
	234
	235	if (irq_status & MCPDM_DN_IRQ_FULL)
	236	dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
	237
	238	if (irq_status & MCPDM_DN_IRQ_EMPTY)
	239	dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
	240
	241	if (irq_status & MCPDM_DN_IRQ)
	242	dev_dbg(mcpdm->dev, "DN (playback) write request\n");
	243
	244	if (irq_status & MCPDM_UP_IRQ_FULL)
	245	dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
	246
	247	if (irq_status & MCPDM_UP_IRQ_EMPTY)
	248	dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
	249
	250	if (irq_status & MCPDM_UP_IRQ)
	251	dev_dbg(mcpdm->dev, "UP (capture) write request\n");
	252
	253	return IRQ_HANDLED;
db72c2f8 MLC	254	}
db72c2f8 MLC	255
f5f9d7bf	256	static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
db72c2f8 MLC	257	struct snd_soc_dai *dai)
db72c2f8 MLC	258	{
f5f9d7bf	259	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	260
f5f9d7bf MLC	261	mutex_lock(&mcpdm->mutex);
	262
	263	if (!dai->active) {
f5f9d7bf MLC	264	/* Enable watch dog for ES above ES 1.0 to avoid saturation */
	265	if (omap_rev() != OMAP4430_REV_ES1_0) {
	266	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	267
	268	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL,
	269	ctrl \| MCPDM_WD_EN);
	270	}
	271	omap_mcpdm_open_streams(mcpdm);
db72c2f8 MLC	272	}
db72c2f8 MLC	273
f5f9d7bf MLC	274	mutex_unlock(&mcpdm->mutex);
	275
	276	return 0;
	277	}
	278
	279	static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
	280	struct snd_soc_dai *dai)
	281	{
	282	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	283
	284	mutex_lock(&mcpdm->mutex);
	285
	286	if (!dai->active) {
	287	if (omap_mcpdm_active(mcpdm)) {
	288	omap_mcpdm_stop(mcpdm);
	289	omap_mcpdm_close_streams(mcpdm);
	290	}
f5f9d7bf MLC	291	}
	292
	293	mutex_unlock(&mcpdm->mutex);
db72c2f8 MLC	294	}
	295
	296	static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
	297	struct snd_pcm_hw_params *params,
	298	struct snd_soc_dai *dai)
	299	{
f5f9d7bf	300	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	301	int stream = substream->stream;
f5f9d7bf MLC	302	struct omap_pcm_dma_data *dma_data;
	303	int channels;
	304	int link_mask = 0;
db72c2f8	305
db72c2f8 MLC	306	channels = params_channels(params);
db72c2f8 MLC	307	switch (channels) {
3b5b516f PU	308	case 5:
	309	if (stream == SNDRV_PCM_STREAM_CAPTURE)
	310	/* up to 3 channels for capture */
	311	return -EINVAL;
	312	link_mask \|= 1 << 4;
db72c2f8 MLC	313	case 4:
db72c2f8 MLC	314	if (stream == SNDRV_PCM_STREAM_CAPTURE)
3b5b516f	315	/* up to 3 channels for capture */
db72c2f8 MLC	316	return -EINVAL;
	317	link_mask \|= 1 << 3;
	318	case 3:
db72c2f8 MLC	319	link_mask \|= 1 << 2;
	320	case 2:
	321	link_mask \|= 1 << 1;
	322	case 1:
	323	link_mask \|= 1 << 0;
	324	break;
	325	default:
	326	/* unsupported number of channels */
	327	return -EINVAL;
	328	}
	329
b199adfd	330	dma_data = &omap_mcpdm_dai_dma_params[stream];
b199adfd	331
f5f9d7bf	332	/* Configure McPDM channels, and DMA packet size */
db72c2f8	333	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
f5f9d7bf MLC	334	mcpdm->dn_channels = link_mask << 3;
	335	dma_data->packet_size =
	336	(MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
db72c2f8	337	} else {
f5f9d7bf MLC	338	mcpdm->up_channels = link_mask << 0;
f5f9d7bf MLC	339	dma_data->packet_size = mcpdm->up_threshold * channels;
db72c2f8 MLC	340	}
db72c2f8 MLC	341
b199adfd	342	snd_soc_dai_set_dma_data(dai, substream, dma_data);
f5f9d7bf MLC	343
f5f9d7bf MLC	344	return 0;
db72c2f8 MLC	345	}
db72c2f8 MLC	346
f5f9d7bf	347	static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
db72c2f8 MLC	348	struct snd_soc_dai *dai)
db72c2f8 MLC	349	{
f5f9d7bf	350	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	351
f5f9d7bf MLC	352	if (!omap_mcpdm_active(mcpdm)) {
	353	omap_mcpdm_start(mcpdm);
	354	omap_mcpdm_reg_dump(mcpdm);
	355	}
db72c2f8	356
f5f9d7bf	357	return 0;
db72c2f8 MLC	358	}
db72c2f8 MLC	359
85e7652d	360	static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
db72c2f8 MLC	361	.startup = omap_mcpdm_dai_startup,
db72c2f8 MLC	362	.shutdown = omap_mcpdm_dai_shutdown,
db72c2f8	363	.hw_params = omap_mcpdm_dai_hw_params,
f5f9d7bf	364	.prepare = omap_mcpdm_prepare,
db72c2f8 MLC	365	};
db72c2f8 MLC	366
f5f9d7bf MLC	367	static int omap_mcpdm_probe(struct snd_soc_dai *dai)
	368	{
	369	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	370	int ret;
	371
	372	pm_runtime_enable(mcpdm->dev);
	373
	374	/* Disable lines while request is ongoing */
	375	pm_runtime_get_sync(mcpdm->dev);
	376	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
	377
	378	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
	379	0, "McPDM", (void *)mcpdm);
db72c2f8	380
f5f9d7bf MLC	381	pm_runtime_put_sync(mcpdm->dev);
	382
	383	if (ret) {
	384	dev_err(mcpdm->dev, "Request for IRQ failed\n");
	385	pm_runtime_disable(mcpdm->dev);
	386	}
	387
	388	/* Configure McPDM threshold values */
	389	mcpdm->dn_threshold = 2;
	390	mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
	391	return ret;
	392	}
	393
	394	static int omap_mcpdm_remove(struct snd_soc_dai *dai)
f0fba2ad	395	{
f5f9d7bf MLC	396	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	397
	398	free_irq(mcpdm->irq, (void *)mcpdm);
	399	pm_runtime_disable(mcpdm->dev);
	400
f0fba2ad LG	401	return 0;
	402	}
	403
f5f9d7bf MLC	404	#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	405	#define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
	406
f0fba2ad	407	static struct snd_soc_dai_driver omap_mcpdm_dai = {
f5f9d7bf MLC	408	.probe = omap_mcpdm_probe,
	409	.remove = omap_mcpdm_remove,
	410	.probe_order = SND_SOC_COMP_ORDER_LATE,
	411	.remove_order = SND_SOC_COMP_ORDER_EARLY,
db72c2f8 MLC	412	.playback = {
db72c2f8 MLC	413	.channels_min = 1,
3b5b516f	414	.channels_max = 5,
db72c2f8 MLC	415	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	416	.formats = OMAP_MCPDM_FORMATS,
b4badd49	417	.sig_bits = 24,
db72c2f8 MLC	418	},
	419	.capture = {
	420	.channels_min = 1,
3b5b516f	421	.channels_max = 3,
db72c2f8 MLC	422	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	423	.formats = OMAP_MCPDM_FORMATS,
b4badd49	424	.sig_bits = 24,
db72c2f8 MLC	425	},
db72c2f8 MLC	426	.ops = &omap_mcpdm_dai_ops,
db72c2f8	427	};
f0fba2ad	428
89b0d550 PU	429	void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
	430	u8 rx1, u8 rx2)
	431	{
	432	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
	433
	434	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) \| MCPDM_DNOFST_RX2(rx2);
	435	}
	436	EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
	437
f0fba2ad LG	438	static __devinit int asoc_mcpdm_probe(struct platform_device *pdev)
f0fba2ad LG	439	{
f5f9d7bf MLC	440	struct omap_mcpdm *mcpdm;
f5f9d7bf MLC	441	struct resource *res;
f5f9d7bf	442
d77ae332	443	mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
f5f9d7bf MLC	444	if (!mcpdm)
	445	return -ENOMEM;
	446
	447	platform_set_drvdata(pdev, mcpdm);
	448
	449	mutex_init(&mcpdm->mutex);
	450
5a40c57a PU	451	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	452	if (res == NULL)
	453	return -ENOMEM;
	454
	455	omap_mcpdm_dai_dma_params[0].port_addr = res->start + MCPDM_REG_DN_DATA;
	456	omap_mcpdm_dai_dma_params[1].port_addr = res->start + MCPDM_REG_UP_DATA;
	457
f5f9d7bf	458	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d77ae332 PU	459	if (res == NULL)
d77ae332 PU	460	return -ENOMEM;
f5f9d7bf	461
5a40c57a PU	462	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "dn_link");
	463	if (!res)
	464	return -ENODEV;
	465
	466	omap_mcpdm_dai_dma_params[0].dma_req = res->start;
	467
	468	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "up_link");
	469	if (!res)
	470	return -ENODEV;
	471
	472	omap_mcpdm_dai_dma_params[1].dma_req = res->start;
	473
	474	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
	475	if (res == NULL)
	476	return -ENOMEM;
	477
d77ae332 PU	478	if (!devm_request_mem_region(&pdev->dev, res->start,
	479	resource_size(res), "McPDM"))
	480	return -EBUSY;
f5f9d7bf	481
d77ae332 PU	482	mcpdm->io_base = devm_ioremap(&pdev->dev, res->start,
	483	resource_size(res));
	484	if (!mcpdm->io_base)
	485	return -ENOMEM;
f5f9d7bf MLC	486
f5f9d7bf MLC	487	mcpdm->irq = platform_get_irq(pdev, 0);
d77ae332 PU	488	if (mcpdm->irq < 0)
d77ae332 PU	489	return mcpdm->irq;
f5f9d7bf MLC	490
f5f9d7bf MLC	491	mcpdm->dev = &pdev->dev;
f0fba2ad	492
d77ae332	493	return snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
f0fba2ad LG	494	}
	495
	496	static int __devexit asoc_mcpdm_remove(struct platform_device *pdev)
	497	{
	498	snd_soc_unregister_dai(&pdev->dev);
f0fba2ad LG	499	return 0;
	500	}
	501
7cb8a1b5 PU	502	static const struct of_device_id omap_mcpdm_of_match[] = {
	503	{ .compatible = "ti,omap4-mcpdm", },
	504	{ }
	505	};
	506	MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
	507
f0fba2ad LG	508	static struct platform_driver asoc_mcpdm_driver = {
f0fba2ad LG	509	.driver = {
f5f9d7bf MLC	510	.name = "omap-mcpdm",
f5f9d7bf MLC	511	.owner = THIS_MODULE,
7cb8a1b5	512	.of_match_table = omap_mcpdm_of_match,
f0fba2ad LG	513	},
f0fba2ad LG	514
f5f9d7bf MLC	515	.probe = asoc_mcpdm_probe,
f5f9d7bf MLC	516	.remove = __devexit_p(asoc_mcpdm_remove),
f0fba2ad	517	};
db72c2f8	518
beda5bf5	519	module_platform_driver(asoc_mcpdm_driver);
db72c2f8	520
d66a547c	521	MODULE_ALIAS("platform:omap-mcpdm");
f5f9d7bf	522	MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
db72c2f8 MLC	523	MODULE_DESCRIPTION("OMAP PDM SoC Interface");
db72c2f8 MLC	524	MODULE_LICENSE("GPL");