Commit | Line | Data |
---|---|---|
db72c2f8 MLC |
1 | /* |
2 | * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port | |
3 | * | |
f5f9d7bf | 4 | * Copyright (C) 2009 - 2011 Texas Instruments |
db72c2f8 | 5 | * |
f5f9d7bf | 6 | * Author: Misael Lopez Cruz <misael.lopez@ti.com> |
db72c2f8 MLC |
7 | * Contact: Jorge Eduardo Candelaria <x0107209@ti.com> |
8 | * Margarita Olaya <magi.olaya@ti.com> | |
f5f9d7bf | 9 | * Peter Ujfalusi <peter.ujfalusi@ti.com> |
db72c2f8 MLC |
10 | * |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * version 2 as published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
23 | * 02110-1301 USA | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
f5f9d7bf MLC |
29 | #include <linux/platform_device.h> |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/err.h> | |
32 | #include <linux/io.h> | |
33 | #include <linux/irq.h> | |
65aca64d | 34 | #include <linux/clk.h> |
f5f9d7bf MLC |
35 | #include <linux/slab.h> |
36 | #include <linux/pm_runtime.h> | |
7cb8a1b5 | 37 | #include <linux/of_device.h> |
f5f9d7bf | 38 | |
db72c2f8 MLC |
39 | #include <sound/core.h> |
40 | #include <sound/pcm.h> | |
41 | #include <sound/pcm_params.h> | |
db72c2f8 | 42 | #include <sound/soc.h> |
09ae3aaf | 43 | #include <sound/dmaengine_pcm.h> |
87c19364 | 44 | #include <sound/omap-pcm.h> |
db72c2f8 | 45 | |
f5f9d7bf | 46 | #include "omap-mcpdm.h" |
db72c2f8 | 47 | |
62376631 PU |
48 | struct mcpdm_link_config { |
49 | u32 link_mask; /* channel mask for the direction */ | |
50 | u32 threshold; /* FIFO threshold */ | |
51 | }; | |
dbc04161 | 52 | |
f5f9d7bf MLC |
53 | struct omap_mcpdm { |
54 | struct device *dev; | |
55 | unsigned long phys_base; | |
56 | void __iomem *io_base; | |
57 | int irq; | |
65aca64d | 58 | struct clk *pdmclk; |
db72c2f8 | 59 | |
f5f9d7bf MLC |
60 | struct mutex mutex; |
61 | ||
62376631 PU |
62 | /* Playback/Capture configuration */ |
63 | struct mcpdm_link_config config[2]; | |
89b0d550 PU |
64 | |
65 | /* McPDM dn offsets for rx1, and 2 channels */ | |
66 | u32 dn_rx_offset; | |
81054b22 PU |
67 | |
68 | /* McPDM needs to be restarted due to runtime reconfiguration */ | |
69 | bool restart; | |
09ae3aaf | 70 | |
4a5c8374 PU |
71 | /* pm state for suspend/resume handling */ |
72 | int pm_active_count; | |
73 | ||
09ae3aaf | 74 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
db72c2f8 MLC |
75 | }; |
76 | ||
77 | /* | |
78 | * Stream DMA parameters | |
79 | */ | |
db72c2f8 | 80 | |
f5f9d7bf | 81 | static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val) |
db72c2f8 | 82 | { |
1b488a48 | 83 | writel_relaxed(val, mcpdm->io_base + reg); |
f5f9d7bf | 84 | } |
db72c2f8 | 85 | |
f5f9d7bf MLC |
86 | static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg) |
87 | { | |
1b488a48 | 88 | return readl_relaxed(mcpdm->io_base + reg); |
f5f9d7bf | 89 | } |
db72c2f8 | 90 | |
f5f9d7bf MLC |
91 | #ifdef DEBUG |
92 | static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) | |
93 | { | |
94 | dev_dbg(mcpdm->dev, "***********************\n"); | |
95 | dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n", | |
96 | omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW)); | |
97 | dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n", | |
98 | omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS)); | |
99 | dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n", | |
100 | omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET)); | |
101 | dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n", | |
102 | omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR)); | |
103 | dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n", | |
104 | omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN)); | |
105 | dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n", | |
106 | omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET)); | |
107 | dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n", | |
108 | omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR)); | |
109 | dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n", | |
110 | omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN)); | |
111 | dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n", | |
112 | omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL)); | |
113 | dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n", | |
114 | omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA)); | |
115 | dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n", | |
116 | omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA)); | |
117 | dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n", | |
118 | omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN)); | |
119 | dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n", | |
120 | omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP)); | |
121 | dev_dbg(mcpdm->dev, "***********************\n"); | |
db72c2f8 | 122 | } |
f5f9d7bf MLC |
123 | #else |
124 | static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {} | |
125 | #endif | |
db72c2f8 | 126 | |
f5f9d7bf MLC |
127 | /* |
128 | * Enables the transfer through the PDM interface to/from the Phoenix | |
129 | * codec by enabling the corresponding UP or DN channels. | |
130 | */ | |
131 | static void omap_mcpdm_start(struct omap_mcpdm *mcpdm) | |
132 | { | |
133 | u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL); | |
62376631 | 134 | u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask; |
f5f9d7bf MLC |
135 | |
136 | ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); | |
137 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); | |
138 | ||
62376631 | 139 | ctrl |= link_mask; |
f5f9d7bf MLC |
140 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); |
141 | ||
142 | ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); | |
143 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); | |
144 | } | |
145 | ||
146 | /* | |
147 | * Disables the transfer through the PDM interface to/from the Phoenix | |
148 | * codec by disabling the corresponding UP or DN channels. | |
149 | */ | |
150 | static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm) | |
151 | { | |
152 | u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL); | |
81054b22 | 153 | u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK; |
f5f9d7bf MLC |
154 | |
155 | ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); | |
156 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); | |
157 | ||
62376631 | 158 | ctrl &= ~(link_mask); |
f5f9d7bf MLC |
159 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); |
160 | ||
161 | ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); | |
162 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); | |
163 | ||
164 | } | |
165 | ||
166 | /* | |
167 | * Is the physical McPDM interface active. | |
168 | */ | |
169 | static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm) | |
170 | { | |
171 | return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) & | |
172 | (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK); | |
173 | } | |
174 | ||
175 | /* | |
176 | * Configures McPDM uplink, and downlink for audio. | |
177 | * This function should be called before omap_mcpdm_start. | |
178 | */ | |
179 | static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm) | |
180 | { | |
0efecc08 PU |
181 | u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL); |
182 | ||
183 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN); | |
184 | ||
f5f9d7bf MLC |
185 | omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET, |
186 | MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL | | |
187 | MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL); | |
188 | ||
89b0d550 PU |
189 | /* Enable DN RX1/2 offset cancellation feature, if configured */ |
190 | if (mcpdm->dn_rx_offset) { | |
191 | u32 dn_offset = mcpdm->dn_rx_offset; | |
192 | ||
193 | omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset); | |
194 | dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN); | |
195 | omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset); | |
196 | } | |
197 | ||
62376631 PU |
198 | omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, |
199 | mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold); | |
200 | omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, | |
201 | mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold); | |
f5f9d7bf MLC |
202 | |
203 | omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET, | |
204 | MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE); | |
205 | } | |
206 | ||
207 | /* | |
208 | * Cleans McPDM uplink, and downlink configuration. | |
209 | * This function should be called when the stream is closed. | |
210 | */ | |
211 | static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm) | |
db72c2f8 | 212 | { |
f5f9d7bf MLC |
213 | /* Disable irq request generation for downlink */ |
214 | omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR, | |
215 | MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL); | |
216 | ||
217 | /* Disable DMA request generation for downlink */ | |
218 | omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE); | |
219 | ||
220 | /* Disable irq request generation for uplink */ | |
221 | omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR, | |
222 | MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL); | |
223 | ||
224 | /* Disable DMA request generation for uplink */ | |
225 | omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE); | |
89b0d550 PU |
226 | |
227 | /* Disable RX1/2 offset cancellation */ | |
228 | if (mcpdm->dn_rx_offset) | |
229 | omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0); | |
f5f9d7bf MLC |
230 | } |
231 | ||
232 | static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id) | |
233 | { | |
234 | struct omap_mcpdm *mcpdm = dev_id; | |
235 | int irq_status; | |
236 | ||
237 | irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS); | |
238 | ||
239 | /* Acknowledge irq event */ | |
240 | omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status); | |
241 | ||
242 | if (irq_status & MCPDM_DN_IRQ_FULL) | |
243 | dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n"); | |
244 | ||
245 | if (irq_status & MCPDM_DN_IRQ_EMPTY) | |
246 | dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n"); | |
247 | ||
248 | if (irq_status & MCPDM_DN_IRQ) | |
249 | dev_dbg(mcpdm->dev, "DN (playback) write request\n"); | |
250 | ||
251 | if (irq_status & MCPDM_UP_IRQ_FULL) | |
252 | dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n"); | |
253 | ||
254 | if (irq_status & MCPDM_UP_IRQ_EMPTY) | |
255 | dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n"); | |
256 | ||
257 | if (irq_status & MCPDM_UP_IRQ) | |
258 | dev_dbg(mcpdm->dev, "UP (capture) write request\n"); | |
259 | ||
260 | return IRQ_HANDLED; | |
db72c2f8 MLC |
261 | } |
262 | ||
f5f9d7bf | 263 | static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream, |
db72c2f8 MLC |
264 | struct snd_soc_dai *dai) |
265 | { | |
f5f9d7bf | 266 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); |
db72c2f8 | 267 | |
f5f9d7bf MLC |
268 | mutex_lock(&mcpdm->mutex); |
269 | ||
0efecc08 | 270 | if (!dai->active) |
f5f9d7bf | 271 | omap_mcpdm_open_streams(mcpdm); |
0efecc08 | 272 | |
f5f9d7bf MLC |
273 | mutex_unlock(&mcpdm->mutex); |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
278 | static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream, | |
279 | struct snd_soc_dai *dai) | |
280 | { | |
281 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); | |
282 | ||
283 | mutex_lock(&mcpdm->mutex); | |
284 | ||
285 | if (!dai->active) { | |
286 | if (omap_mcpdm_active(mcpdm)) { | |
287 | omap_mcpdm_stop(mcpdm); | |
288 | omap_mcpdm_close_streams(mcpdm); | |
81054b22 PU |
289 | mcpdm->config[0].link_mask = 0; |
290 | mcpdm->config[1].link_mask = 0; | |
f5f9d7bf | 291 | } |
f5f9d7bf MLC |
292 | } |
293 | ||
294 | mutex_unlock(&mcpdm->mutex); | |
db72c2f8 MLC |
295 | } |
296 | ||
297 | static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream, | |
298 | struct snd_pcm_hw_params *params, | |
299 | struct snd_soc_dai *dai) | |
300 | { | |
f5f9d7bf | 301 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); |
db72c2f8 | 302 | int stream = substream->stream; |
09ae3aaf | 303 | struct snd_dmaengine_dai_dma_data *dma_data; |
62376631 | 304 | u32 threshold; |
f5f9d7bf MLC |
305 | int channels; |
306 | int link_mask = 0; | |
db72c2f8 | 307 | |
db72c2f8 MLC |
308 | channels = params_channels(params); |
309 | switch (channels) { | |
3b5b516f PU |
310 | case 5: |
311 | if (stream == SNDRV_PCM_STREAM_CAPTURE) | |
312 | /* up to 3 channels for capture */ | |
313 | return -EINVAL; | |
314 | link_mask |= 1 << 4; | |
db72c2f8 MLC |
315 | case 4: |
316 | if (stream == SNDRV_PCM_STREAM_CAPTURE) | |
3b5b516f | 317 | /* up to 3 channels for capture */ |
db72c2f8 MLC |
318 | return -EINVAL; |
319 | link_mask |= 1 << 3; | |
320 | case 3: | |
db72c2f8 MLC |
321 | link_mask |= 1 << 2; |
322 | case 2: | |
323 | link_mask |= 1 << 1; | |
324 | case 1: | |
325 | link_mask |= 1 << 0; | |
326 | break; | |
327 | default: | |
328 | /* unsupported number of channels */ | |
329 | return -EINVAL; | |
330 | } | |
331 | ||
bcd6da7b | 332 | dma_data = snd_soc_dai_get_dma_data(dai, substream); |
b199adfd | 333 | |
62376631 | 334 | threshold = mcpdm->config[stream].threshold; |
f5f9d7bf | 335 | /* Configure McPDM channels, and DMA packet size */ |
db72c2f8 | 336 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
62376631 | 337 | link_mask <<= 3; |
81054b22 PU |
338 | |
339 | /* If capture is not running assume a stereo stream to come */ | |
340 | if (!mcpdm->config[!stream].link_mask) | |
341 | mcpdm->config[!stream].link_mask = 0x3; | |
342 | ||
09ae3aaf | 343 | dma_data->maxburst = |
62376631 | 344 | (MCPDM_DN_THRES_MAX - threshold) * channels; |
db72c2f8 | 345 | } else { |
81054b22 PU |
346 | /* If playback is not running assume a stereo stream to come */ |
347 | if (!mcpdm->config[!stream].link_mask) | |
348 | mcpdm->config[!stream].link_mask = (0x3 << 3); | |
349 | ||
09ae3aaf | 350 | dma_data->maxburst = threshold * channels; |
db72c2f8 MLC |
351 | } |
352 | ||
81054b22 PU |
353 | /* Check if we need to restart McPDM with this stream */ |
354 | if (mcpdm->config[stream].link_mask && | |
355 | mcpdm->config[stream].link_mask != link_mask) | |
356 | mcpdm->restart = true; | |
357 | ||
62376631 | 358 | mcpdm->config[stream].link_mask = link_mask; |
db72c2f8 | 359 | |
f5f9d7bf | 360 | return 0; |
db72c2f8 MLC |
361 | } |
362 | ||
f5f9d7bf | 363 | static int omap_mcpdm_prepare(struct snd_pcm_substream *substream, |
db72c2f8 MLC |
364 | struct snd_soc_dai *dai) |
365 | { | |
f5f9d7bf | 366 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); |
db72c2f8 | 367 | |
f5f9d7bf MLC |
368 | if (!omap_mcpdm_active(mcpdm)) { |
369 | omap_mcpdm_start(mcpdm); | |
370 | omap_mcpdm_reg_dump(mcpdm); | |
81054b22 PU |
371 | } else if (mcpdm->restart) { |
372 | omap_mcpdm_stop(mcpdm); | |
373 | omap_mcpdm_start(mcpdm); | |
374 | mcpdm->restart = false; | |
375 | omap_mcpdm_reg_dump(mcpdm); | |
f5f9d7bf | 376 | } |
db72c2f8 | 377 | |
f5f9d7bf | 378 | return 0; |
db72c2f8 MLC |
379 | } |
380 | ||
85e7652d | 381 | static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = { |
db72c2f8 MLC |
382 | .startup = omap_mcpdm_dai_startup, |
383 | .shutdown = omap_mcpdm_dai_shutdown, | |
db72c2f8 | 384 | .hw_params = omap_mcpdm_dai_hw_params, |
f5f9d7bf | 385 | .prepare = omap_mcpdm_prepare, |
db72c2f8 MLC |
386 | }; |
387 | ||
f5f9d7bf MLC |
388 | static int omap_mcpdm_probe(struct snd_soc_dai *dai) |
389 | { | |
390 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); | |
391 | int ret; | |
392 | ||
65aca64d | 393 | clk_prepare_enable(mcpdm->pdmclk); |
f5f9d7bf MLC |
394 | pm_runtime_enable(mcpdm->dev); |
395 | ||
396 | /* Disable lines while request is ongoing */ | |
397 | pm_runtime_get_sync(mcpdm->dev); | |
398 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00); | |
399 | ||
ddd17531 | 400 | ret = devm_request_irq(mcpdm->dev, mcpdm->irq, omap_mcpdm_irq_handler, |
f5f9d7bf | 401 | 0, "McPDM", (void *)mcpdm); |
db72c2f8 | 402 | |
f5f9d7bf MLC |
403 | pm_runtime_put_sync(mcpdm->dev); |
404 | ||
405 | if (ret) { | |
406 | dev_err(mcpdm->dev, "Request for IRQ failed\n"); | |
407 | pm_runtime_disable(mcpdm->dev); | |
408 | } | |
409 | ||
410 | /* Configure McPDM threshold values */ | |
62376631 PU |
411 | mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2; |
412 | mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold = | |
413 | MCPDM_UP_THRES_MAX - 3; | |
f6563b31 PU |
414 | |
415 | snd_soc_dai_init_dma_data(dai, | |
416 | &mcpdm->dma_data[SNDRV_PCM_STREAM_PLAYBACK], | |
417 | &mcpdm->dma_data[SNDRV_PCM_STREAM_CAPTURE]); | |
418 | ||
f5f9d7bf MLC |
419 | return ret; |
420 | } | |
421 | ||
422 | static int omap_mcpdm_remove(struct snd_soc_dai *dai) | |
f0fba2ad | 423 | { |
f5f9d7bf MLC |
424 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); |
425 | ||
f5f9d7bf MLC |
426 | pm_runtime_disable(mcpdm->dev); |
427 | ||
65aca64d | 428 | clk_disable_unprepare(mcpdm->pdmclk); |
f0fba2ad LG |
429 | return 0; |
430 | } | |
431 | ||
4a5c8374 PU |
432 | #ifdef CONFIG_PM_SLEEP |
433 | static int omap_mcpdm_suspend(struct snd_soc_dai *dai) | |
434 | { | |
435 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); | |
436 | ||
437 | if (dai->active) { | |
438 | omap_mcpdm_stop(mcpdm); | |
439 | omap_mcpdm_close_streams(mcpdm); | |
440 | } | |
441 | ||
442 | mcpdm->pm_active_count = 0; | |
443 | while (pm_runtime_active(mcpdm->dev)) { | |
444 | pm_runtime_put_sync(mcpdm->dev); | |
445 | mcpdm->pm_active_count++; | |
446 | } | |
447 | ||
65aca64d PU |
448 | clk_disable_unprepare(mcpdm->pdmclk); |
449 | ||
4a5c8374 PU |
450 | return 0; |
451 | } | |
452 | ||
453 | static int omap_mcpdm_resume(struct snd_soc_dai *dai) | |
454 | { | |
455 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); | |
456 | ||
65aca64d PU |
457 | clk_prepare_enable(mcpdm->pdmclk); |
458 | ||
4a5c8374 PU |
459 | if (mcpdm->pm_active_count) { |
460 | while (mcpdm->pm_active_count--) | |
461 | pm_runtime_get_sync(mcpdm->dev); | |
462 | ||
463 | if (dai->active) { | |
464 | omap_mcpdm_open_streams(mcpdm); | |
465 | omap_mcpdm_start(mcpdm); | |
466 | } | |
467 | } | |
468 | ||
469 | ||
470 | return 0; | |
471 | } | |
472 | #else | |
473 | #define omap_mcpdm_suspend NULL | |
474 | #define omap_mcpdm_resume NULL | |
475 | #endif | |
476 | ||
f5f9d7bf MLC |
477 | #define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) |
478 | #define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE | |
479 | ||
f0fba2ad | 480 | static struct snd_soc_dai_driver omap_mcpdm_dai = { |
f5f9d7bf MLC |
481 | .probe = omap_mcpdm_probe, |
482 | .remove = omap_mcpdm_remove, | |
4a5c8374 PU |
483 | .suspend = omap_mcpdm_suspend, |
484 | .resume = omap_mcpdm_resume, | |
f5f9d7bf MLC |
485 | .probe_order = SND_SOC_COMP_ORDER_LATE, |
486 | .remove_order = SND_SOC_COMP_ORDER_EARLY, | |
db72c2f8 MLC |
487 | .playback = { |
488 | .channels_min = 1, | |
3b5b516f | 489 | .channels_max = 5, |
db72c2f8 MLC |
490 | .rates = OMAP_MCPDM_RATES, |
491 | .formats = OMAP_MCPDM_FORMATS, | |
b4badd49 | 492 | .sig_bits = 24, |
db72c2f8 MLC |
493 | }, |
494 | .capture = { | |
495 | .channels_min = 1, | |
3b5b516f | 496 | .channels_max = 3, |
db72c2f8 MLC |
497 | .rates = OMAP_MCPDM_RATES, |
498 | .formats = OMAP_MCPDM_FORMATS, | |
b4badd49 | 499 | .sig_bits = 24, |
db72c2f8 MLC |
500 | }, |
501 | .ops = &omap_mcpdm_dai_ops, | |
db72c2f8 | 502 | }; |
f0fba2ad | 503 | |
58709a32 KM |
504 | static const struct snd_soc_component_driver omap_mcpdm_component = { |
505 | .name = "omap-mcpdm", | |
506 | }; | |
507 | ||
89b0d550 PU |
508 | void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd, |
509 | u8 rx1, u8 rx2) | |
510 | { | |
511 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai); | |
512 | ||
513 | mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2); | |
514 | } | |
515 | EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets); | |
516 | ||
7ff60006 | 517 | static int asoc_mcpdm_probe(struct platform_device *pdev) |
f0fba2ad | 518 | { |
f5f9d7bf MLC |
519 | struct omap_mcpdm *mcpdm; |
520 | struct resource *res; | |
335b0651 | 521 | int ret; |
f5f9d7bf | 522 | |
d77ae332 | 523 | mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL); |
f5f9d7bf MLC |
524 | if (!mcpdm) |
525 | return -ENOMEM; | |
526 | ||
527 | platform_set_drvdata(pdev, mcpdm); | |
528 | ||
529 | mutex_init(&mcpdm->mutex); | |
530 | ||
5a40c57a PU |
531 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); |
532 | if (res == NULL) | |
533 | return -ENOMEM; | |
534 | ||
09ae3aaf LPC |
535 | mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA; |
536 | mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA; | |
5a40c57a | 537 | |
a8035f07 PU |
538 | mcpdm->dma_data[0].filter_data = "dn_link"; |
539 | mcpdm->dma_data[1].filter_data = "up_link"; | |
5a40c57a PU |
540 | |
541 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); | |
77c641d3 SMP |
542 | mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res); |
543 | if (IS_ERR(mcpdm->io_base)) | |
544 | return PTR_ERR(mcpdm->io_base); | |
f5f9d7bf MLC |
545 | |
546 | mcpdm->irq = platform_get_irq(pdev, 0); | |
d77ae332 PU |
547 | if (mcpdm->irq < 0) |
548 | return mcpdm->irq; | |
f5f9d7bf MLC |
549 | |
550 | mcpdm->dev = &pdev->dev; | |
f0fba2ad | 551 | |
65aca64d PU |
552 | mcpdm->pdmclk = devm_clk_get(&pdev->dev, "pdmclk"); |
553 | if (IS_ERR(mcpdm->pdmclk)) { | |
554 | if (PTR_ERR(mcpdm->pdmclk) == -EPROBE_DEFER) | |
555 | return -EPROBE_DEFER; | |
556 | dev_warn(&pdev->dev, "Error getting pdmclk (%ld)!\n", | |
557 | PTR_ERR(mcpdm->pdmclk)); | |
558 | mcpdm->pdmclk = NULL; | |
559 | } | |
560 | ||
335b0651 | 561 | ret = devm_snd_soc_register_component(&pdev->dev, |
6c3cc302 SK |
562 | &omap_mcpdm_component, |
563 | &omap_mcpdm_dai, 1); | |
335b0651 PU |
564 | if (ret) |
565 | return ret; | |
566 | ||
567 | return omap_pcm_platform_register(&pdev->dev); | |
f0fba2ad LG |
568 | } |
569 | ||
7cb8a1b5 PU |
570 | static const struct of_device_id omap_mcpdm_of_match[] = { |
571 | { .compatible = "ti,omap4-mcpdm", }, | |
572 | { } | |
573 | }; | |
574 | MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match); | |
575 | ||
f0fba2ad LG |
576 | static struct platform_driver asoc_mcpdm_driver = { |
577 | .driver = { | |
f5f9d7bf | 578 | .name = "omap-mcpdm", |
7cb8a1b5 | 579 | .of_match_table = omap_mcpdm_of_match, |
f0fba2ad LG |
580 | }, |
581 | ||
f5f9d7bf | 582 | .probe = asoc_mcpdm_probe, |
f0fba2ad | 583 | }; |
db72c2f8 | 584 | |
beda5bf5 | 585 | module_platform_driver(asoc_mcpdm_driver); |
db72c2f8 | 586 | |
d66a547c | 587 | MODULE_ALIAS("platform:omap-mcpdm"); |
f5f9d7bf | 588 | MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>"); |
db72c2f8 MLC |
589 | MODULE_DESCRIPTION("OMAP PDM SoC Interface"); |
590 | MODULE_LICENSE("GPL"); |