[deliverable/linux.git] / sound / soc / omap / omap-mcpdm.c

/*
 * omap-mcpdm.c  --  OMAP ALSA SoC DAI driver using McPDM port
 *
 * Copyright (C) 2009 - 2011 Texas Instruments
 *
 * Author: Misael Lopez Cruz <misael.lopez@ti.com>
 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
 *          Margarita Olaya <magi.olaya@ti.com>
 *          Peter Ujfalusi <peter.ujfalusi@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/of_device.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include <plat/dma.h>
#include <plat/omap_hwmod.h>
#include "omap-mcpdm.h"
#include "omap-pcm.h"

struct omap_mcpdm {
	struct device *dev;
	unsigned long phys_base;
	void __iomem *io_base;
	int irq;

	struct mutex mutex;

	/* channel data */
	u32 dn_channels;
	u32 up_channels;

	/* McPDM FIFO thresholds */
	u32 dn_threshold;
	u32 up_threshold;

	/* McPDM dn offsets for rx1, and 2 channels */
	u32 dn_rx_offset;
};

/*
 * Stream DMA parameters
 */
static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
	{
		.name = "Audio playback",
		.dma_req = OMAP44XX_DMA_MCPDM_DL,
		.data_type = OMAP_DMA_DATA_TYPE_S32,
		.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_DN_DATA,
	},
	{
		.name = "Audio capture",
		.dma_req = OMAP44XX_DMA_MCPDM_UP,
		.data_type = OMAP_DMA_DATA_TYPE_S32,
		.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_UP_DATA,
	},
};

static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
{
	__raw_writel(val, mcpdm->io_base + reg);
}

static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
{
	return __raw_readl(mcpdm->io_base + reg);
}

#ifdef DEBUG
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
{
	dev_dbg(mcpdm->dev, "***********************\n");
	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	dev_dbg(mcpdm->dev, "IRQSTATUS:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	dev_dbg(mcpdm->dev, "DMAWAKEEN:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	dev_dbg(mcpdm->dev, "CTRL:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	dev_dbg(mcpdm->dev, "***********************\n");
}
#else
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
#endif

/*
 * Enables the transfer through the PDM interface to/from the Phoenix
 * codec by enabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl |= mcpdm->dn_channels | mcpdm->up_channels;
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
}

/*
 * Disables the transfer through the PDM interface to/from the Phoenix
 * codec by disabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(mcpdm->dn_channels | mcpdm->up_channels);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

}

/*
 * Is the physical McPDM interface active.
 */
static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
{
	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
					(MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
}

/*
 * Configures McPDM uplink, and downlink for audio.
 * This function should be called before omap_mcpdm_start.
 */
static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
{
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Enable DN RX1/2 offset cancellation feature, if configured */
	if (mcpdm->dn_rx_offset) {
		u32 dn_offset = mcpdm->dn_rx_offset;

		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
		dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	}

	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);

	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
			MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
}

/*
 * Cleans McPDM uplink, and downlink configuration.
 * This function should be called when the stream is closed.
 */
static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
{
	/* Disable irq request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);

	/* Disable DMA request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);

	/* Disable irq request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Disable DMA request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);

	/* Disable RX1/2 offset cancellation */
	if (mcpdm->dn_rx_offset)
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
}

static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
{
	struct omap_mcpdm *mcpdm = dev_id;
	int irq_status;

	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);

	/* Acknowledge irq event */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);

	if (irq_status & MCPDM_DN_IRQ_FULL)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");

	if (irq_status & MCPDM_DN_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");

	if (irq_status & MCPDM_DN_IRQ)
		dev_dbg(mcpdm->dev, "DN (playback) write request\n");

	if (irq_status & MCPDM_UP_IRQ_FULL)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");

	if (irq_status & MCPDM_UP_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");

	if (irq_status & MCPDM_UP_IRQ)
		dev_dbg(mcpdm->dev, "UP (capture) write request\n");

	return IRQ_HANDLED;
}

static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		/* Enable watch dog for ES above ES 1.0 to avoid saturation */
		if (omap_rev() != OMAP4430_REV_ES1_0) {
			u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

			omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL,
					 ctrl | MCPDM_WD_EN);
		}
		omap_mcpdm_open_streams(mcpdm);
	}

	mutex_unlock(&mcpdm->mutex);

	return 0;
}

static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		if (omap_mcpdm_active(mcpdm)) {
			omap_mcpdm_stop(mcpdm);
			omap_mcpdm_close_streams(mcpdm);
		}
	}

	mutex_unlock(&mcpdm->mutex);
}

static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int stream = substream->stream;
	struct omap_pcm_dma_data *dma_data;
	int channels;
	int link_mask = 0;

	channels = params_channels(params);
	switch (channels) {
	case 5:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 4;
	case 4:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 3;
	case 3:
		link_mask |= 1 << 2;
	case 2:
		link_mask |= 1 << 1;
	case 1:
		link_mask |= 1 << 0;
		break;
	default:
		/* unsupported number of channels */
		return -EINVAL;
	}

	dma_data = &omap_mcpdm_dai_dma_params[stream];

	/* Configure McPDM channels, and DMA packet size */
	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		mcpdm->dn_channels = link_mask << 3;
		dma_data->packet_size =
			(MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
	} else {
		mcpdm->up_channels = link_mask << 0;
		dma_data->packet_size = mcpdm->up_threshold * channels;
	}

	snd_soc_dai_set_dma_data(dai, substream, dma_data);

	return 0;
}

static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	if (!omap_mcpdm_active(mcpdm)) {
		omap_mcpdm_start(mcpdm);
		omap_mcpdm_reg_dump(mcpdm);
	}

	return 0;
}

static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
	.startup	= omap_mcpdm_dai_startup,
	.shutdown	= omap_mcpdm_dai_shutdown,
	.hw_params	= omap_mcpdm_dai_hw_params,
	.prepare	= omap_mcpdm_prepare,
};

static int omap_mcpdm_probe(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int ret;

	pm_runtime_enable(mcpdm->dev);

	/* Disable lines while request is ongoing */
	pm_runtime_get_sync(mcpdm->dev);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);

	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
				0, "McPDM", (void *)mcpdm);

	pm_runtime_put_sync(mcpdm->dev);

	if (ret) {
		dev_err(mcpdm->dev, "Request for IRQ failed\n");
		pm_runtime_disable(mcpdm->dev);
	}

	/* Configure McPDM threshold values */
	mcpdm->dn_threshold = 2;
	mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
	return ret;
}

static int omap_mcpdm_remove(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	free_irq(mcpdm->irq, (void *)mcpdm);
	pm_runtime_disable(mcpdm->dev);

	return 0;
}

#define OMAP_MCPDM_RATES	(SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define OMAP_MCPDM_FORMATS	SNDRV_PCM_FMTBIT_S32_LE

static struct snd_soc_dai_driver omap_mcpdm_dai = {
	.probe = omap_mcpdm_probe,
	.remove = omap_mcpdm_remove,
	.probe_order = SND_SOC_COMP_ORDER_LATE,
	.remove_order = SND_SOC_COMP_ORDER_EARLY,
	.playback = {
		.channels_min = 1,
		.channels_max = 5,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.capture = {
		.channels_min = 1,
		.channels_max = 3,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.ops = &omap_mcpdm_dai_ops,
};

void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
				    u8 rx1, u8 rx2)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);

	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
}
EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);

static __devinit int asoc_mcpdm_probe(struct platform_device *pdev)
{
	struct omap_mcpdm *mcpdm;
	struct resource *res;

	mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
	if (!mcpdm)
		return -ENOMEM;

	platform_set_drvdata(pdev, mcpdm);

	mutex_init(&mcpdm->mutex);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res == NULL)
		return -ENOMEM;

	if (!devm_request_mem_region(&pdev->dev, res->start,
				     resource_size(res), "McPDM"))
		return -EBUSY;

	mcpdm->io_base = devm_ioremap(&pdev->dev, res->start,
				      resource_size(res));
	if (!mcpdm->io_base)
		return -ENOMEM;

	mcpdm->irq = platform_get_irq(pdev, 0);
	if (mcpdm->irq < 0)
		return mcpdm->irq;

	mcpdm->dev = &pdev->dev;

	return snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
}

static int __devexit asoc_mcpdm_remove(struct platform_device *pdev)
{
	snd_soc_unregister_dai(&pdev->dev);
	return 0;
}

static const struct of_device_id omap_mcpdm_of_match[] = {
	{ .compatible = "ti,omap4-mcpdm", },
	{ }
};
MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);

static struct platform_driver asoc_mcpdm_driver = {
	.driver = {
		.name	= "omap-mcpdm",
		.owner	= THIS_MODULE,
		.of_match_table = omap_mcpdm_of_match,
	},

	.probe	= asoc_mcpdm_probe,
	.remove	= __devexit_p(asoc_mcpdm_remove),
};

module_platform_driver(asoc_mcpdm_driver);

MODULE_ALIAS("platform:omap-mcpdm");
MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
MODULE_DESCRIPTION("OMAP PDM SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
db72c2f8 MLC	1	/*
	2	* omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
	3	*
f5f9d7bf	4	* Copyright (C) 2009 - 2011 Texas Instruments
db72c2f8	5	*
f5f9d7bf	6	* Author: Misael Lopez Cruz <misael.lopez@ti.com>
db72c2f8 MLC	7	* Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
db72c2f8 MLC	8	* Margarita Olaya <magi.olaya@ti.com>
f5f9d7bf	9	* Peter Ujfalusi <peter.ujfalusi@ti.com>
db72c2f8 MLC	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License
	13	* version 2 as published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful, but
	16	* WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	23	* 02110-1301 USA
	24	*
	25	*/
	26
	27	#include <linux/init.h>
	28	#include <linux/module.h>
f5f9d7bf MLC	29	#include <linux/platform_device.h>
	30	#include <linux/interrupt.h>
	31	#include <linux/err.h>
	32	#include <linux/io.h>
	33	#include <linux/irq.h>
	34	#include <linux/slab.h>
	35	#include <linux/pm_runtime.h>
7cb8a1b5	36	#include <linux/of_device.h>
f5f9d7bf	37
db72c2f8 MLC	38	#include <sound/core.h>
	39	#include <sound/pcm.h>
	40	#include <sound/pcm_params.h>
db72c2f8 MLC	41	#include <sound/soc.h>
db72c2f8 MLC	42
db72c2f8	43	#include <plat/dma.h>
f5f9d7bf MLC	44	#include <plat/omap_hwmod.h>
f5f9d7bf MLC	45	#include "omap-mcpdm.h"
db72c2f8 MLC	46	#include "omap-pcm.h"
db72c2f8 MLC	47
f5f9d7bf MLC	48	struct omap_mcpdm {
	49	struct device *dev;
	50	unsigned long phys_base;
	51	void __iomem *io_base;
	52	int irq;
db72c2f8	53
f5f9d7bf MLC	54	struct mutex mutex;
	55
	56	/* channel data */
	57	u32 dn_channels;
	58	u32 up_channels;
db72c2f8	59
f5f9d7bf MLC	60	/* McPDM FIFO thresholds */
	61	u32 dn_threshold;
	62	u32 up_threshold;
89b0d550 PU	63
	64	/* McPDM dn offsets for rx1, and 2 channels */
	65	u32 dn_rx_offset;
db72c2f8 MLC	66	};
	67
	68	/*
	69	* Stream DMA parameters
	70	*/
	71	static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
	72	{
	73	.name = "Audio playback",
	74	.dma_req = OMAP44XX_DMA_MCPDM_DL,
	75	.data_type = OMAP_DMA_DATA_TYPE_S32,
f5f9d7bf	76	.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_DN_DATA,
db72c2f8 MLC	77	},
	78	{
	79	.name = "Audio capture",
	80	.dma_req = OMAP44XX_DMA_MCPDM_UP,
	81	.data_type = OMAP_DMA_DATA_TYPE_S32,
f5f9d7bf	82	.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_UP_DATA,
db72c2f8 MLC	83	},
	84	};
	85
f5f9d7bf	86	static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
db72c2f8	87	{
f5f9d7bf MLC	88	__raw_writel(val, mcpdm->io_base + reg);
f5f9d7bf MLC	89	}
db72c2f8	90
f5f9d7bf MLC	91	static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
	92	{
	93	return __raw_readl(mcpdm->io_base + reg);
	94	}
db72c2f8	95
f5f9d7bf MLC	96	#ifdef DEBUG
	97	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
	98	{
	99	dev_dbg(mcpdm->dev, "***********************\n");
	100	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
	101	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	102	dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
	103	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	104	dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
	105	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	106	dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
	107	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	108	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
	109	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	110	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
	111	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	112	dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
	113	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	114	dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
	115	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	116	dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
	117	omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	118	dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
	119	omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	120	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
	121	omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	122	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
	123	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	124	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
	125	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	126	dev_dbg(mcpdm->dev, "***********************\n");
db72c2f8	127	}
f5f9d7bf MLC	128	#else
	129	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
	130	#endif
db72c2f8	131
f5f9d7bf MLC	132	/*
	133	* Enables the transfer through the PDM interface to/from the Phoenix
	134	* codec by enabling the corresponding UP or DN channels.
	135	*/
	136	static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
	137	{
	138	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	139
	140	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	141	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	142
	143	ctrl \|= mcpdm->dn_channels \| mcpdm->up_channels;
	144	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	145
	146	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	147	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	148	}
	149
	150	/*
	151	* Disables the transfer through the PDM interface to/from the Phoenix
	152	* codec by disabling the corresponding UP or DN channels.
	153	*/
	154	static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
	155	{
	156	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	157
	158	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	159	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	160
	161	ctrl &= ~(mcpdm->dn_channels \| mcpdm->up_channels);
	162	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	163
	164	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	165	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	166
	167	}
	168
	169	/*
	170	* Is the physical McPDM interface active.
	171	*/
	172	static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
	173	{
	174	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
	175	(MCPDM_PDM_DN_MASK \| MCPDM_PDM_UP_MASK);
	176	}
	177
	178	/*
	179	* Configures McPDM uplink, and downlink for audio.
	180	* This function should be called before omap_mcpdm_start.
	181	*/
	182	static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
	183	{
	184	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
	185	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL \|
	186	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	187
89b0d550 PU	188	/* Enable DN RX1/2 offset cancellation feature, if configured */
	189	if (mcpdm->dn_rx_offset) {
	190	u32 dn_offset = mcpdm->dn_rx_offset;
	191
	192	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	193	dn_offset \|= (MCPDM_DN_OFST_RX1_EN \| MCPDM_DN_OFST_RX2_EN);
	194	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	195	}
	196
f5f9d7bf MLC	197	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
	198	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);
	199
	200	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
	201	MCPDM_DMA_DN_ENABLE \| MCPDM_DMA_UP_ENABLE);
	202	}
	203
	204	/*
	205	* Cleans McPDM uplink, and downlink configuration.
	206	* This function should be called when the stream is closed.
	207	*/
	208	static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
db72c2f8	209	{
f5f9d7bf MLC	210	/* Disable irq request generation for downlink */
	211	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	212	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL);
	213
	214	/* Disable DMA request generation for downlink */
	215	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
	216
	217	/* Disable irq request generation for uplink */
	218	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	219	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	220
	221	/* Disable DMA request generation for uplink */
	222	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
89b0d550 PU	223
	224	/* Disable RX1/2 offset cancellation */
	225	if (mcpdm->dn_rx_offset)
	226	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
f5f9d7bf MLC	227	}
	228
	229	static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
	230	{
	231	struct omap_mcpdm *mcpdm = dev_id;
	232	int irq_status;
	233
	234	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
	235
	236	/* Acknowledge irq event */
	237	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
	238
	239	if (irq_status & MCPDM_DN_IRQ_FULL)
	240	dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
	241
	242	if (irq_status & MCPDM_DN_IRQ_EMPTY)
	243	dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
	244
	245	if (irq_status & MCPDM_DN_IRQ)
	246	dev_dbg(mcpdm->dev, "DN (playback) write request\n");
	247
	248	if (irq_status & MCPDM_UP_IRQ_FULL)
	249	dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
	250
	251	if (irq_status & MCPDM_UP_IRQ_EMPTY)
	252	dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
	253
	254	if (irq_status & MCPDM_UP_IRQ)
	255	dev_dbg(mcpdm->dev, "UP (capture) write request\n");
	256
	257	return IRQ_HANDLED;
db72c2f8 MLC	258	}
db72c2f8 MLC	259
f5f9d7bf	260	static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
db72c2f8 MLC	261	struct snd_soc_dai *dai)
db72c2f8 MLC	262	{
f5f9d7bf	263	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	264
f5f9d7bf MLC	265	mutex_lock(&mcpdm->mutex);
	266
	267	if (!dai->active) {
f5f9d7bf MLC	268	/* Enable watch dog for ES above ES 1.0 to avoid saturation */
	269	if (omap_rev() != OMAP4430_REV_ES1_0) {
	270	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	271
	272	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL,
	273	ctrl \| MCPDM_WD_EN);
	274	}
	275	omap_mcpdm_open_streams(mcpdm);
db72c2f8 MLC	276	}
db72c2f8 MLC	277
f5f9d7bf MLC	278	mutex_unlock(&mcpdm->mutex);
	279
	280	return 0;
	281	}
	282
	283	static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
	284	struct snd_soc_dai *dai)
	285	{
	286	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	287
	288	mutex_lock(&mcpdm->mutex);
	289
	290	if (!dai->active) {
	291	if (omap_mcpdm_active(mcpdm)) {
	292	omap_mcpdm_stop(mcpdm);
	293	omap_mcpdm_close_streams(mcpdm);
	294	}
f5f9d7bf MLC	295	}
	296
	297	mutex_unlock(&mcpdm->mutex);
db72c2f8 MLC	298	}
	299
	300	static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
	301	struct snd_pcm_hw_params *params,
	302	struct snd_soc_dai *dai)
	303	{
f5f9d7bf	304	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	305	int stream = substream->stream;
f5f9d7bf MLC	306	struct omap_pcm_dma_data *dma_data;
	307	int channels;
	308	int link_mask = 0;
db72c2f8	309
db72c2f8 MLC	310	channels = params_channels(params);
db72c2f8 MLC	311	switch (channels) {
3b5b516f PU	312	case 5:
	313	if (stream == SNDRV_PCM_STREAM_CAPTURE)
	314	/* up to 3 channels for capture */
	315	return -EINVAL;
	316	link_mask \|= 1 << 4;
db72c2f8 MLC	317	case 4:
db72c2f8 MLC	318	if (stream == SNDRV_PCM_STREAM_CAPTURE)
3b5b516f	319	/* up to 3 channels for capture */
db72c2f8 MLC	320	return -EINVAL;
	321	link_mask \|= 1 << 3;
	322	case 3:
db72c2f8 MLC	323	link_mask \|= 1 << 2;
	324	case 2:
	325	link_mask \|= 1 << 1;
	326	case 1:
	327	link_mask \|= 1 << 0;
	328	break;
	329	default:
	330	/* unsupported number of channels */
	331	return -EINVAL;
	332	}
	333
b199adfd	334	dma_data = &omap_mcpdm_dai_dma_params[stream];
b199adfd	335
f5f9d7bf	336	/* Configure McPDM channels, and DMA packet size */
db72c2f8	337	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
f5f9d7bf MLC	338	mcpdm->dn_channels = link_mask << 3;
	339	dma_data->packet_size =
	340	(MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
db72c2f8	341	} else {
f5f9d7bf MLC	342	mcpdm->up_channels = link_mask << 0;
f5f9d7bf MLC	343	dma_data->packet_size = mcpdm->up_threshold * channels;
db72c2f8 MLC	344	}
db72c2f8 MLC	345
b199adfd	346	snd_soc_dai_set_dma_data(dai, substream, dma_data);
f5f9d7bf MLC	347
f5f9d7bf MLC	348	return 0;
db72c2f8 MLC	349	}
db72c2f8 MLC	350
f5f9d7bf	351	static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
db72c2f8 MLC	352	struct snd_soc_dai *dai)
db72c2f8 MLC	353	{
f5f9d7bf	354	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	355
f5f9d7bf MLC	356	if (!omap_mcpdm_active(mcpdm)) {
	357	omap_mcpdm_start(mcpdm);
	358	omap_mcpdm_reg_dump(mcpdm);
	359	}
db72c2f8	360
f5f9d7bf	361	return 0;
db72c2f8 MLC	362	}
db72c2f8 MLC	363
85e7652d	364	static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
db72c2f8 MLC	365	.startup = omap_mcpdm_dai_startup,
db72c2f8 MLC	366	.shutdown = omap_mcpdm_dai_shutdown,
db72c2f8	367	.hw_params = omap_mcpdm_dai_hw_params,
f5f9d7bf	368	.prepare = omap_mcpdm_prepare,
db72c2f8 MLC	369	};
db72c2f8 MLC	370
f5f9d7bf MLC	371	static int omap_mcpdm_probe(struct snd_soc_dai *dai)
	372	{
	373	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	374	int ret;
	375
	376	pm_runtime_enable(mcpdm->dev);
	377
	378	/* Disable lines while request is ongoing */
	379	pm_runtime_get_sync(mcpdm->dev);
	380	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
	381
	382	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
	383	0, "McPDM", (void *)mcpdm);
db72c2f8	384
f5f9d7bf MLC	385	pm_runtime_put_sync(mcpdm->dev);
	386
	387	if (ret) {
	388	dev_err(mcpdm->dev, "Request for IRQ failed\n");
	389	pm_runtime_disable(mcpdm->dev);
	390	}
	391
	392	/* Configure McPDM threshold values */
	393	mcpdm->dn_threshold = 2;
	394	mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
	395	return ret;
	396	}
	397
	398	static int omap_mcpdm_remove(struct snd_soc_dai *dai)
f0fba2ad	399	{
f5f9d7bf MLC	400	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	401
	402	free_irq(mcpdm->irq, (void *)mcpdm);
	403	pm_runtime_disable(mcpdm->dev);
	404
f0fba2ad LG	405	return 0;
	406	}
	407
f5f9d7bf MLC	408	#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	409	#define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
	410
f0fba2ad	411	static struct snd_soc_dai_driver omap_mcpdm_dai = {
f5f9d7bf MLC	412	.probe = omap_mcpdm_probe,
	413	.remove = omap_mcpdm_remove,
	414	.probe_order = SND_SOC_COMP_ORDER_LATE,
	415	.remove_order = SND_SOC_COMP_ORDER_EARLY,
db72c2f8 MLC	416	.playback = {
db72c2f8 MLC	417	.channels_min = 1,
3b5b516f	418	.channels_max = 5,
db72c2f8 MLC	419	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	420	.formats = OMAP_MCPDM_FORMATS,
b4badd49	421	.sig_bits = 24,
db72c2f8 MLC	422	},
	423	.capture = {
	424	.channels_min = 1,
3b5b516f	425	.channels_max = 3,
db72c2f8 MLC	426	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	427	.formats = OMAP_MCPDM_FORMATS,
b4badd49	428	.sig_bits = 24,
db72c2f8 MLC	429	},
db72c2f8 MLC	430	.ops = &omap_mcpdm_dai_ops,
db72c2f8	431	};
f0fba2ad	432
89b0d550 PU	433	void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
	434	u8 rx1, u8 rx2)
	435	{
	436	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
	437
	438	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) \| MCPDM_DNOFST_RX2(rx2);
	439	}
	440	EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
	441
f0fba2ad LG	442	static __devinit int asoc_mcpdm_probe(struct platform_device *pdev)
f0fba2ad LG	443	{
f5f9d7bf MLC	444	struct omap_mcpdm *mcpdm;
f5f9d7bf MLC	445	struct resource *res;
f5f9d7bf	446
d77ae332	447	mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
f5f9d7bf MLC	448	if (!mcpdm)
	449	return -ENOMEM;
	450
	451	platform_set_drvdata(pdev, mcpdm);
	452
	453	mutex_init(&mcpdm->mutex);
	454
	455	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d77ae332 PU	456	if (res == NULL)
d77ae332 PU	457	return -ENOMEM;
f5f9d7bf	458
d77ae332 PU	459	if (!devm_request_mem_region(&pdev->dev, res->start,
	460	resource_size(res), "McPDM"))
	461	return -EBUSY;
f5f9d7bf	462
d77ae332 PU	463	mcpdm->io_base = devm_ioremap(&pdev->dev, res->start,
	464	resource_size(res));
	465	if (!mcpdm->io_base)
	466	return -ENOMEM;
f5f9d7bf MLC	467
f5f9d7bf MLC	468	mcpdm->irq = platform_get_irq(pdev, 0);
d77ae332 PU	469	if (mcpdm->irq < 0)
d77ae332 PU	470	return mcpdm->irq;
f5f9d7bf MLC	471
f5f9d7bf MLC	472	mcpdm->dev = &pdev->dev;
f0fba2ad	473
d77ae332	474	return snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
f0fba2ad LG	475	}
	476
	477	static int __devexit asoc_mcpdm_remove(struct platform_device *pdev)
	478	{
	479	snd_soc_unregister_dai(&pdev->dev);
f0fba2ad LG	480	return 0;
	481	}
	482
7cb8a1b5 PU	483	static const struct of_device_id omap_mcpdm_of_match[] = {
	484	{ .compatible = "ti,omap4-mcpdm", },
	485	{ }
	486	};
	487	MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
	488
f0fba2ad LG	489	static struct platform_driver asoc_mcpdm_driver = {
f0fba2ad LG	490	.driver = {
f5f9d7bf MLC	491	.name = "omap-mcpdm",
f5f9d7bf MLC	492	.owner = THIS_MODULE,
7cb8a1b5	493	.of_match_table = omap_mcpdm_of_match,
f0fba2ad LG	494	},
f0fba2ad LG	495
f5f9d7bf MLC	496	.probe = asoc_mcpdm_probe,
f5f9d7bf MLC	497	.remove = __devexit_p(asoc_mcpdm_remove),
f0fba2ad	498	};
db72c2f8	499
beda5bf5	500	module_platform_driver(asoc_mcpdm_driver);
db72c2f8	501
d66a547c	502	MODULE_ALIAS("platform:omap-mcpdm");
f5f9d7bf	503	MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
db72c2f8 MLC	504	MODULE_DESCRIPTION("OMAP PDM SoC Interface");
db72c2f8 MLC	505	MODULE_LICENSE("GPL");