[deliverable/linux.git] / sound / soc / omap / omap-mcpdm.c

/*
 * omap-mcpdm.c  --  OMAP ALSA SoC DAI driver using McPDM port
 *
 * Copyright (C) 2009 - 2011 Texas Instruments
 *
 * Author: Misael Lopez Cruz <misael.lopez@ti.com>
 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
 *          Margarita Olaya <magi.olaya@ti.com>
 *          Peter Ujfalusi <peter.ujfalusi@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/of_device.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include <plat/dma.h>
#include <plat/omap_hwmod.h>
#include "omap-mcpdm.h"
#include "omap-pcm.h"

struct omap_mcpdm {
	struct device *dev;
	unsigned long phys_base;
	void __iomem *io_base;
	int irq;

	struct mutex mutex;

	/* channel data */
	u32 dn_channels;
	u32 up_channels;

	/* McPDM FIFO thresholds */
	u32 dn_threshold;
	u32 up_threshold;

	/* McPDM dn offsets for rx1, and 2 channels */
	u32 dn_rx_offset;
};

/*
 * Stream DMA parameters
 */
static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
	{
		.name = "Audio playback",
		.dma_req = OMAP44XX_DMA_MCPDM_DL,
		.data_type = OMAP_DMA_DATA_TYPE_S32,
		.sync_mode = OMAP_DMA_SYNC_PACKET,
		.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_DN_DATA,
	},
	{
		.name = "Audio capture",
		.dma_req = OMAP44XX_DMA_MCPDM_UP,
		.data_type = OMAP_DMA_DATA_TYPE_S32,
		.sync_mode = OMAP_DMA_SYNC_PACKET,
		.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_UP_DATA,
	},
};

static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
{
	__raw_writel(val, mcpdm->io_base + reg);
}

static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
{
	return __raw_readl(mcpdm->io_base + reg);
}

#ifdef DEBUG
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
{
	dev_dbg(mcpdm->dev, "***********************\n");
	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	dev_dbg(mcpdm->dev, "IRQSTATUS:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	dev_dbg(mcpdm->dev, "DMAWAKEEN:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	dev_dbg(mcpdm->dev, "CTRL:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	dev_dbg(mcpdm->dev, "***********************\n");
}
#else
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
#endif

/*
 * Enables the transfer through the PDM interface to/from the Phoenix
 * codec by enabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl |= mcpdm->dn_channels | mcpdm->up_channels;
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
}

/*
 * Disables the transfer through the PDM interface to/from the Phoenix
 * codec by disabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(mcpdm->dn_channels | mcpdm->up_channels);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

}

/*
 * Is the physical McPDM interface active.
 */
static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
{
	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
					(MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
}

/*
 * Configures McPDM uplink, and downlink for audio.
 * This function should be called before omap_mcpdm_start.
 */
static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
{
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Enable DN RX1/2 offset cancellation feature, if configured */
	if (mcpdm->dn_rx_offset) {
		u32 dn_offset = mcpdm->dn_rx_offset;

		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
		dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	}

	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);

	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
			MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
}

/*
 * Cleans McPDM uplink, and downlink configuration.
 * This function should be called when the stream is closed.
 */
static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
{
	/* Disable irq request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);

	/* Disable DMA request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);

	/* Disable irq request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Disable DMA request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);

	/* Disable RX1/2 offset cancellation */
	if (mcpdm->dn_rx_offset)
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
}

static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
{
	struct omap_mcpdm *mcpdm = dev_id;
	int irq_status;

	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);

	/* Acknowledge irq event */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);

	if (irq_status & MCPDM_DN_IRQ_FULL)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");

	if (irq_status & MCPDM_DN_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");

	if (irq_status & MCPDM_DN_IRQ)
		dev_dbg(mcpdm->dev, "DN (playback) write request\n");

	if (irq_status & MCPDM_UP_IRQ_FULL)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");

	if (irq_status & MCPDM_UP_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");

	if (irq_status & MCPDM_UP_IRQ)
		dev_dbg(mcpdm->dev, "UP (capture) write request\n");

	return IRQ_HANDLED;
}

static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		/* Enable watch dog for ES above ES 1.0 to avoid saturation */
		if (omap_rev() != OMAP4430_REV_ES1_0) {
			u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

			omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL,
					 ctrl | MCPDM_WD_EN);
		}
		omap_mcpdm_open_streams(mcpdm);
	}

	mutex_unlock(&mcpdm->mutex);

	return 0;
}

static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		if (omap_mcpdm_active(mcpdm)) {
			omap_mcpdm_stop(mcpdm);
			omap_mcpdm_close_streams(mcpdm);
		}
	}

	mutex_unlock(&mcpdm->mutex);
}

static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int stream = substream->stream;
	struct omap_pcm_dma_data *dma_data;
	int channels;
	int link_mask = 0;

	channels = params_channels(params);
	switch (channels) {
	case 5:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 4;
	case 4:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 3;
	case 3:
		link_mask |= 1 << 2;
	case 2:
		link_mask |= 1 << 1;
	case 1:
		link_mask |= 1 << 0;
		break;
	default:
		/* unsupported number of channels */
		return -EINVAL;
	}

	dma_data = &omap_mcpdm_dai_dma_params[stream];

	/* Configure McPDM channels, and DMA packet size */
	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		mcpdm->dn_channels = link_mask << 3;
		dma_data->packet_size =
			(MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
	} else {
		mcpdm->up_channels = link_mask << 0;
		dma_data->packet_size = mcpdm->up_threshold * channels;
	}

	snd_soc_dai_set_dma_data(dai, substream, dma_data);

	return 0;
}

static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	if (!omap_mcpdm_active(mcpdm)) {
		omap_mcpdm_start(mcpdm);
		omap_mcpdm_reg_dump(mcpdm);
	}

	return 0;
}

static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
	.startup	= omap_mcpdm_dai_startup,
	.shutdown	= omap_mcpdm_dai_shutdown,
	.hw_params	= omap_mcpdm_dai_hw_params,
	.prepare	= omap_mcpdm_prepare,
};

static int omap_mcpdm_probe(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int ret;

	pm_runtime_enable(mcpdm->dev);

	/* Disable lines while request is ongoing */
	pm_runtime_get_sync(mcpdm->dev);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);

	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
				0, "McPDM", (void *)mcpdm);

	pm_runtime_put_sync(mcpdm->dev);

	if (ret) {
		dev_err(mcpdm->dev, "Request for IRQ failed\n");
		pm_runtime_disable(mcpdm->dev);
	}

	/* Configure McPDM threshold values */
	mcpdm->dn_threshold = 2;
	mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
	return ret;
}

static int omap_mcpdm_remove(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	free_irq(mcpdm->irq, (void *)mcpdm);
	pm_runtime_disable(mcpdm->dev);

	return 0;
}

#define OMAP_MCPDM_RATES	(SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define OMAP_MCPDM_FORMATS	SNDRV_PCM_FMTBIT_S32_LE

static struct snd_soc_dai_driver omap_mcpdm_dai = {
	.probe = omap_mcpdm_probe,
	.remove = omap_mcpdm_remove,
	.probe_order = SND_SOC_COMP_ORDER_LATE,
	.remove_order = SND_SOC_COMP_ORDER_EARLY,
	.playback = {
		.channels_min = 1,
		.channels_max = 5,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.capture = {
		.channels_min = 1,
		.channels_max = 3,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.ops = &omap_mcpdm_dai_ops,
};

void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
				    u8 rx1, u8 rx2)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);

	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
}
EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);

static __devinit int asoc_mcpdm_probe(struct platform_device *pdev)
{
	struct omap_mcpdm *mcpdm;
	struct resource *res;
	int ret = 0;

	mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
	if (!mcpdm)
		return -ENOMEM;

	platform_set_drvdata(pdev, mcpdm);

	mutex_init(&mcpdm->mutex);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res == NULL) {
		dev_err(&pdev->dev, "no resource\n");
		goto err_res;
	}

	if (!request_mem_region(res->start, resource_size(res), "McPDM")) {
		ret = -EBUSY;
		goto err_res;
	}

	mcpdm->io_base = ioremap(res->start, resource_size(res));
	if (!mcpdm->io_base) {
		ret = -ENOMEM;
		goto err_iomap;
	}

	mcpdm->irq = platform_get_irq(pdev, 0);
	if (mcpdm->irq < 0) {
		ret = mcpdm->irq;
		goto err_irq;
	}

	mcpdm->dev = &pdev->dev;

	ret = snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
	if (!ret)
		return 0;

err_irq:
	iounmap(mcpdm->io_base);
err_iomap:
	release_mem_region(res->start, resource_size(res));
err_res:
	kfree(mcpdm);
	return ret;
}

static int __devexit asoc_mcpdm_remove(struct platform_device *pdev)
{
	struct omap_mcpdm *mcpdm = platform_get_drvdata(pdev);
	struct resource *res;

	snd_soc_unregister_dai(&pdev->dev);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	iounmap(mcpdm->io_base);
	release_mem_region(res->start, resource_size(res));

	kfree(mcpdm);
	return 0;
}

static const struct of_device_id omap_mcpdm_of_match[] = {
	{ .compatible = "ti,omap4-mcpdm", },
	{ }
};
MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);

static struct platform_driver asoc_mcpdm_driver = {
	.driver = {
		.name	= "omap-mcpdm",
		.owner	= THIS_MODULE,
		.of_match_table = omap_mcpdm_of_match,
	},

	.probe	= asoc_mcpdm_probe,
	.remove	= __devexit_p(asoc_mcpdm_remove),
};

module_platform_driver(asoc_mcpdm_driver);

MODULE_ALIAS("platform:omap-mcpdm");
MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
MODULE_DESCRIPTION("OMAP PDM SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
db72c2f8 MLC	1	/*
	2	* omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
	3	*
f5f9d7bf	4	* Copyright (C) 2009 - 2011 Texas Instruments
db72c2f8	5	*
f5f9d7bf	6	* Author: Misael Lopez Cruz <misael.lopez@ti.com>
db72c2f8 MLC	7	* Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
db72c2f8 MLC	8	* Margarita Olaya <magi.olaya@ti.com>
f5f9d7bf	9	* Peter Ujfalusi <peter.ujfalusi@ti.com>
db72c2f8 MLC	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License
	13	* version 2 as published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful, but
	16	* WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	23	* 02110-1301 USA
	24	*
	25	*/
	26
	27	#include <linux/init.h>
	28	#include <linux/module.h>
f5f9d7bf MLC	29	#include <linux/platform_device.h>
	30	#include <linux/interrupt.h>
	31	#include <linux/err.h>
	32	#include <linux/io.h>
	33	#include <linux/irq.h>
	34	#include <linux/slab.h>
	35	#include <linux/pm_runtime.h>
7cb8a1b5	36	#include <linux/of_device.h>
f5f9d7bf	37
db72c2f8 MLC	38	#include <sound/core.h>
	39	#include <sound/pcm.h>
	40	#include <sound/pcm_params.h>
db72c2f8 MLC	41	#include <sound/soc.h>
db72c2f8 MLC	42
db72c2f8	43	#include <plat/dma.h>
f5f9d7bf MLC	44	#include <plat/omap_hwmod.h>
f5f9d7bf MLC	45	#include "omap-mcpdm.h"
db72c2f8 MLC	46	#include "omap-pcm.h"
db72c2f8 MLC	47
f5f9d7bf MLC	48	struct omap_mcpdm {
	49	struct device *dev;
	50	unsigned long phys_base;
	51	void __iomem *io_base;
	52	int irq;
db72c2f8	53
f5f9d7bf MLC	54	struct mutex mutex;
	55
	56	/* channel data */
	57	u32 dn_channels;
	58	u32 up_channels;
db72c2f8	59
f5f9d7bf MLC	60	/* McPDM FIFO thresholds */
	61	u32 dn_threshold;
	62	u32 up_threshold;
89b0d550 PU	63
	64	/* McPDM dn offsets for rx1, and 2 channels */
	65	u32 dn_rx_offset;
db72c2f8 MLC	66	};
	67
	68	/*
	69	* Stream DMA parameters
	70	*/
	71	static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
	72	{
	73	.name = "Audio playback",
	74	.dma_req = OMAP44XX_DMA_MCPDM_DL,
	75	.data_type = OMAP_DMA_DATA_TYPE_S32,
	76	.sync_mode = OMAP_DMA_SYNC_PACKET,
f5f9d7bf	77	.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_DN_DATA,
db72c2f8 MLC	78	},
	79	{
	80	.name = "Audio capture",
	81	.dma_req = OMAP44XX_DMA_MCPDM_UP,
	82	.data_type = OMAP_DMA_DATA_TYPE_S32,
	83	.sync_mode = OMAP_DMA_SYNC_PACKET,
f5f9d7bf	84	.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_UP_DATA,
db72c2f8 MLC	85	},
	86	};
	87
f5f9d7bf	88	static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
db72c2f8	89	{
f5f9d7bf MLC	90	__raw_writel(val, mcpdm->io_base + reg);
f5f9d7bf MLC	91	}
db72c2f8	92
f5f9d7bf MLC	93	static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
	94	{
	95	return __raw_readl(mcpdm->io_base + reg);
	96	}
db72c2f8	97
f5f9d7bf MLC	98	#ifdef DEBUG
	99	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
	100	{
	101	dev_dbg(mcpdm->dev, "***********************\n");
	102	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
	103	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	104	dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
	105	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	106	dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
	107	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	108	dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
	109	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	110	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
	111	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	112	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
	113	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	114	dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
	115	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	116	dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
	117	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	118	dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
	119	omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	120	dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
	121	omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	122	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
	123	omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	124	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
	125	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	126	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
	127	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	128	dev_dbg(mcpdm->dev, "***********************\n");
db72c2f8	129	}
f5f9d7bf MLC	130	#else
	131	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
	132	#endif
db72c2f8	133
f5f9d7bf MLC	134	/*
	135	* Enables the transfer through the PDM interface to/from the Phoenix
	136	* codec by enabling the corresponding UP or DN channels.
	137	*/
	138	static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
	139	{
	140	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	141
	142	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	143	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	144
	145	ctrl \|= mcpdm->dn_channels \| mcpdm->up_channels;
	146	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	147
	148	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	149	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	150	}
	151
	152	/*
	153	* Disables the transfer through the PDM interface to/from the Phoenix
	154	* codec by disabling the corresponding UP or DN channels.
	155	*/
	156	static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
	157	{
	158	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	159
	160	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	161	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	162
	163	ctrl &= ~(mcpdm->dn_channels \| mcpdm->up_channels);
	164	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	165
	166	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	167	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	168
	169	}
	170
	171	/*
	172	* Is the physical McPDM interface active.
	173	*/
	174	static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
	175	{
	176	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
	177	(MCPDM_PDM_DN_MASK \| MCPDM_PDM_UP_MASK);
	178	}
	179
	180	/*
	181	* Configures McPDM uplink, and downlink for audio.
	182	* This function should be called before omap_mcpdm_start.
	183	*/
	184	static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
	185	{
	186	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
	187	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL \|
	188	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	189
89b0d550 PU	190	/* Enable DN RX1/2 offset cancellation feature, if configured */
	191	if (mcpdm->dn_rx_offset) {
	192	u32 dn_offset = mcpdm->dn_rx_offset;
	193
	194	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	195	dn_offset \|= (MCPDM_DN_OFST_RX1_EN \| MCPDM_DN_OFST_RX2_EN);
	196	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	197	}
	198
f5f9d7bf MLC	199	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
	200	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);
	201
	202	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
	203	MCPDM_DMA_DN_ENABLE \| MCPDM_DMA_UP_ENABLE);
	204	}
	205
	206	/*
	207	* Cleans McPDM uplink, and downlink configuration.
	208	* This function should be called when the stream is closed.
	209	*/
	210	static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
db72c2f8	211	{
f5f9d7bf MLC	212	/* Disable irq request generation for downlink */
	213	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	214	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL);
	215
	216	/* Disable DMA request generation for downlink */
	217	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
	218
	219	/* Disable irq request generation for uplink */
	220	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	221	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	222
	223	/* Disable DMA request generation for uplink */
	224	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
89b0d550 PU	225
	226	/* Disable RX1/2 offset cancellation */
	227	if (mcpdm->dn_rx_offset)
	228	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
f5f9d7bf MLC	229	}
	230
	231	static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
	232	{
	233	struct omap_mcpdm *mcpdm = dev_id;
	234	int irq_status;
	235
	236	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
	237
	238	/* Acknowledge irq event */
	239	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
	240
	241	if (irq_status & MCPDM_DN_IRQ_FULL)
	242	dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
	243
	244	if (irq_status & MCPDM_DN_IRQ_EMPTY)
	245	dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
	246
	247	if (irq_status & MCPDM_DN_IRQ)
	248	dev_dbg(mcpdm->dev, "DN (playback) write request\n");
	249
	250	if (irq_status & MCPDM_UP_IRQ_FULL)
	251	dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
	252
	253	if (irq_status & MCPDM_UP_IRQ_EMPTY)
	254	dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
	255
	256	if (irq_status & MCPDM_UP_IRQ)
	257	dev_dbg(mcpdm->dev, "UP (capture) write request\n");
	258
	259	return IRQ_HANDLED;
db72c2f8 MLC	260	}
db72c2f8 MLC	261
f5f9d7bf	262	static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
db72c2f8 MLC	263	struct snd_soc_dai *dai)
db72c2f8 MLC	264	{
f5f9d7bf	265	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	266
f5f9d7bf MLC	267	mutex_lock(&mcpdm->mutex);
	268
	269	if (!dai->active) {
f5f9d7bf MLC	270	/* Enable watch dog for ES above ES 1.0 to avoid saturation */
	271	if (omap_rev() != OMAP4430_REV_ES1_0) {
	272	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	273
	274	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL,
	275	ctrl \| MCPDM_WD_EN);
	276	}
	277	omap_mcpdm_open_streams(mcpdm);
db72c2f8 MLC	278	}
db72c2f8 MLC	279
f5f9d7bf MLC	280	mutex_unlock(&mcpdm->mutex);
	281
	282	return 0;
	283	}
	284
	285	static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
	286	struct snd_soc_dai *dai)
	287	{
	288	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	289
	290	mutex_lock(&mcpdm->mutex);
	291
	292	if (!dai->active) {
	293	if (omap_mcpdm_active(mcpdm)) {
	294	omap_mcpdm_stop(mcpdm);
	295	omap_mcpdm_close_streams(mcpdm);
	296	}
f5f9d7bf MLC	297	}
	298
	299	mutex_unlock(&mcpdm->mutex);
db72c2f8 MLC	300	}
	301
	302	static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
	303	struct snd_pcm_hw_params *params,
	304	struct snd_soc_dai *dai)
	305	{
f5f9d7bf	306	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	307	int stream = substream->stream;
f5f9d7bf MLC	308	struct omap_pcm_dma_data *dma_data;
	309	int channels;
	310	int link_mask = 0;
db72c2f8	311
db72c2f8 MLC	312	channels = params_channels(params);
db72c2f8 MLC	313	switch (channels) {
3b5b516f PU	314	case 5:
	315	if (stream == SNDRV_PCM_STREAM_CAPTURE)
	316	/* up to 3 channels for capture */
	317	return -EINVAL;
	318	link_mask \|= 1 << 4;
db72c2f8 MLC	319	case 4:
db72c2f8 MLC	320	if (stream == SNDRV_PCM_STREAM_CAPTURE)
3b5b516f	321	/* up to 3 channels for capture */
db72c2f8 MLC	322	return -EINVAL;
	323	link_mask \|= 1 << 3;
	324	case 3:
db72c2f8 MLC	325	link_mask \|= 1 << 2;
	326	case 2:
	327	link_mask \|= 1 << 1;
	328	case 1:
	329	link_mask \|= 1 << 0;
	330	break;
	331	default:
	332	/* unsupported number of channels */
	333	return -EINVAL;
	334	}
	335
b199adfd	336	dma_data = &omap_mcpdm_dai_dma_params[stream];
b199adfd	337
f5f9d7bf	338	/* Configure McPDM channels, and DMA packet size */
db72c2f8	339	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
f5f9d7bf MLC	340	mcpdm->dn_channels = link_mask << 3;
	341	dma_data->packet_size =
	342	(MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
db72c2f8	343	} else {
f5f9d7bf MLC	344	mcpdm->up_channels = link_mask << 0;
f5f9d7bf MLC	345	dma_data->packet_size = mcpdm->up_threshold * channels;
db72c2f8 MLC	346	}
db72c2f8 MLC	347
b199adfd	348	snd_soc_dai_set_dma_data(dai, substream, dma_data);
f5f9d7bf MLC	349
f5f9d7bf MLC	350	return 0;
db72c2f8 MLC	351	}
db72c2f8 MLC	352
f5f9d7bf	353	static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
db72c2f8 MLC	354	struct snd_soc_dai *dai)
db72c2f8 MLC	355	{
f5f9d7bf	356	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	357
f5f9d7bf MLC	358	if (!omap_mcpdm_active(mcpdm)) {
	359	omap_mcpdm_start(mcpdm);
	360	omap_mcpdm_reg_dump(mcpdm);
	361	}
db72c2f8	362
f5f9d7bf	363	return 0;
db72c2f8 MLC	364	}
db72c2f8 MLC	365
85e7652d	366	static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
db72c2f8 MLC	367	.startup = omap_mcpdm_dai_startup,
db72c2f8 MLC	368	.shutdown = omap_mcpdm_dai_shutdown,
db72c2f8	369	.hw_params = omap_mcpdm_dai_hw_params,
f5f9d7bf	370	.prepare = omap_mcpdm_prepare,
db72c2f8 MLC	371	};
db72c2f8 MLC	372
f5f9d7bf MLC	373	static int omap_mcpdm_probe(struct snd_soc_dai *dai)
	374	{
	375	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	376	int ret;
	377
	378	pm_runtime_enable(mcpdm->dev);
	379
	380	/* Disable lines while request is ongoing */
	381	pm_runtime_get_sync(mcpdm->dev);
	382	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
	383
	384	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
	385	0, "McPDM", (void *)mcpdm);
db72c2f8	386
f5f9d7bf MLC	387	pm_runtime_put_sync(mcpdm->dev);
	388
	389	if (ret) {
	390	dev_err(mcpdm->dev, "Request for IRQ failed\n");
	391	pm_runtime_disable(mcpdm->dev);
	392	}
	393
	394	/* Configure McPDM threshold values */
	395	mcpdm->dn_threshold = 2;
	396	mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
	397	return ret;
	398	}
	399
	400	static int omap_mcpdm_remove(struct snd_soc_dai *dai)
f0fba2ad	401	{
f5f9d7bf MLC	402	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	403
	404	free_irq(mcpdm->irq, (void *)mcpdm);
	405	pm_runtime_disable(mcpdm->dev);
	406
f0fba2ad LG	407	return 0;
	408	}
	409
f5f9d7bf MLC	410	#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	411	#define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
	412
f0fba2ad	413	static struct snd_soc_dai_driver omap_mcpdm_dai = {
f5f9d7bf MLC	414	.probe = omap_mcpdm_probe,
	415	.remove = omap_mcpdm_remove,
	416	.probe_order = SND_SOC_COMP_ORDER_LATE,
	417	.remove_order = SND_SOC_COMP_ORDER_EARLY,
db72c2f8 MLC	418	.playback = {
db72c2f8 MLC	419	.channels_min = 1,
3b5b516f	420	.channels_max = 5,
db72c2f8 MLC	421	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	422	.formats = OMAP_MCPDM_FORMATS,
b4badd49	423	.sig_bits = 24,
db72c2f8 MLC	424	},
	425	.capture = {
	426	.channels_min = 1,
3b5b516f	427	.channels_max = 3,
db72c2f8 MLC	428	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	429	.formats = OMAP_MCPDM_FORMATS,
b4badd49	430	.sig_bits = 24,
db72c2f8 MLC	431	},
db72c2f8 MLC	432	.ops = &omap_mcpdm_dai_ops,
db72c2f8	433	};
f0fba2ad	434
89b0d550 PU	435	void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
	436	u8 rx1, u8 rx2)
	437	{
	438	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
	439
	440	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) \| MCPDM_DNOFST_RX2(rx2);
	441	}
	442	EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
	443
f0fba2ad LG	444	static __devinit int asoc_mcpdm_probe(struct platform_device *pdev)
f0fba2ad LG	445	{
f5f9d7bf MLC	446	struct omap_mcpdm *mcpdm;
	447	struct resource *res;
	448	int ret = 0;
	449
	450	mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
	451	if (!mcpdm)
	452	return -ENOMEM;
	453
	454	platform_set_drvdata(pdev, mcpdm);
	455
	456	mutex_init(&mcpdm->mutex);
	457
	458	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	459	if (res == NULL) {
	460	dev_err(&pdev->dev, "no resource\n");
	461	goto err_res;
	462	}
	463
	464	if (!request_mem_region(res->start, resource_size(res), "McPDM")) {
	465	ret = -EBUSY;
	466	goto err_res;
	467	}
	468
	469	mcpdm->io_base = ioremap(res->start, resource_size(res));
	470	if (!mcpdm->io_base) {
	471	ret = -ENOMEM;
	472	goto err_iomap;
	473	}
	474
	475	mcpdm->irq = platform_get_irq(pdev, 0);
	476	if (mcpdm->irq < 0) {
	477	ret = mcpdm->irq;
	478	goto err_irq;
	479	}
	480
	481	mcpdm->dev = &pdev->dev;
f0fba2ad	482
f0fba2ad	483	ret = snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
f5f9d7bf MLC	484	if (!ret)
	485	return 0;
	486
	487	err_irq:
	488	iounmap(mcpdm->io_base);
	489	err_iomap:
	490	release_mem_region(res->start, resource_size(res));
	491	err_res:
	492	kfree(mcpdm);
f0fba2ad LG	493	return ret;
	494	}
	495
	496	static int __devexit asoc_mcpdm_remove(struct platform_device *pdev)
	497	{
f5f9d7bf MLC	498	struct omap_mcpdm *mcpdm = platform_get_drvdata(pdev);
	499	struct resource *res;
	500
f0fba2ad	501	snd_soc_unregister_dai(&pdev->dev);
f5f9d7bf MLC	502
	503	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	504	iounmap(mcpdm->io_base);
	505	release_mem_region(res->start, resource_size(res));
	506
	507	kfree(mcpdm);
f0fba2ad LG	508	return 0;
	509	}
	510
7cb8a1b5 PU	511	static const struct of_device_id omap_mcpdm_of_match[] = {
	512	{ .compatible = "ti,omap4-mcpdm", },
	513	{ }
	514	};
	515	MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
	516
f0fba2ad LG	517	static struct platform_driver asoc_mcpdm_driver = {
f0fba2ad LG	518	.driver = {
f5f9d7bf MLC	519	.name = "omap-mcpdm",
f5f9d7bf MLC	520	.owner = THIS_MODULE,
7cb8a1b5	521	.of_match_table = omap_mcpdm_of_match,
f0fba2ad LG	522	},
f0fba2ad LG	523
f5f9d7bf MLC	524	.probe = asoc_mcpdm_probe,
f5f9d7bf MLC	525	.remove = __devexit_p(asoc_mcpdm_remove),
f0fba2ad	526	};
db72c2f8	527
beda5bf5	528	module_platform_driver(asoc_mcpdm_driver);
db72c2f8	529
d66a547c	530	MODULE_ALIAS("platform:omap-mcpdm");
f5f9d7bf	531	MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
db72c2f8 MLC	532	MODULE_DESCRIPTION("OMAP PDM SoC Interface");
db72c2f8 MLC	533	MODULE_LICENSE("GPL");