[deliverable/linux.git] / sound / soc / omap / omap-mcpdm.c

/*
 * omap-mcpdm.c  --  OMAP ALSA SoC DAI driver using McPDM port
 *
 * Copyright (C) 2009 - 2011 Texas Instruments
 *
 * Author: Misael Lopez Cruz <misael.lopez@ti.com>
 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
 *          Margarita Olaya <magi.olaya@ti.com>
 *          Peter Ujfalusi <peter.ujfalusi@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include <plat/dma.h>
#include <plat/omap_hwmod.h>
#include "omap-mcpdm.h"
#include "omap-pcm.h"

struct omap_mcpdm {
	struct device *dev;
	unsigned long phys_base;
	void __iomem *io_base;
	int irq;

	struct mutex mutex;

	/* channel data */
	u32 dn_channels;
	u32 up_channels;

	/* McPDM FIFO thresholds */
	u32 dn_threshold;
	u32 up_threshold;
};

/*
 * Stream DMA parameters
 */
static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
	{
		.name = "Audio playback",
		.dma_req = OMAP44XX_DMA_MCPDM_DL,
		.data_type = OMAP_DMA_DATA_TYPE_S32,
		.sync_mode = OMAP_DMA_SYNC_PACKET,
		.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_DN_DATA,
	},
	{
		.name = "Audio capture",
		.dma_req = OMAP44XX_DMA_MCPDM_UP,
		.data_type = OMAP_DMA_DATA_TYPE_S32,
		.sync_mode = OMAP_DMA_SYNC_PACKET,
		.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_UP_DATA,
	},
};

static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
{
	__raw_writel(val, mcpdm->io_base + reg);
}

static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
{
	return __raw_readl(mcpdm->io_base + reg);
}

#ifdef DEBUG
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
{
	dev_dbg(mcpdm->dev, "***********************\n");
	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	dev_dbg(mcpdm->dev, "IRQSTATUS:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	dev_dbg(mcpdm->dev, "DMAWAKEEN:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	dev_dbg(mcpdm->dev, "CTRL:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	dev_dbg(mcpdm->dev, "***********************\n");
}
#else
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
#endif

/*
 * Enables the transfer through the PDM interface to/from the Phoenix
 * codec by enabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl |= mcpdm->dn_channels | mcpdm->up_channels;
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
}

/*
 * Disables the transfer through the PDM interface to/from the Phoenix
 * codec by disabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(mcpdm->dn_channels | mcpdm->up_channels);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

}

/*
 * Is the physical McPDM interface active.
 */
static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
{
	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
					(MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
}

/*
 * Configures McPDM uplink, and downlink for audio.
 * This function should be called before omap_mcpdm_start.
 */
static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
{
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);

	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
			MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
}

/*
 * Cleans McPDM uplink, and downlink configuration.
 * This function should be called when the stream is closed.
 */
static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
{
	/* Disable irq request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);

	/* Disable DMA request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);

	/* Disable irq request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Disable DMA request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
}

static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
{
	struct omap_mcpdm *mcpdm = dev_id;
	int irq_status;

	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);

	/* Acknowledge irq event */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);

	if (irq_status & MCPDM_DN_IRQ_FULL)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");

	if (irq_status & MCPDM_DN_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");

	if (irq_status & MCPDM_DN_IRQ)
		dev_dbg(mcpdm->dev, "DN (playback) write request\n");

	if (irq_status & MCPDM_UP_IRQ_FULL)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");

	if (irq_status & MCPDM_UP_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");

	if (irq_status & MCPDM_UP_IRQ)
		dev_dbg(mcpdm->dev, "UP (capture) write request\n");

	return IRQ_HANDLED;
}

static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		pm_runtime_get_sync(mcpdm->dev);

		/* Enable watch dog for ES above ES 1.0 to avoid saturation */
		if (omap_rev() != OMAP4430_REV_ES1_0) {
			u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

			omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL,
					 ctrl | MCPDM_WD_EN);
		}
		omap_mcpdm_open_streams(mcpdm);
	}

	mutex_unlock(&mcpdm->mutex);

	return 0;
}

static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		if (omap_mcpdm_active(mcpdm)) {
			omap_mcpdm_stop(mcpdm);
			omap_mcpdm_close_streams(mcpdm);
		}

		if (!omap_mcpdm_active(mcpdm))
			pm_runtime_put_sync(mcpdm->dev);
	}

	mutex_unlock(&mcpdm->mutex);
}

static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int stream = substream->stream;
	struct omap_pcm_dma_data *dma_data;
	int channels;
	int link_mask = 0;

	channels = params_channels(params);
	switch (channels) {
	case 4:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 2 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 3;
	case 3:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 2 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 2;
	case 2:
		link_mask |= 1 << 1;
	case 1:
		link_mask |= 1 << 0;
		break;
	default:
		/* unsupported number of channels */
		return -EINVAL;
	}

	dma_data = &omap_mcpdm_dai_dma_params[stream];

	/* Configure McPDM channels, and DMA packet size */
	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		mcpdm->dn_channels = link_mask << 3;
		dma_data->packet_size =
			(MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
	} else {
		mcpdm->up_channels = link_mask << 0;
		dma_data->packet_size = mcpdm->up_threshold * channels;
	}

	snd_soc_dai_set_dma_data(dai, substream, dma_data);

	return 0;
}

static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	if (!omap_mcpdm_active(mcpdm)) {
		omap_mcpdm_start(mcpdm);
		omap_mcpdm_reg_dump(mcpdm);
	}

	return 0;
}

static struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
	.startup	= omap_mcpdm_dai_startup,
	.shutdown	= omap_mcpdm_dai_shutdown,
	.hw_params	= omap_mcpdm_dai_hw_params,
	.prepare	= omap_mcpdm_prepare,
};

static int omap_mcpdm_probe(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int ret;

	pm_runtime_enable(mcpdm->dev);

	/* Disable lines while request is ongoing */
	pm_runtime_get_sync(mcpdm->dev);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);

	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
				0, "McPDM", (void *)mcpdm);

	pm_runtime_put_sync(mcpdm->dev);

	if (ret) {
		dev_err(mcpdm->dev, "Request for IRQ failed\n");
		pm_runtime_disable(mcpdm->dev);
	}

	/* Configure McPDM threshold values */
	mcpdm->dn_threshold = 2;
	mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
	return ret;
}

static int omap_mcpdm_remove(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	free_irq(mcpdm->irq, (void *)mcpdm);
	pm_runtime_disable(mcpdm->dev);

	return 0;
}

#define OMAP_MCPDM_RATES	(SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define OMAP_MCPDM_FORMATS	SNDRV_PCM_FMTBIT_S32_LE

static struct snd_soc_dai_driver omap_mcpdm_dai = {
	.probe = omap_mcpdm_probe,
	.remove = omap_mcpdm_remove,
	.probe_order = SND_SOC_COMP_ORDER_LATE,
	.remove_order = SND_SOC_COMP_ORDER_EARLY,
	.playback = {
		.channels_min = 1,
		.channels_max = 4,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
	},
	.capture = {
		.channels_min = 1,
		.channels_max = 2,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
	},
	.ops = &omap_mcpdm_dai_ops,
};

static __devinit int asoc_mcpdm_probe(struct platform_device *pdev)
{
	struct omap_mcpdm *mcpdm;
	struct resource *res;
	int ret = 0;

	mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
	if (!mcpdm)
		return -ENOMEM;

	platform_set_drvdata(pdev, mcpdm);

	mutex_init(&mcpdm->mutex);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res == NULL) {
		dev_err(&pdev->dev, "no resource\n");
		goto err_res;
	}

	if (!request_mem_region(res->start, resource_size(res), "McPDM")) {
		ret = -EBUSY;
		goto err_res;
	}

	mcpdm->io_base = ioremap(res->start, resource_size(res));
	if (!mcpdm->io_base) {
		ret = -ENOMEM;
		goto err_iomap;
	}

	mcpdm->irq = platform_get_irq(pdev, 0);
	if (mcpdm->irq < 0) {
		ret = mcpdm->irq;
		goto err_irq;
	}

	mcpdm->dev = &pdev->dev;

	ret = snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
	if (!ret)
		return 0;

err_irq:
	iounmap(mcpdm->io_base);
err_iomap:
	release_mem_region(res->start, resource_size(res));
err_res:
	kfree(mcpdm);
	return ret;
}

static int __devexit asoc_mcpdm_remove(struct platform_device *pdev)
{
	struct omap_mcpdm *mcpdm = platform_get_drvdata(pdev);
	struct resource *res;

	snd_soc_unregister_dai(&pdev->dev);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	iounmap(mcpdm->io_base);
	release_mem_region(res->start, resource_size(res));

	kfree(mcpdm);
	return 0;
}

static struct platform_driver asoc_mcpdm_driver = {
	.driver = {
		.name	= "omap-mcpdm",
		.owner	= THIS_MODULE,
	},

	.probe	= asoc_mcpdm_probe,
	.remove	= __devexit_p(asoc_mcpdm_remove),
};

static int __init snd_omap_mcpdm_init(void)
{
	return platform_driver_register(&asoc_mcpdm_driver);
}
module_init(snd_omap_mcpdm_init);

static void __exit snd_omap_mcpdm_exit(void)
{
	platform_driver_unregister(&asoc_mcpdm_driver);
}
module_exit(snd_omap_mcpdm_exit);

MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
MODULE_DESCRIPTION("OMAP PDM SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
db72c2f8 MLC	1	/*
	2	* omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
	3	*
f5f9d7bf	4	* Copyright (C) 2009 - 2011 Texas Instruments
db72c2f8	5	*
f5f9d7bf	6	* Author: Misael Lopez Cruz <misael.lopez@ti.com>
db72c2f8 MLC	7	* Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
db72c2f8 MLC	8	* Margarita Olaya <magi.olaya@ti.com>
f5f9d7bf	9	* Peter Ujfalusi <peter.ujfalusi@ti.com>
db72c2f8 MLC	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License
	13	* version 2 as published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful, but
	16	* WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	23	* 02110-1301 USA
	24	*
	25	*/
	26
	27	#include <linux/init.h>
	28	#include <linux/module.h>
f5f9d7bf MLC	29	#include <linux/platform_device.h>
	30	#include <linux/interrupt.h>
	31	#include <linux/err.h>
	32	#include <linux/io.h>
	33	#include <linux/irq.h>
	34	#include <linux/slab.h>
	35	#include <linux/pm_runtime.h>
	36
db72c2f8 MLC	37	#include <sound/core.h>
	38	#include <sound/pcm.h>
	39	#include <sound/pcm_params.h>
db72c2f8 MLC	40	#include <sound/soc.h>
db72c2f8 MLC	41
db72c2f8	42	#include <plat/dma.h>
f5f9d7bf MLC	43	#include <plat/omap_hwmod.h>
f5f9d7bf MLC	44	#include "omap-mcpdm.h"
db72c2f8 MLC	45	#include "omap-pcm.h"
db72c2f8 MLC	46
f5f9d7bf MLC	47	struct omap_mcpdm {
	48	struct device *dev;
	49	unsigned long phys_base;
	50	void __iomem *io_base;
	51	int irq;
db72c2f8	52
f5f9d7bf MLC	53	struct mutex mutex;
	54
	55	/* channel data */
	56	u32 dn_channels;
	57	u32 up_channels;
db72c2f8	58
f5f9d7bf MLC	59	/* McPDM FIFO thresholds */
	60	u32 dn_threshold;
	61	u32 up_threshold;
db72c2f8 MLC	62	};
	63
	64	/*
	65	* Stream DMA parameters
	66	*/
	67	static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
	68	{
	69	.name = "Audio playback",
	70	.dma_req = OMAP44XX_DMA_MCPDM_DL,
	71	.data_type = OMAP_DMA_DATA_TYPE_S32,
	72	.sync_mode = OMAP_DMA_SYNC_PACKET,
f5f9d7bf	73	.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_DN_DATA,
db72c2f8 MLC	74	},
	75	{
	76	.name = "Audio capture",
	77	.dma_req = OMAP44XX_DMA_MCPDM_UP,
	78	.data_type = OMAP_DMA_DATA_TYPE_S32,
	79	.sync_mode = OMAP_DMA_SYNC_PACKET,
f5f9d7bf	80	.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_UP_DATA,
db72c2f8 MLC	81	},
	82	};
	83
f5f9d7bf	84	static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
db72c2f8	85	{
f5f9d7bf MLC	86	__raw_writel(val, mcpdm->io_base + reg);
f5f9d7bf MLC	87	}
db72c2f8	88
f5f9d7bf MLC	89	static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
	90	{
	91	return __raw_readl(mcpdm->io_base + reg);
	92	}
db72c2f8	93
f5f9d7bf MLC	94	#ifdef DEBUG
	95	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
	96	{
	97	dev_dbg(mcpdm->dev, "***********************\n");
	98	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
	99	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	100	dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
	101	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	102	dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
	103	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	104	dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
	105	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	106	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
	107	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	108	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
	109	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	110	dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
	111	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	112	dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
	113	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	114	dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
	115	omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	116	dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
	117	omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	118	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
	119	omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	120	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
	121	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	122	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
	123	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	124	dev_dbg(mcpdm->dev, "***********************\n");
db72c2f8	125	}
f5f9d7bf MLC	126	#else
	127	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
	128	#endif
db72c2f8	129
f5f9d7bf MLC	130	/*
	131	* Enables the transfer through the PDM interface to/from the Phoenix
	132	* codec by enabling the corresponding UP or DN channels.
	133	*/
	134	static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
	135	{
	136	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	137
	138	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	139	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	140
	141	ctrl \|= mcpdm->dn_channels \| mcpdm->up_channels;
	142	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	143
	144	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	145	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	146	}
	147
	148	/*
	149	* Disables the transfer through the PDM interface to/from the Phoenix
	150	* codec by disabling the corresponding UP or DN channels.
	151	*/
	152	static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
	153	{
	154	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	155
	156	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	157	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	158
	159	ctrl &= ~(mcpdm->dn_channels \| mcpdm->up_channels);
	160	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	161
	162	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	163	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	164
	165	}
	166
	167	/*
	168	* Is the physical McPDM interface active.
	169	*/
	170	static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
	171	{
	172	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
	173	(MCPDM_PDM_DN_MASK \| MCPDM_PDM_UP_MASK);
	174	}
	175
	176	/*
	177	* Configures McPDM uplink, and downlink for audio.
	178	* This function should be called before omap_mcpdm_start.
	179	*/
	180	static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
	181	{
	182	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
	183	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL \|
	184	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	185
	186	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
	187	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);
	188
	189	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
	190	MCPDM_DMA_DN_ENABLE \| MCPDM_DMA_UP_ENABLE);
	191	}
	192
	193	/*
194	* Cleans McPDM uplink, and downlink configuration.
195	* This function should be called when the stream is closed.
196	*/
197	static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
db72c2f8	198	{
f5f9d7bf MLC	199	/* Disable irq request generation for downlink */
	200	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	201	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL);
	202
	203	/* Disable DMA request generation for downlink */
	204	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
	205
	206	/* Disable irq request generation for uplink */
	207	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	208	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	209
	210	/* Disable DMA request generation for uplink */
	211	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
	212	}
	213
	214	static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
	215	{
	216	struct omap_mcpdm *mcpdm = dev_id;
	217	int irq_status;
	218
	219	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
	220
	221	/* Acknowledge irq event */
	222	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
	223
	224	if (irq_status & MCPDM_DN_IRQ_FULL)
	225	dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
	226
	227	if (irq_status & MCPDM_DN_IRQ_EMPTY)
	228	dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
	229
	230	if (irq_status & MCPDM_DN_IRQ)
	231	dev_dbg(mcpdm->dev, "DN (playback) write request\n");
	232
	233	if (irq_status & MCPDM_UP_IRQ_FULL)
	234	dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
	235
	236	if (irq_status & MCPDM_UP_IRQ_EMPTY)
	237	dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
	238
	239	if (irq_status & MCPDM_UP_IRQ)
	240	dev_dbg(mcpdm->dev, "UP (capture) write request\n");
	241
	242	return IRQ_HANDLED;
db72c2f8 MLC	243	}
db72c2f8 MLC	244
f5f9d7bf	245	static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
db72c2f8 MLC	246	struct snd_soc_dai *dai)
db72c2f8 MLC	247	{
f5f9d7bf	248	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	249
f5f9d7bf MLC	250	mutex_lock(&mcpdm->mutex);
	251
	252	if (!dai->active) {
	253	pm_runtime_get_sync(mcpdm->dev);
	254
	255	/* Enable watch dog for ES above ES 1.0 to avoid saturation */
	256	if (omap_rev() != OMAP4430_REV_ES1_0) {
	257	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	258
	259	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL,
	260	ctrl \| MCPDM_WD_EN);
	261	}
	262	omap_mcpdm_open_streams(mcpdm);
db72c2f8 MLC	263	}
db72c2f8 MLC	264
f5f9d7bf MLC	265	mutex_unlock(&mcpdm->mutex);
	266
	267	return 0;
	268	}
	269
	270	static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
	271	struct snd_soc_dai *dai)
	272	{
	273	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	274
	275	mutex_lock(&mcpdm->mutex);
	276
	277	if (!dai->active) {
	278	if (omap_mcpdm_active(mcpdm)) {
	279	omap_mcpdm_stop(mcpdm);
	280	omap_mcpdm_close_streams(mcpdm);
	281	}
	282
	283	if (!omap_mcpdm_active(mcpdm))
	284	pm_runtime_put_sync(mcpdm->dev);
	285	}
	286
	287	mutex_unlock(&mcpdm->mutex);
db72c2f8 MLC	288	}
	289
	290	static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
	291	struct snd_pcm_hw_params *params,
	292	struct snd_soc_dai *dai)
	293	{
f5f9d7bf	294	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	295	int stream = substream->stream;
f5f9d7bf MLC	296	struct omap_pcm_dma_data *dma_data;
	297	int channels;
	298	int link_mask = 0;
db72c2f8	299
db72c2f8 MLC	300	channels = params_channels(params);
	301	switch (channels) {
	302	case 4:
	303	if (stream == SNDRV_PCM_STREAM_CAPTURE)
	304	/* up to 2 channels for capture */
	305	return -EINVAL;
	306	link_mask \|= 1 << 3;
	307	case 3:
	308	if (stream == SNDRV_PCM_STREAM_CAPTURE)
	309	/* up to 2 channels for capture */
	310	return -EINVAL;
	311	link_mask \|= 1 << 2;
	312	case 2:
	313	link_mask \|= 1 << 1;
	314	case 1:
	315	link_mask \|= 1 << 0;
	316	break;
	317	default:
	318	/* unsupported number of channels */
	319	return -EINVAL;
	320	}
	321
b199adfd	322	dma_data = &omap_mcpdm_dai_dma_params[stream];
b199adfd	323
f5f9d7bf	324	/* Configure McPDM channels, and DMA packet size */
db72c2f8	325	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
f5f9d7bf MLC	326	mcpdm->dn_channels = link_mask << 3;
	327	dma_data->packet_size =
	328	(MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
db72c2f8	329	} else {
f5f9d7bf MLC	330	mcpdm->up_channels = link_mask << 0;
f5f9d7bf MLC	331	dma_data->packet_size = mcpdm->up_threshold * channels;
db72c2f8 MLC	332	}
db72c2f8 MLC	333
b199adfd	334	snd_soc_dai_set_dma_data(dai, substream, dma_data);
f5f9d7bf MLC	335
f5f9d7bf MLC	336	return 0;
db72c2f8 MLC	337	}
db72c2f8 MLC	338
f5f9d7bf	339	static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
db72c2f8 MLC	340	struct snd_soc_dai *dai)
db72c2f8 MLC	341	{
f5f9d7bf	342	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	343
f5f9d7bf MLC	344	if (!omap_mcpdm_active(mcpdm)) {
	345	omap_mcpdm_start(mcpdm);
	346	omap_mcpdm_reg_dump(mcpdm);
	347	}
db72c2f8	348
f5f9d7bf	349	return 0;
db72c2f8 MLC	350	}
	351
	352	static struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
	353	.startup = omap_mcpdm_dai_startup,
	354	.shutdown = omap_mcpdm_dai_shutdown,
db72c2f8	355	.hw_params = omap_mcpdm_dai_hw_params,
f5f9d7bf	356	.prepare = omap_mcpdm_prepare,
db72c2f8 MLC	357	};
db72c2f8 MLC	358
f5f9d7bf MLC	359	static int omap_mcpdm_probe(struct snd_soc_dai *dai)
	360	{
	361	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	362	int ret;
	363
	364	pm_runtime_enable(mcpdm->dev);
	365
	366	/* Disable lines while request is ongoing */
	367	pm_runtime_get_sync(mcpdm->dev);
	368	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
	369
	370	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
	371	0, "McPDM", (void *)mcpdm);
db72c2f8	372
f5f9d7bf MLC	373	pm_runtime_put_sync(mcpdm->dev);
	374
	375	if (ret) {
	376	dev_err(mcpdm->dev, "Request for IRQ failed\n");
	377	pm_runtime_disable(mcpdm->dev);
	378	}
	379
	380	/* Configure McPDM threshold values */
	381	mcpdm->dn_threshold = 2;
	382	mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
	383	return ret;
	384	}
	385
	386	static int omap_mcpdm_remove(struct snd_soc_dai *dai)
f0fba2ad	387	{
f5f9d7bf MLC	388	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	389
	390	free_irq(mcpdm->irq, (void *)mcpdm);
	391	pm_runtime_disable(mcpdm->dev);
	392
f0fba2ad LG	393	return 0;
	394	}
	395
f5f9d7bf MLC	396	#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	397	#define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
	398
f0fba2ad	399	static struct snd_soc_dai_driver omap_mcpdm_dai = {
f5f9d7bf MLC	400	.probe = omap_mcpdm_probe,
	401	.remove = omap_mcpdm_remove,
	402	.probe_order = SND_SOC_COMP_ORDER_LATE,
	403	.remove_order = SND_SOC_COMP_ORDER_EARLY,
db72c2f8 MLC	404	.playback = {
	405	.channels_min = 1,
	406	.channels_max = 4,
	407	.rates = OMAP_MCPDM_RATES,
	408	.formats = OMAP_MCPDM_FORMATS,
	409	},
	410	.capture = {
	411	.channels_min = 1,
	412	.channels_max = 2,
	413	.rates = OMAP_MCPDM_RATES,
	414	.formats = OMAP_MCPDM_FORMATS,
	415	},
	416	.ops = &omap_mcpdm_dai_ops,
db72c2f8	417	};
f0fba2ad LG	418
	419	static __devinit int asoc_mcpdm_probe(struct platform_device *pdev)
	420	{
f5f9d7bf MLC	421	struct omap_mcpdm *mcpdm;
	422	struct resource *res;
	423	int ret = 0;
	424
	425	mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
	426	if (!mcpdm)
	427	return -ENOMEM;
	428
	429	platform_set_drvdata(pdev, mcpdm);
	430
	431	mutex_init(&mcpdm->mutex);
	432
	433	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	434	if (res == NULL) {
	435	dev_err(&pdev->dev, "no resource\n");
	436	goto err_res;
	437	}
	438
	439	if (!request_mem_region(res->start, resource_size(res), "McPDM")) {
	440	ret = -EBUSY;
	441	goto err_res;
	442	}
	443
	444	mcpdm->io_base = ioremap(res->start, resource_size(res));
	445	if (!mcpdm->io_base) {
	446	ret = -ENOMEM;
	447	goto err_iomap;
	448	}
	449
	450	mcpdm->irq = platform_get_irq(pdev, 0);
	451	if (mcpdm->irq < 0) {
	452	ret = mcpdm->irq;
	453	goto err_irq;
	454	}
	455
	456	mcpdm->dev = &pdev->dev;
f0fba2ad	457
f0fba2ad	458	ret = snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
f5f9d7bf MLC	459	if (!ret)
	460	return 0;
	461
	462	err_irq:
	463	iounmap(mcpdm->io_base);
	464	err_iomap:
	465	release_mem_region(res->start, resource_size(res));
	466	err_res:
	467	kfree(mcpdm);
f0fba2ad LG	468	return ret;
	469	}
	470
	471	static int __devexit asoc_mcpdm_remove(struct platform_device *pdev)
	472	{
f5f9d7bf MLC	473	struct omap_mcpdm *mcpdm = platform_get_drvdata(pdev);
	474	struct resource *res;
	475
f0fba2ad	476	snd_soc_unregister_dai(&pdev->dev);
f5f9d7bf MLC	477
	478	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	479	iounmap(mcpdm->io_base);
	480	release_mem_region(res->start, resource_size(res));
	481
	482	kfree(mcpdm);
f0fba2ad LG	483	return 0;
	484	}
	485
	486	static struct platform_driver asoc_mcpdm_driver = {
	487	.driver = {
f5f9d7bf MLC	488	.name = "omap-mcpdm",
f5f9d7bf MLC	489	.owner = THIS_MODULE,
f0fba2ad LG	490	},
f0fba2ad LG	491
f5f9d7bf MLC	492	.probe = asoc_mcpdm_probe,
f5f9d7bf MLC	493	.remove = __devexit_p(asoc_mcpdm_remove),
f0fba2ad	494	};
db72c2f8 MLC	495
	496	static int __init snd_omap_mcpdm_init(void)
	497	{
f0fba2ad	498	return platform_driver_register(&asoc_mcpdm_driver);
db72c2f8 MLC	499	}
	500	module_init(snd_omap_mcpdm_init);
	501
	502	static void __exit snd_omap_mcpdm_exit(void)
	503	{
f0fba2ad	504	platform_driver_unregister(&asoc_mcpdm_driver);
db72c2f8 MLC	505	}
	506	module_exit(snd_omap_mcpdm_exit);
	507
f5f9d7bf	508	MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
db72c2f8 MLC	509	MODULE_DESCRIPTION("OMAP PDM SoC Interface");
db72c2f8 MLC	510	MODULE_LICENSE("GPL");