Commit | Line | Data |
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db72c2f8 MLC |
1 | /* |
2 | * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port | |
3 | * | |
f5f9d7bf | 4 | * Copyright (C) 2009 - 2011 Texas Instruments |
db72c2f8 | 5 | * |
f5f9d7bf | 6 | * Author: Misael Lopez Cruz <misael.lopez@ti.com> |
db72c2f8 MLC |
7 | * Contact: Jorge Eduardo Candelaria <x0107209@ti.com> |
8 | * Margarita Olaya <magi.olaya@ti.com> | |
f5f9d7bf | 9 | * Peter Ujfalusi <peter.ujfalusi@ti.com> |
db72c2f8 MLC |
10 | * |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * version 2 as published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
23 | * 02110-1301 USA | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
f5f9d7bf MLC |
29 | #include <linux/platform_device.h> |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/err.h> | |
32 | #include <linux/io.h> | |
33 | #include <linux/irq.h> | |
34 | #include <linux/slab.h> | |
35 | #include <linux/pm_runtime.h> | |
7cb8a1b5 | 36 | #include <linux/of_device.h> |
f5f9d7bf | 37 | |
db72c2f8 MLC |
38 | #include <sound/core.h> |
39 | #include <sound/pcm.h> | |
40 | #include <sound/pcm_params.h> | |
db72c2f8 | 41 | #include <sound/soc.h> |
09ae3aaf | 42 | #include <sound/dmaengine_pcm.h> |
db72c2f8 | 43 | |
f5f9d7bf | 44 | #include "omap-mcpdm.h" |
db72c2f8 | 45 | |
62376631 PU |
46 | struct mcpdm_link_config { |
47 | u32 link_mask; /* channel mask for the direction */ | |
48 | u32 threshold; /* FIFO threshold */ | |
49 | }; | |
dbc04161 | 50 | |
f5f9d7bf MLC |
51 | struct omap_mcpdm { |
52 | struct device *dev; | |
53 | unsigned long phys_base; | |
54 | void __iomem *io_base; | |
55 | int irq; | |
db72c2f8 | 56 | |
f5f9d7bf MLC |
57 | struct mutex mutex; |
58 | ||
62376631 PU |
59 | /* Playback/Capture configuration */ |
60 | struct mcpdm_link_config config[2]; | |
89b0d550 PU |
61 | |
62 | /* McPDM dn offsets for rx1, and 2 channels */ | |
63 | u32 dn_rx_offset; | |
81054b22 PU |
64 | |
65 | /* McPDM needs to be restarted due to runtime reconfiguration */ | |
66 | bool restart; | |
09ae3aaf LPC |
67 | |
68 | struct snd_dmaengine_dai_dma_data dma_data[2]; | |
db72c2f8 MLC |
69 | }; |
70 | ||
71 | /* | |
72 | * Stream DMA parameters | |
73 | */ | |
db72c2f8 | 74 | |
f5f9d7bf | 75 | static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val) |
db72c2f8 | 76 | { |
1b488a48 | 77 | writel_relaxed(val, mcpdm->io_base + reg); |
f5f9d7bf | 78 | } |
db72c2f8 | 79 | |
f5f9d7bf MLC |
80 | static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg) |
81 | { | |
1b488a48 | 82 | return readl_relaxed(mcpdm->io_base + reg); |
f5f9d7bf | 83 | } |
db72c2f8 | 84 | |
f5f9d7bf MLC |
85 | #ifdef DEBUG |
86 | static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) | |
87 | { | |
88 | dev_dbg(mcpdm->dev, "***********************\n"); | |
89 | dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n", | |
90 | omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW)); | |
91 | dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n", | |
92 | omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS)); | |
93 | dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n", | |
94 | omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET)); | |
95 | dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n", | |
96 | omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR)); | |
97 | dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n", | |
98 | omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN)); | |
99 | dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n", | |
100 | omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET)); | |
101 | dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n", | |
102 | omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR)); | |
103 | dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n", | |
104 | omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN)); | |
105 | dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n", | |
106 | omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL)); | |
107 | dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n", | |
108 | omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA)); | |
109 | dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n", | |
110 | omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA)); | |
111 | dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n", | |
112 | omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN)); | |
113 | dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n", | |
114 | omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP)); | |
115 | dev_dbg(mcpdm->dev, "***********************\n"); | |
db72c2f8 | 116 | } |
f5f9d7bf MLC |
117 | #else |
118 | static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {} | |
119 | #endif | |
db72c2f8 | 120 | |
f5f9d7bf MLC |
121 | /* |
122 | * Enables the transfer through the PDM interface to/from the Phoenix | |
123 | * codec by enabling the corresponding UP or DN channels. | |
124 | */ | |
125 | static void omap_mcpdm_start(struct omap_mcpdm *mcpdm) | |
126 | { | |
127 | u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL); | |
62376631 | 128 | u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask; |
f5f9d7bf MLC |
129 | |
130 | ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); | |
131 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); | |
132 | ||
62376631 | 133 | ctrl |= link_mask; |
f5f9d7bf MLC |
134 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); |
135 | ||
136 | ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); | |
137 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); | |
138 | } | |
139 | ||
140 | /* | |
141 | * Disables the transfer through the PDM interface to/from the Phoenix | |
142 | * codec by disabling the corresponding UP or DN channels. | |
143 | */ | |
144 | static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm) | |
145 | { | |
146 | u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL); | |
81054b22 | 147 | u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK; |
f5f9d7bf MLC |
148 | |
149 | ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); | |
150 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); | |
151 | ||
62376631 | 152 | ctrl &= ~(link_mask); |
f5f9d7bf MLC |
153 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); |
154 | ||
155 | ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); | |
156 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); | |
157 | ||
158 | } | |
159 | ||
160 | /* | |
161 | * Is the physical McPDM interface active. | |
162 | */ | |
163 | static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm) | |
164 | { | |
165 | return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) & | |
166 | (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK); | |
167 | } | |
168 | ||
169 | /* | |
170 | * Configures McPDM uplink, and downlink for audio. | |
171 | * This function should be called before omap_mcpdm_start. | |
172 | */ | |
173 | static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm) | |
174 | { | |
175 | omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET, | |
176 | MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL | | |
177 | MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL); | |
178 | ||
89b0d550 PU |
179 | /* Enable DN RX1/2 offset cancellation feature, if configured */ |
180 | if (mcpdm->dn_rx_offset) { | |
181 | u32 dn_offset = mcpdm->dn_rx_offset; | |
182 | ||
183 | omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset); | |
184 | dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN); | |
185 | omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset); | |
186 | } | |
187 | ||
62376631 PU |
188 | omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, |
189 | mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold); | |
190 | omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, | |
191 | mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold); | |
f5f9d7bf MLC |
192 | |
193 | omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET, | |
194 | MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE); | |
195 | } | |
196 | ||
197 | /* | |
198 | * Cleans McPDM uplink, and downlink configuration. | |
199 | * This function should be called when the stream is closed. | |
200 | */ | |
201 | static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm) | |
db72c2f8 | 202 | { |
f5f9d7bf MLC |
203 | /* Disable irq request generation for downlink */ |
204 | omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR, | |
205 | MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL); | |
206 | ||
207 | /* Disable DMA request generation for downlink */ | |
208 | omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE); | |
209 | ||
210 | /* Disable irq request generation for uplink */ | |
211 | omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR, | |
212 | MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL); | |
213 | ||
214 | /* Disable DMA request generation for uplink */ | |
215 | omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE); | |
89b0d550 PU |
216 | |
217 | /* Disable RX1/2 offset cancellation */ | |
218 | if (mcpdm->dn_rx_offset) | |
219 | omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0); | |
f5f9d7bf MLC |
220 | } |
221 | ||
222 | static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id) | |
223 | { | |
224 | struct omap_mcpdm *mcpdm = dev_id; | |
225 | int irq_status; | |
226 | ||
227 | irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS); | |
228 | ||
229 | /* Acknowledge irq event */ | |
230 | omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status); | |
231 | ||
232 | if (irq_status & MCPDM_DN_IRQ_FULL) | |
233 | dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n"); | |
234 | ||
235 | if (irq_status & MCPDM_DN_IRQ_EMPTY) | |
236 | dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n"); | |
237 | ||
238 | if (irq_status & MCPDM_DN_IRQ) | |
239 | dev_dbg(mcpdm->dev, "DN (playback) write request\n"); | |
240 | ||
241 | if (irq_status & MCPDM_UP_IRQ_FULL) | |
242 | dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n"); | |
243 | ||
244 | if (irq_status & MCPDM_UP_IRQ_EMPTY) | |
245 | dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n"); | |
246 | ||
247 | if (irq_status & MCPDM_UP_IRQ) | |
248 | dev_dbg(mcpdm->dev, "UP (capture) write request\n"); | |
249 | ||
250 | return IRQ_HANDLED; | |
db72c2f8 MLC |
251 | } |
252 | ||
f5f9d7bf | 253 | static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream, |
db72c2f8 MLC |
254 | struct snd_soc_dai *dai) |
255 | { | |
f5f9d7bf | 256 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); |
db72c2f8 | 257 | |
f5f9d7bf MLC |
258 | mutex_lock(&mcpdm->mutex); |
259 | ||
260 | if (!dai->active) { | |
68214d99 | 261 | u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL); |
f5f9d7bf | 262 | |
68214d99 | 263 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN); |
f5f9d7bf | 264 | omap_mcpdm_open_streams(mcpdm); |
db72c2f8 | 265 | } |
f5f9d7bf MLC |
266 | mutex_unlock(&mcpdm->mutex); |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
271 | static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream, | |
272 | struct snd_soc_dai *dai) | |
273 | { | |
274 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); | |
275 | ||
276 | mutex_lock(&mcpdm->mutex); | |
277 | ||
278 | if (!dai->active) { | |
279 | if (omap_mcpdm_active(mcpdm)) { | |
280 | omap_mcpdm_stop(mcpdm); | |
281 | omap_mcpdm_close_streams(mcpdm); | |
81054b22 PU |
282 | mcpdm->config[0].link_mask = 0; |
283 | mcpdm->config[1].link_mask = 0; | |
f5f9d7bf | 284 | } |
f5f9d7bf MLC |
285 | } |
286 | ||
287 | mutex_unlock(&mcpdm->mutex); | |
db72c2f8 MLC |
288 | } |
289 | ||
290 | static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream, | |
291 | struct snd_pcm_hw_params *params, | |
292 | struct snd_soc_dai *dai) | |
293 | { | |
f5f9d7bf | 294 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); |
db72c2f8 | 295 | int stream = substream->stream; |
09ae3aaf | 296 | struct snd_dmaengine_dai_dma_data *dma_data; |
62376631 | 297 | u32 threshold; |
f5f9d7bf MLC |
298 | int channels; |
299 | int link_mask = 0; | |
db72c2f8 | 300 | |
db72c2f8 MLC |
301 | channels = params_channels(params); |
302 | switch (channels) { | |
3b5b516f PU |
303 | case 5: |
304 | if (stream == SNDRV_PCM_STREAM_CAPTURE) | |
305 | /* up to 3 channels for capture */ | |
306 | return -EINVAL; | |
307 | link_mask |= 1 << 4; | |
db72c2f8 MLC |
308 | case 4: |
309 | if (stream == SNDRV_PCM_STREAM_CAPTURE) | |
3b5b516f | 310 | /* up to 3 channels for capture */ |
db72c2f8 MLC |
311 | return -EINVAL; |
312 | link_mask |= 1 << 3; | |
313 | case 3: | |
db72c2f8 MLC |
314 | link_mask |= 1 << 2; |
315 | case 2: | |
316 | link_mask |= 1 << 1; | |
317 | case 1: | |
318 | link_mask |= 1 << 0; | |
319 | break; | |
320 | default: | |
321 | /* unsupported number of channels */ | |
322 | return -EINVAL; | |
323 | } | |
324 | ||
bcd6da7b | 325 | dma_data = snd_soc_dai_get_dma_data(dai, substream); |
b199adfd | 326 | |
62376631 | 327 | threshold = mcpdm->config[stream].threshold; |
f5f9d7bf | 328 | /* Configure McPDM channels, and DMA packet size */ |
db72c2f8 | 329 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
62376631 | 330 | link_mask <<= 3; |
81054b22 PU |
331 | |
332 | /* If capture is not running assume a stereo stream to come */ | |
333 | if (!mcpdm->config[!stream].link_mask) | |
334 | mcpdm->config[!stream].link_mask = 0x3; | |
335 | ||
09ae3aaf | 336 | dma_data->maxburst = |
62376631 | 337 | (MCPDM_DN_THRES_MAX - threshold) * channels; |
db72c2f8 | 338 | } else { |
81054b22 PU |
339 | /* If playback is not running assume a stereo stream to come */ |
340 | if (!mcpdm->config[!stream].link_mask) | |
341 | mcpdm->config[!stream].link_mask = (0x3 << 3); | |
342 | ||
09ae3aaf | 343 | dma_data->maxburst = threshold * channels; |
db72c2f8 MLC |
344 | } |
345 | ||
81054b22 PU |
346 | /* Check if we need to restart McPDM with this stream */ |
347 | if (mcpdm->config[stream].link_mask && | |
348 | mcpdm->config[stream].link_mask != link_mask) | |
349 | mcpdm->restart = true; | |
350 | ||
62376631 | 351 | mcpdm->config[stream].link_mask = link_mask; |
db72c2f8 | 352 | |
f5f9d7bf | 353 | return 0; |
db72c2f8 MLC |
354 | } |
355 | ||
f5f9d7bf | 356 | static int omap_mcpdm_prepare(struct snd_pcm_substream *substream, |
db72c2f8 MLC |
357 | struct snd_soc_dai *dai) |
358 | { | |
f5f9d7bf | 359 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); |
db72c2f8 | 360 | |
f5f9d7bf MLC |
361 | if (!omap_mcpdm_active(mcpdm)) { |
362 | omap_mcpdm_start(mcpdm); | |
363 | omap_mcpdm_reg_dump(mcpdm); | |
81054b22 PU |
364 | } else if (mcpdm->restart) { |
365 | omap_mcpdm_stop(mcpdm); | |
366 | omap_mcpdm_start(mcpdm); | |
367 | mcpdm->restart = false; | |
368 | omap_mcpdm_reg_dump(mcpdm); | |
f5f9d7bf | 369 | } |
db72c2f8 | 370 | |
f5f9d7bf | 371 | return 0; |
db72c2f8 MLC |
372 | } |
373 | ||
85e7652d | 374 | static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = { |
db72c2f8 MLC |
375 | .startup = omap_mcpdm_dai_startup, |
376 | .shutdown = omap_mcpdm_dai_shutdown, | |
db72c2f8 | 377 | .hw_params = omap_mcpdm_dai_hw_params, |
f5f9d7bf | 378 | .prepare = omap_mcpdm_prepare, |
db72c2f8 MLC |
379 | }; |
380 | ||
f5f9d7bf MLC |
381 | static int omap_mcpdm_probe(struct snd_soc_dai *dai) |
382 | { | |
383 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); | |
384 | int ret; | |
385 | ||
386 | pm_runtime_enable(mcpdm->dev); | |
387 | ||
388 | /* Disable lines while request is ongoing */ | |
389 | pm_runtime_get_sync(mcpdm->dev); | |
390 | omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00); | |
391 | ||
ddd17531 | 392 | ret = devm_request_irq(mcpdm->dev, mcpdm->irq, omap_mcpdm_irq_handler, |
f5f9d7bf | 393 | 0, "McPDM", (void *)mcpdm); |
db72c2f8 | 394 | |
f5f9d7bf MLC |
395 | pm_runtime_put_sync(mcpdm->dev); |
396 | ||
397 | if (ret) { | |
398 | dev_err(mcpdm->dev, "Request for IRQ failed\n"); | |
399 | pm_runtime_disable(mcpdm->dev); | |
400 | } | |
401 | ||
402 | /* Configure McPDM threshold values */ | |
62376631 PU |
403 | mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2; |
404 | mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold = | |
405 | MCPDM_UP_THRES_MAX - 3; | |
f6563b31 PU |
406 | |
407 | snd_soc_dai_init_dma_data(dai, | |
408 | &mcpdm->dma_data[SNDRV_PCM_STREAM_PLAYBACK], | |
409 | &mcpdm->dma_data[SNDRV_PCM_STREAM_CAPTURE]); | |
410 | ||
f5f9d7bf MLC |
411 | return ret; |
412 | } | |
413 | ||
414 | static int omap_mcpdm_remove(struct snd_soc_dai *dai) | |
f0fba2ad | 415 | { |
f5f9d7bf MLC |
416 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); |
417 | ||
f5f9d7bf MLC |
418 | pm_runtime_disable(mcpdm->dev); |
419 | ||
f0fba2ad LG |
420 | return 0; |
421 | } | |
422 | ||
f5f9d7bf MLC |
423 | #define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) |
424 | #define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE | |
425 | ||
f0fba2ad | 426 | static struct snd_soc_dai_driver omap_mcpdm_dai = { |
f5f9d7bf MLC |
427 | .probe = omap_mcpdm_probe, |
428 | .remove = omap_mcpdm_remove, | |
429 | .probe_order = SND_SOC_COMP_ORDER_LATE, | |
430 | .remove_order = SND_SOC_COMP_ORDER_EARLY, | |
db72c2f8 MLC |
431 | .playback = { |
432 | .channels_min = 1, | |
3b5b516f | 433 | .channels_max = 5, |
db72c2f8 MLC |
434 | .rates = OMAP_MCPDM_RATES, |
435 | .formats = OMAP_MCPDM_FORMATS, | |
b4badd49 | 436 | .sig_bits = 24, |
db72c2f8 MLC |
437 | }, |
438 | .capture = { | |
439 | .channels_min = 1, | |
3b5b516f | 440 | .channels_max = 3, |
db72c2f8 MLC |
441 | .rates = OMAP_MCPDM_RATES, |
442 | .formats = OMAP_MCPDM_FORMATS, | |
b4badd49 | 443 | .sig_bits = 24, |
db72c2f8 MLC |
444 | }, |
445 | .ops = &omap_mcpdm_dai_ops, | |
db72c2f8 | 446 | }; |
f0fba2ad | 447 | |
58709a32 KM |
448 | static const struct snd_soc_component_driver omap_mcpdm_component = { |
449 | .name = "omap-mcpdm", | |
450 | }; | |
451 | ||
89b0d550 PU |
452 | void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd, |
453 | u8 rx1, u8 rx2) | |
454 | { | |
455 | struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai); | |
456 | ||
457 | mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2); | |
458 | } | |
459 | EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets); | |
460 | ||
7ff60006 | 461 | static int asoc_mcpdm_probe(struct platform_device *pdev) |
f0fba2ad | 462 | { |
f5f9d7bf MLC |
463 | struct omap_mcpdm *mcpdm; |
464 | struct resource *res; | |
f5f9d7bf | 465 | |
d77ae332 | 466 | mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL); |
f5f9d7bf MLC |
467 | if (!mcpdm) |
468 | return -ENOMEM; | |
469 | ||
470 | platform_set_drvdata(pdev, mcpdm); | |
471 | ||
472 | mutex_init(&mcpdm->mutex); | |
473 | ||
5a40c57a PU |
474 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); |
475 | if (res == NULL) | |
476 | return -ENOMEM; | |
477 | ||
09ae3aaf LPC |
478 | mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA; |
479 | mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA; | |
5a40c57a | 480 | |
a8035f07 PU |
481 | mcpdm->dma_data[0].filter_data = "dn_link"; |
482 | mcpdm->dma_data[1].filter_data = "up_link"; | |
5a40c57a PU |
483 | |
484 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); | |
77c641d3 SMP |
485 | mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res); |
486 | if (IS_ERR(mcpdm->io_base)) | |
487 | return PTR_ERR(mcpdm->io_base); | |
f5f9d7bf MLC |
488 | |
489 | mcpdm->irq = platform_get_irq(pdev, 0); | |
d77ae332 PU |
490 | if (mcpdm->irq < 0) |
491 | return mcpdm->irq; | |
f5f9d7bf MLC |
492 | |
493 | mcpdm->dev = &pdev->dev; | |
f0fba2ad | 494 | |
6c3cc302 SK |
495 | return devm_snd_soc_register_component(&pdev->dev, |
496 | &omap_mcpdm_component, | |
497 | &omap_mcpdm_dai, 1); | |
f0fba2ad LG |
498 | } |
499 | ||
7cb8a1b5 PU |
500 | static const struct of_device_id omap_mcpdm_of_match[] = { |
501 | { .compatible = "ti,omap4-mcpdm", }, | |
502 | { } | |
503 | }; | |
504 | MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match); | |
505 | ||
f0fba2ad LG |
506 | static struct platform_driver asoc_mcpdm_driver = { |
507 | .driver = { | |
f5f9d7bf MLC |
508 | .name = "omap-mcpdm", |
509 | .owner = THIS_MODULE, | |
7cb8a1b5 | 510 | .of_match_table = omap_mcpdm_of_match, |
f0fba2ad LG |
511 | }, |
512 | ||
f5f9d7bf | 513 | .probe = asoc_mcpdm_probe, |
f0fba2ad | 514 | }; |
db72c2f8 | 515 | |
beda5bf5 | 516 | module_platform_driver(asoc_mcpdm_driver); |
db72c2f8 | 517 | |
d66a547c | 518 | MODULE_ALIAS("platform:omap-mcpdm"); |
f5f9d7bf | 519 | MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>"); |
db72c2f8 MLC |
520 | MODULE_DESCRIPTION("OMAP PDM SoC Interface"); |
521 | MODULE_LICENSE("GPL"); |