[deliverable/linux.git] / sound / soc / omap / omap-mcpdm.c

/*
 * omap-mcpdm.c  --  OMAP ALSA SoC DAI driver using McPDM port
 *
 * Copyright (C) 2009 - 2011 Texas Instruments
 *
 * Author: Misael Lopez Cruz <misael.lopez@ti.com>
 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
 *          Margarita Olaya <magi.olaya@ti.com>
 *          Peter Ujfalusi <peter.ujfalusi@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include <plat/dma.h>
#include <plat/omap_hwmod.h>
#include "omap-mcpdm.h"
#include "omap-pcm.h"

struct omap_mcpdm {
	struct device *dev;
	unsigned long phys_base;
	void __iomem *io_base;
	int irq;

	struct mutex mutex;

	/* channel data */
	u32 dn_channels;
	u32 up_channels;

	/* McPDM FIFO thresholds */
	u32 dn_threshold;
	u32 up_threshold;

	/* McPDM dn offsets for rx1, and 2 channels */
	u32 dn_rx_offset;
};

/*
 * Stream DMA parameters
 */
static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
	{
		.name = "Audio playback",
		.dma_req = OMAP44XX_DMA_MCPDM_DL,
		.data_type = OMAP_DMA_DATA_TYPE_S32,
		.sync_mode = OMAP_DMA_SYNC_PACKET,
		.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_DN_DATA,
	},
	{
		.name = "Audio capture",
		.dma_req = OMAP44XX_DMA_MCPDM_UP,
		.data_type = OMAP_DMA_DATA_TYPE_S32,
		.sync_mode = OMAP_DMA_SYNC_PACKET,
		.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_UP_DATA,
	},
};

static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
{
	__raw_writel(val, mcpdm->io_base + reg);
}

static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
{
	return __raw_readl(mcpdm->io_base + reg);
}

#ifdef DEBUG
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
{
	dev_dbg(mcpdm->dev, "***********************\n");
	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	dev_dbg(mcpdm->dev, "IRQSTATUS:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	dev_dbg(mcpdm->dev, "DMAWAKEEN:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	dev_dbg(mcpdm->dev, "CTRL:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	dev_dbg(mcpdm->dev, "***********************\n");
}
#else
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
#endif

/*
 * Enables the transfer through the PDM interface to/from the Phoenix
 * codec by enabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl |= mcpdm->dn_channels | mcpdm->up_channels;
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
}

/*
 * Disables the transfer through the PDM interface to/from the Phoenix
 * codec by disabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(mcpdm->dn_channels | mcpdm->up_channels);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

}

/*
 * Is the physical McPDM interface active.
 */
static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
{
	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
					(MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
}

/*
 * Configures McPDM uplink, and downlink for audio.
 * This function should be called before omap_mcpdm_start.
 */
static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
{
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Enable DN RX1/2 offset cancellation feature, if configured */
	if (mcpdm->dn_rx_offset) {
		u32 dn_offset = mcpdm->dn_rx_offset;

		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
		dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	}

	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);

	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
			MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
}

/*
 * Cleans McPDM uplink, and downlink configuration.
 * This function should be called when the stream is closed.
 */
static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
{
	/* Disable irq request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);

	/* Disable DMA request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);

	/* Disable irq request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Disable DMA request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);

	/* Disable RX1/2 offset cancellation */
	if (mcpdm->dn_rx_offset)
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
}

static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
{
	struct omap_mcpdm *mcpdm = dev_id;
	int irq_status;

	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);

	/* Acknowledge irq event */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);

	if (irq_status & MCPDM_DN_IRQ_FULL)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");

	if (irq_status & MCPDM_DN_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");

	if (irq_status & MCPDM_DN_IRQ)
		dev_dbg(mcpdm->dev, "DN (playback) write request\n");

	if (irq_status & MCPDM_UP_IRQ_FULL)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");

	if (irq_status & MCPDM_UP_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");

	if (irq_status & MCPDM_UP_IRQ)
		dev_dbg(mcpdm->dev, "UP (capture) write request\n");

	return IRQ_HANDLED;
}

static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		pm_runtime_get_sync(mcpdm->dev);

		/* Enable watch dog for ES above ES 1.0 to avoid saturation */
		if (omap_rev() != OMAP4430_REV_ES1_0) {
			u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

			omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL,
					 ctrl | MCPDM_WD_EN);
		}
		omap_mcpdm_open_streams(mcpdm);
	}

	mutex_unlock(&mcpdm->mutex);

	return 0;
}

static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		if (omap_mcpdm_active(mcpdm)) {
			omap_mcpdm_stop(mcpdm);
			omap_mcpdm_close_streams(mcpdm);
		}

		if (!omap_mcpdm_active(mcpdm))
			pm_runtime_put_sync(mcpdm->dev);
	}

	mutex_unlock(&mcpdm->mutex);
}

static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int stream = substream->stream;
	struct omap_pcm_dma_data *dma_data;
	int channels;
	int link_mask = 0;

	channels = params_channels(params);
	switch (channels) {
	case 5:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 4;
	case 4:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 3;
	case 3:
		link_mask |= 1 << 2;
	case 2:
		link_mask |= 1 << 1;
	case 1:
		link_mask |= 1 << 0;
		break;
	default:
		/* unsupported number of channels */
		return -EINVAL;
	}

	dma_data = &omap_mcpdm_dai_dma_params[stream];

	/* Configure McPDM channels, and DMA packet size */
	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		mcpdm->dn_channels = link_mask << 3;
		dma_data->packet_size =
			(MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
	} else {
		mcpdm->up_channels = link_mask << 0;
		dma_data->packet_size = mcpdm->up_threshold * channels;
	}

	snd_soc_dai_set_dma_data(dai, substream, dma_data);

	return 0;
}

static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	if (!omap_mcpdm_active(mcpdm)) {
		omap_mcpdm_start(mcpdm);
		omap_mcpdm_reg_dump(mcpdm);
	}

	return 0;
}

static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
	.startup	= omap_mcpdm_dai_startup,
	.shutdown	= omap_mcpdm_dai_shutdown,
	.hw_params	= omap_mcpdm_dai_hw_params,
	.prepare	= omap_mcpdm_prepare,
};

static int omap_mcpdm_probe(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int ret;

	pm_runtime_enable(mcpdm->dev);

	/* Disable lines while request is ongoing */
	pm_runtime_get_sync(mcpdm->dev);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);

	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
				0, "McPDM", (void *)mcpdm);

	pm_runtime_put_sync(mcpdm->dev);

	if (ret) {
		dev_err(mcpdm->dev, "Request for IRQ failed\n");
		pm_runtime_disable(mcpdm->dev);
	}

	/* Configure McPDM threshold values */
	mcpdm->dn_threshold = 2;
	mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
	return ret;
}

static int omap_mcpdm_remove(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	free_irq(mcpdm->irq, (void *)mcpdm);
	pm_runtime_disable(mcpdm->dev);

	return 0;
}

#define OMAP_MCPDM_RATES	(SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define OMAP_MCPDM_FORMATS	SNDRV_PCM_FMTBIT_S32_LE

static struct snd_soc_dai_driver omap_mcpdm_dai = {
	.probe = omap_mcpdm_probe,
	.remove = omap_mcpdm_remove,
	.probe_order = SND_SOC_COMP_ORDER_LATE,
	.remove_order = SND_SOC_COMP_ORDER_EARLY,
	.playback = {
		.channels_min = 1,
		.channels_max = 5,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
	},
	.capture = {
		.channels_min = 1,
		.channels_max = 3,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
	},
	.ops = &omap_mcpdm_dai_ops,
};

void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
				    u8 rx1, u8 rx2)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);

	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
}
EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);

static __devinit int asoc_mcpdm_probe(struct platform_device *pdev)
{
	struct omap_mcpdm *mcpdm;
	struct resource *res;
	int ret = 0;

	mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
	if (!mcpdm)
		return -ENOMEM;

	platform_set_drvdata(pdev, mcpdm);

	mutex_init(&mcpdm->mutex);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res == NULL) {
		dev_err(&pdev->dev, "no resource\n");
		goto err_res;
	}

	if (!request_mem_region(res->start, resource_size(res), "McPDM")) {
		ret = -EBUSY;
		goto err_res;
	}

	mcpdm->io_base = ioremap(res->start, resource_size(res));
	if (!mcpdm->io_base) {
		ret = -ENOMEM;
		goto err_iomap;
	}

	mcpdm->irq = platform_get_irq(pdev, 0);
	if (mcpdm->irq < 0) {
		ret = mcpdm->irq;
		goto err_irq;
	}

	mcpdm->dev = &pdev->dev;

	ret = snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
	if (!ret)
		return 0;

err_irq:
	iounmap(mcpdm->io_base);
err_iomap:
	release_mem_region(res->start, resource_size(res));
err_res:
	kfree(mcpdm);
	return ret;
}

static int __devexit asoc_mcpdm_remove(struct platform_device *pdev)
{
	struct omap_mcpdm *mcpdm = platform_get_drvdata(pdev);
	struct resource *res;

	snd_soc_unregister_dai(&pdev->dev);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	iounmap(mcpdm->io_base);
	release_mem_region(res->start, resource_size(res));

	kfree(mcpdm);
	return 0;
}

static struct platform_driver asoc_mcpdm_driver = {
	.driver = {
		.name	= "omap-mcpdm",
		.owner	= THIS_MODULE,
	},

	.probe	= asoc_mcpdm_probe,
	.remove	= __devexit_p(asoc_mcpdm_remove),
};

static int __init snd_omap_mcpdm_init(void)
{
	return platform_driver_register(&asoc_mcpdm_driver);
}
module_init(snd_omap_mcpdm_init);

static void __exit snd_omap_mcpdm_exit(void)
{
	platform_driver_unregister(&asoc_mcpdm_driver);
}
module_exit(snd_omap_mcpdm_exit);

MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
MODULE_DESCRIPTION("OMAP PDM SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
db72c2f8 MLC	1	/*
	2	* omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
	3	*
f5f9d7bf	4	* Copyright (C) 2009 - 2011 Texas Instruments
db72c2f8	5	*
f5f9d7bf	6	* Author: Misael Lopez Cruz <misael.lopez@ti.com>
db72c2f8 MLC	7	* Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
db72c2f8 MLC	8	* Margarita Olaya <magi.olaya@ti.com>
f5f9d7bf	9	* Peter Ujfalusi <peter.ujfalusi@ti.com>
db72c2f8 MLC	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License
	13	* version 2 as published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful, but
	16	* WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	23	* 02110-1301 USA
	24	*
	25	*/
	26
	27	#include <linux/init.h>
	28	#include <linux/module.h>
f5f9d7bf MLC	29	#include <linux/platform_device.h>
	30	#include <linux/interrupt.h>
	31	#include <linux/err.h>
	32	#include <linux/io.h>
	33	#include <linux/irq.h>
	34	#include <linux/slab.h>
	35	#include <linux/pm_runtime.h>
	36
db72c2f8 MLC	37	#include <sound/core.h>
	38	#include <sound/pcm.h>
	39	#include <sound/pcm_params.h>
db72c2f8 MLC	40	#include <sound/soc.h>
db72c2f8 MLC	41
db72c2f8	42	#include <plat/dma.h>
f5f9d7bf MLC	43	#include <plat/omap_hwmod.h>
f5f9d7bf MLC	44	#include "omap-mcpdm.h"
db72c2f8 MLC	45	#include "omap-pcm.h"
db72c2f8 MLC	46
f5f9d7bf MLC	47	struct omap_mcpdm {
	48	struct device *dev;
	49	unsigned long phys_base;
	50	void __iomem *io_base;
	51	int irq;
db72c2f8	52
f5f9d7bf MLC	53	struct mutex mutex;
	54
	55	/* channel data */
	56	u32 dn_channels;
	57	u32 up_channels;
db72c2f8	58
f5f9d7bf MLC	59	/* McPDM FIFO thresholds */
	60	u32 dn_threshold;
	61	u32 up_threshold;
89b0d550 PU	62
	63	/* McPDM dn offsets for rx1, and 2 channels */
	64	u32 dn_rx_offset;
db72c2f8 MLC	65	};
	66
	67	/*
	68	* Stream DMA parameters
	69	*/
	70	static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
	71	{
	72	.name = "Audio playback",
	73	.dma_req = OMAP44XX_DMA_MCPDM_DL,
	74	.data_type = OMAP_DMA_DATA_TYPE_S32,
	75	.sync_mode = OMAP_DMA_SYNC_PACKET,
f5f9d7bf	76	.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_DN_DATA,
db72c2f8 MLC	77	},
	78	{
	79	.name = "Audio capture",
	80	.dma_req = OMAP44XX_DMA_MCPDM_UP,
	81	.data_type = OMAP_DMA_DATA_TYPE_S32,
	82	.sync_mode = OMAP_DMA_SYNC_PACKET,
f5f9d7bf	83	.port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_UP_DATA,
db72c2f8 MLC	84	},
	85	};
	86
f5f9d7bf	87	static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
db72c2f8	88	{
f5f9d7bf MLC	89	__raw_writel(val, mcpdm->io_base + reg);
f5f9d7bf MLC	90	}
db72c2f8	91
f5f9d7bf MLC	92	static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
	93	{
	94	return __raw_readl(mcpdm->io_base + reg);
	95	}
db72c2f8	96
f5f9d7bf MLC	97	#ifdef DEBUG
	98	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
	99	{
	100	dev_dbg(mcpdm->dev, "***********************\n");
	101	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
	102	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	103	dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
	104	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	105	dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
	106	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	107	dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
	108	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	109	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
	110	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	111	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
	112	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	113	dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
	114	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	115	dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
	116	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	117	dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
	118	omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	119	dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
	120	omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	121	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
	122	omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	123	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
	124	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	125	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
	126	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	127	dev_dbg(mcpdm->dev, "***********************\n");
db72c2f8	128	}
f5f9d7bf MLC	129	#else
	130	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
	131	#endif
db72c2f8	132
f5f9d7bf MLC	133	/*
	134	* Enables the transfer through the PDM interface to/from the Phoenix
	135	* codec by enabling the corresponding UP or DN channels.
	136	*/
	137	static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
	138	{
	139	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	140
	141	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	142	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	143
	144	ctrl \|= mcpdm->dn_channels \| mcpdm->up_channels;
	145	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	146
	147	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	148	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	149	}
	150
	151	/*
	152	* Disables the transfer through the PDM interface to/from the Phoenix
	153	* codec by disabling the corresponding UP or DN channels.
	154	*/
	155	static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
	156	{
	157	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	158
	159	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	160	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	161
	162	ctrl &= ~(mcpdm->dn_channels \| mcpdm->up_channels);
	163	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	164
	165	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	166	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	167
	168	}
	169
	170	/*
	171	* Is the physical McPDM interface active.
	172	*/
	173	static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
	174	{
	175	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
	176	(MCPDM_PDM_DN_MASK \| MCPDM_PDM_UP_MASK);
	177	}
	178
	179	/*
	180	* Configures McPDM uplink, and downlink for audio.
	181	* This function should be called before omap_mcpdm_start.
	182	*/
	183	static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
	184	{
	185	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
	186	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL \|
	187	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	188
89b0d550 PU	189	/* Enable DN RX1/2 offset cancellation feature, if configured */
	190	if (mcpdm->dn_rx_offset) {
	191	u32 dn_offset = mcpdm->dn_rx_offset;
	192
	193	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	194	dn_offset \|= (MCPDM_DN_OFST_RX1_EN \| MCPDM_DN_OFST_RX2_EN);
	195	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	196	}
	197
f5f9d7bf MLC	198	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
	199	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);
	200
	201	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
	202	MCPDM_DMA_DN_ENABLE \| MCPDM_DMA_UP_ENABLE);
	203	}
	204
	205	/*
	206	* Cleans McPDM uplink, and downlink configuration.
	207	* This function should be called when the stream is closed.
	208	*/
	209	static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
db72c2f8	210	{
f5f9d7bf MLC	211	/* Disable irq request generation for downlink */
	212	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	213	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL);
	214
	215	/* Disable DMA request generation for downlink */
	216	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
	217
	218	/* Disable irq request generation for uplink */
	219	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	220	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	221
	222	/* Disable DMA request generation for uplink */
	223	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
89b0d550 PU	224
	225	/* Disable RX1/2 offset cancellation */
	226	if (mcpdm->dn_rx_offset)
	227	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
f5f9d7bf MLC	228	}
	229
	230	static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
	231	{
	232	struct omap_mcpdm *mcpdm = dev_id;
	233	int irq_status;
	234
	235	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
	236
	237	/* Acknowledge irq event */
	238	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
	239
	240	if (irq_status & MCPDM_DN_IRQ_FULL)
	241	dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
	242
	243	if (irq_status & MCPDM_DN_IRQ_EMPTY)
	244	dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
	245
	246	if (irq_status & MCPDM_DN_IRQ)
	247	dev_dbg(mcpdm->dev, "DN (playback) write request\n");
	248
	249	if (irq_status & MCPDM_UP_IRQ_FULL)
	250	dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
	251
	252	if (irq_status & MCPDM_UP_IRQ_EMPTY)
	253	dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
	254
	255	if (irq_status & MCPDM_UP_IRQ)
	256	dev_dbg(mcpdm->dev, "UP (capture) write request\n");
	257
	258	return IRQ_HANDLED;
db72c2f8 MLC	259	}
db72c2f8 MLC	260
f5f9d7bf	261	static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
db72c2f8 MLC	262	struct snd_soc_dai *dai)
db72c2f8 MLC	263	{
f5f9d7bf	264	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	265
f5f9d7bf MLC	266	mutex_lock(&mcpdm->mutex);
	267
	268	if (!dai->active) {
	269	pm_runtime_get_sync(mcpdm->dev);
	270
	271	/* Enable watch dog for ES above ES 1.0 to avoid saturation */
	272	if (omap_rev() != OMAP4430_REV_ES1_0) {
	273	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	274
	275	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL,
	276	ctrl \| MCPDM_WD_EN);
	277	}
	278	omap_mcpdm_open_streams(mcpdm);
db72c2f8 MLC	279	}
db72c2f8 MLC	280
f5f9d7bf MLC	281	mutex_unlock(&mcpdm->mutex);
	282
	283	return 0;
	284	}
	285
	286	static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
	287	struct snd_soc_dai *dai)
	288	{
	289	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	290
	291	mutex_lock(&mcpdm->mutex);
	292
	293	if (!dai->active) {
	294	if (omap_mcpdm_active(mcpdm)) {
	295	omap_mcpdm_stop(mcpdm);
	296	omap_mcpdm_close_streams(mcpdm);
	297	}
	298
	299	if (!omap_mcpdm_active(mcpdm))
	300	pm_runtime_put_sync(mcpdm->dev);
	301	}
	302
	303	mutex_unlock(&mcpdm->mutex);
db72c2f8 MLC	304	}
	305
	306	static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
	307	struct snd_pcm_hw_params *params,
	308	struct snd_soc_dai *dai)
	309	{
f5f9d7bf	310	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	311	int stream = substream->stream;
f5f9d7bf MLC	312	struct omap_pcm_dma_data *dma_data;
	313	int channels;
	314	int link_mask = 0;
db72c2f8	315
db72c2f8 MLC	316	channels = params_channels(params);
db72c2f8 MLC	317	switch (channels) {
3b5b516f PU	318	case 5:
	319	if (stream == SNDRV_PCM_STREAM_CAPTURE)
	320	/* up to 3 channels for capture */
	321	return -EINVAL;
	322	link_mask \|= 1 << 4;
db72c2f8 MLC	323	case 4:
db72c2f8 MLC	324	if (stream == SNDRV_PCM_STREAM_CAPTURE)
3b5b516f	325	/* up to 3 channels for capture */
db72c2f8 MLC	326	return -EINVAL;
	327	link_mask \|= 1 << 3;
	328	case 3:
db72c2f8 MLC	329	link_mask \|= 1 << 2;
	330	case 2:
	331	link_mask \|= 1 << 1;
	332	case 1:
	333	link_mask \|= 1 << 0;
	334	break;
	335	default:
	336	/* unsupported number of channels */
	337	return -EINVAL;
	338	}
	339
b199adfd	340	dma_data = &omap_mcpdm_dai_dma_params[stream];
b199adfd	341
f5f9d7bf	342	/* Configure McPDM channels, and DMA packet size */
db72c2f8	343	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
f5f9d7bf MLC	344	mcpdm->dn_channels = link_mask << 3;
	345	dma_data->packet_size =
	346	(MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
db72c2f8	347	} else {
f5f9d7bf MLC	348	mcpdm->up_channels = link_mask << 0;
f5f9d7bf MLC	349	dma_data->packet_size = mcpdm->up_threshold * channels;
db72c2f8 MLC	350	}
db72c2f8 MLC	351
b199adfd	352	snd_soc_dai_set_dma_data(dai, substream, dma_data);
f5f9d7bf MLC	353
f5f9d7bf MLC	354	return 0;
db72c2f8 MLC	355	}
db72c2f8 MLC	356
f5f9d7bf	357	static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
db72c2f8 MLC	358	struct snd_soc_dai *dai)
db72c2f8 MLC	359	{
f5f9d7bf	360	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	361
f5f9d7bf MLC	362	if (!omap_mcpdm_active(mcpdm)) {
	363	omap_mcpdm_start(mcpdm);
	364	omap_mcpdm_reg_dump(mcpdm);
	365	}
db72c2f8	366
f5f9d7bf	367	return 0;
db72c2f8 MLC	368	}
db72c2f8 MLC	369
85e7652d	370	static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
db72c2f8 MLC	371	.startup = omap_mcpdm_dai_startup,
db72c2f8 MLC	372	.shutdown = omap_mcpdm_dai_shutdown,
db72c2f8	373	.hw_params = omap_mcpdm_dai_hw_params,
f5f9d7bf	374	.prepare = omap_mcpdm_prepare,
db72c2f8 MLC	375	};
db72c2f8 MLC	376
f5f9d7bf MLC	377	static int omap_mcpdm_probe(struct snd_soc_dai *dai)
	378	{
	379	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	380	int ret;
	381
	382	pm_runtime_enable(mcpdm->dev);
	383
	384	/* Disable lines while request is ongoing */
	385	pm_runtime_get_sync(mcpdm->dev);
	386	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
	387
	388	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
	389	0, "McPDM", (void *)mcpdm);
db72c2f8	390
f5f9d7bf MLC	391	pm_runtime_put_sync(mcpdm->dev);
	392
	393	if (ret) {
	394	dev_err(mcpdm->dev, "Request for IRQ failed\n");
	395	pm_runtime_disable(mcpdm->dev);
	396	}
	397
	398	/* Configure McPDM threshold values */
	399	mcpdm->dn_threshold = 2;
	400	mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
	401	return ret;
	402	}
	403
	404	static int omap_mcpdm_remove(struct snd_soc_dai *dai)
f0fba2ad	405	{
f5f9d7bf MLC	406	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	407
	408	free_irq(mcpdm->irq, (void *)mcpdm);
	409	pm_runtime_disable(mcpdm->dev);
	410
f0fba2ad LG	411	return 0;
	412	}
	413
f5f9d7bf MLC	414	#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	415	#define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
	416
f0fba2ad	417	static struct snd_soc_dai_driver omap_mcpdm_dai = {
f5f9d7bf MLC	418	.probe = omap_mcpdm_probe,
	419	.remove = omap_mcpdm_remove,
	420	.probe_order = SND_SOC_COMP_ORDER_LATE,
	421	.remove_order = SND_SOC_COMP_ORDER_EARLY,
db72c2f8 MLC	422	.playback = {
db72c2f8 MLC	423	.channels_min = 1,
3b5b516f	424	.channels_max = 5,
db72c2f8 MLC	425	.rates = OMAP_MCPDM_RATES,
	426	.formats = OMAP_MCPDM_FORMATS,
	427	},
	428	.capture = {
	429	.channels_min = 1,
3b5b516f	430	.channels_max = 3,
db72c2f8 MLC	431	.rates = OMAP_MCPDM_RATES,
	432	.formats = OMAP_MCPDM_FORMATS,
	433	},
	434	.ops = &omap_mcpdm_dai_ops,
db72c2f8	435	};
f0fba2ad	436
89b0d550 PU	437	void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
	438	u8 rx1, u8 rx2)
	439	{
	440	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
	441
	442	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) \| MCPDM_DNOFST_RX2(rx2);
	443	}
	444	EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
	445
f0fba2ad LG	446	static __devinit int asoc_mcpdm_probe(struct platform_device *pdev)
f0fba2ad LG	447	{
f5f9d7bf MLC	448	struct omap_mcpdm *mcpdm;
	449	struct resource *res;
	450	int ret = 0;
	451
	452	mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
	453	if (!mcpdm)
	454	return -ENOMEM;
	455
	456	platform_set_drvdata(pdev, mcpdm);
	457
	458	mutex_init(&mcpdm->mutex);
	459
	460	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	461	if (res == NULL) {
	462	dev_err(&pdev->dev, "no resource\n");
	463	goto err_res;
	464	}
	465
	466	if (!request_mem_region(res->start, resource_size(res), "McPDM")) {
	467	ret = -EBUSY;
	468	goto err_res;
	469	}
	470
	471	mcpdm->io_base = ioremap(res->start, resource_size(res));
	472	if (!mcpdm->io_base) {
	473	ret = -ENOMEM;
	474	goto err_iomap;
	475	}
	476
	477	mcpdm->irq = platform_get_irq(pdev, 0);
	478	if (mcpdm->irq < 0) {
	479	ret = mcpdm->irq;
	480	goto err_irq;
	481	}
	482
	483	mcpdm->dev = &pdev->dev;
f0fba2ad	484
f0fba2ad	485	ret = snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
f5f9d7bf MLC	486	if (!ret)
	487	return 0;
	488
	489	err_irq:
	490	iounmap(mcpdm->io_base);
	491	err_iomap:
	492	release_mem_region(res->start, resource_size(res));
	493	err_res:
	494	kfree(mcpdm);
f0fba2ad LG	495	return ret;
	496	}
	497
	498	static int __devexit asoc_mcpdm_remove(struct platform_device *pdev)
	499	{
f5f9d7bf MLC	500	struct omap_mcpdm *mcpdm = platform_get_drvdata(pdev);
	501	struct resource *res;
	502
f0fba2ad	503	snd_soc_unregister_dai(&pdev->dev);
f5f9d7bf MLC	504
	505	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	506	iounmap(mcpdm->io_base);
	507	release_mem_region(res->start, resource_size(res));
	508
	509	kfree(mcpdm);
f0fba2ad LG	510	return 0;
	511	}
	512
	513	static struct platform_driver asoc_mcpdm_driver = {
	514	.driver = {
f5f9d7bf MLC	515	.name = "omap-mcpdm",
f5f9d7bf MLC	516	.owner = THIS_MODULE,
f0fba2ad LG	517	},
f0fba2ad LG	518
f5f9d7bf MLC	519	.probe = asoc_mcpdm_probe,
f5f9d7bf MLC	520	.remove = __devexit_p(asoc_mcpdm_remove),
f0fba2ad	521	};
db72c2f8 MLC	522
	523	static int __init snd_omap_mcpdm_init(void)
	524	{
f0fba2ad	525	return platform_driver_register(&asoc_mcpdm_driver);
db72c2f8 MLC	526	}
	527	module_init(snd_omap_mcpdm_init);
	528
	529	static void __exit snd_omap_mcpdm_exit(void)
	530	{
f0fba2ad	531	platform_driver_unregister(&asoc_mcpdm_driver);
db72c2f8 MLC	532	}
	533	module_exit(snd_omap_mcpdm_exit);
	534
f5f9d7bf	535	MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
db72c2f8 MLC	536	MODULE_DESCRIPTION("OMAP PDM SoC Interface");
db72c2f8 MLC	537	MODULE_LICENSE("GPL");