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f5f9d7bf MLC |
1 | /* |
2 | * omap-mcpdm.h | |
3 | * | |
4 | * Copyright (C) 2009 - 2011 Texas Instruments | |
5 | * | |
6 | * Contact: Misael Lopez Cruz <misael.lopez@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #ifndef __OMAP_MCPDM_H__ | |
25 | #define __OMAP_MCPDM_H__ | |
26 | ||
27 | #define MCPDM_REG_REVISION 0x00 | |
28 | #define MCPDM_REG_SYSCONFIG 0x10 | |
29 | #define MCPDM_REG_IRQSTATUS_RAW 0x24 | |
30 | #define MCPDM_REG_IRQSTATUS 0x28 | |
31 | #define MCPDM_REG_IRQENABLE_SET 0x2C | |
32 | #define MCPDM_REG_IRQENABLE_CLR 0x30 | |
33 | #define MCPDM_REG_IRQWAKE_EN 0x34 | |
34 | #define MCPDM_REG_DMAENABLE_SET 0x38 | |
35 | #define MCPDM_REG_DMAENABLE_CLR 0x3C | |
36 | #define MCPDM_REG_DMAWAKEEN 0x40 | |
37 | #define MCPDM_REG_CTRL 0x44 | |
38 | #define MCPDM_REG_DN_DATA 0x48 | |
39 | #define MCPDM_REG_UP_DATA 0x4C | |
40 | #define MCPDM_REG_FIFO_CTRL_DN 0x50 | |
41 | #define MCPDM_REG_FIFO_CTRL_UP 0x54 | |
42 | #define MCPDM_REG_DN_OFFSET 0x58 | |
43 | ||
44 | /* | |
45 | * MCPDM_IRQ bit fields | |
46 | * IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR | |
47 | */ | |
48 | ||
49 | #define MCPDM_DN_IRQ (1 << 0) | |
50 | #define MCPDM_DN_IRQ_EMPTY (1 << 1) | |
51 | #define MCPDM_DN_IRQ_ALMST_EMPTY (1 << 2) | |
52 | #define MCPDM_DN_IRQ_FULL (1 << 3) | |
53 | ||
54 | #define MCPDM_UP_IRQ (1 << 8) | |
55 | #define MCPDM_UP_IRQ_EMPTY (1 << 9) | |
56 | #define MCPDM_UP_IRQ_ALMST_FULL (1 << 10) | |
57 | #define MCPDM_UP_IRQ_FULL (1 << 11) | |
58 | ||
59 | #define MCPDM_DOWNLINK_IRQ_MASK 0x00F | |
60 | #define MCPDM_UPLINK_IRQ_MASK 0xF00 | |
61 | ||
62 | /* | |
63 | * MCPDM_DMAENABLE bit fields | |
64 | */ | |
65 | ||
66 | #define MCPDM_DMA_DN_ENABLE (1 << 0) | |
67 | #define MCPDM_DMA_UP_ENABLE (1 << 1) | |
68 | ||
69 | /* | |
70 | * MCPDM_CTRL bit fields | |
71 | */ | |
72 | ||
73 | #define MCPDM_PDM_UPLINK_EN(x) (1 << (x - 1)) /* ch1 is at bit 0 */ | |
74 | #define MCPDM_PDM_DOWNLINK_EN(x) (1 << (x + 2)) /* ch1 is at bit 3 */ | |
75 | #define MCPDM_PDMOUTFORMAT (1 << 8) | |
76 | #define MCPDM_CMD_INT (1 << 9) | |
77 | #define MCPDM_STATUS_INT (1 << 10) | |
78 | #define MCPDM_SW_UP_RST (1 << 11) | |
79 | #define MCPDM_SW_DN_RST (1 << 12) | |
80 | #define MCPDM_WD_EN (1 << 14) | |
81 | #define MCPDM_PDM_UP_MASK 0x7 | |
82 | #define MCPDM_PDM_DN_MASK (0x1f << 3) | |
83 | ||
84 | ||
85 | #define MCPDM_PDMOUTFORMAT_LJUST (0 << 8) | |
86 | #define MCPDM_PDMOUTFORMAT_RJUST (1 << 8) | |
87 | ||
88 | /* | |
89 | * MCPDM_FIFO_CTRL bit fields | |
90 | */ | |
91 | ||
92 | #define MCPDM_UP_THRES_MAX 0xF | |
93 | #define MCPDM_DN_THRES_MAX 0xF | |
94 | ||
89b0d550 PU |
95 | /* |
96 | * MCPDM_DN_OFFSET bit fields | |
97 | */ | |
98 | ||
99 | #define MCPDM_DN_OFST_RX1_EN (1 << 0) | |
100 | #define MCPDM_DNOFST_RX1(x) ((x & 0x1f) << 1) | |
101 | #define MCPDM_DN_OFST_RX2_EN (1 << 8) | |
102 | #define MCPDM_DNOFST_RX2(x) ((x & 0x1f) << 9) | |
103 | ||
104 | void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd, | |
105 | u8 rx1, u8 rx2); | |
106 | ||
f5f9d7bf | 107 | #endif /* End of __OMAP_MCPDM_H__ */ |