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1b340bd7 MB |
1 | /* |
2 | * pxa-ssp.c -- ALSA Soc Audio Layer | |
3 | * | |
4 | * Copyright 2005,2008 Wolfson Microelectronics PLC. | |
5 | * Author: Liam Girdwood | |
6 | * Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * TODO: | |
14 | * o Test network mode for > 16bit sample size | |
15 | */ | |
16 | ||
17 | #include <linux/init.h> | |
18 | #include <linux/module.h> | |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1b340bd7 MB |
20 | #include <linux/platform_device.h> |
21 | #include <linux/clk.h> | |
22 | #include <linux/io.h> | |
8348c259 | 23 | #include <linux/pxa2xx_ssp.h> |
2023c90c | 24 | #include <linux/of.h> |
d65a1458 | 25 | #include <linux/dmaengine.h> |
1b340bd7 | 26 | |
0664678a PZ |
27 | #include <asm/irq.h> |
28 | ||
1b340bd7 MB |
29 | #include <sound/core.h> |
30 | #include <sound/pcm.h> | |
31 | #include <sound/initval.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/soc.h> | |
34 | #include <sound/pxa2xx-lib.h> | |
d65a1458 | 35 | #include <sound/dmaengine_pcm.h> |
1b340bd7 | 36 | |
dd99a452 | 37 | #include "../../arm/pxa2xx-pcm.h" |
1b340bd7 MB |
38 | #include "pxa-ssp.h" |
39 | ||
40 | /* | |
41 | * SSP audio private data | |
42 | */ | |
43 | struct ssp_priv { | |
f9efc9df | 44 | struct ssp_device *ssp; |
1b340bd7 MB |
45 | unsigned int sysclk; |
46 | int dai_fmt; | |
47 | #ifdef CONFIG_PM | |
f9efc9df EM |
48 | uint32_t cr0; |
49 | uint32_t cr1; | |
50 | uint32_t to; | |
51 | uint32_t psp; | |
1b340bd7 MB |
52 | #endif |
53 | }; | |
54 | ||
1b340bd7 MB |
55 | static void dump_registers(struct ssp_device *ssp) |
56 | { | |
57 | dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n", | |
baffe169 HZ |
58 | pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1), |
59 | pxa_ssp_read_reg(ssp, SSTO)); | |
1b340bd7 MB |
60 | |
61 | dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n", | |
baffe169 HZ |
62 | pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR), |
63 | pxa_ssp_read_reg(ssp, SSACD)); | |
1b340bd7 MB |
64 | } |
65 | ||
baffe169 | 66 | static void pxa_ssp_enable(struct ssp_device *ssp) |
f9efc9df EM |
67 | { |
68 | uint32_t sscr0; | |
69 | ||
70 | sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE; | |
71 | __raw_writel(sscr0, ssp->mmio_base + SSCR0); | |
72 | } | |
73 | ||
baffe169 | 74 | static void pxa_ssp_disable(struct ssp_device *ssp) |
f9efc9df EM |
75 | { |
76 | uint32_t sscr0; | |
77 | ||
78 | sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE; | |
79 | __raw_writel(sscr0, ssp->mmio_base + SSCR0); | |
80 | } | |
81 | ||
d93ca1ae | 82 | static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4, |
d65a1458 | 83 | int out, struct snd_dmaengine_dai_dma_data *dma) |
2d7e71fa | 84 | { |
d65a1458 DM |
85 | dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES : |
86 | DMA_SLAVE_BUSWIDTH_2_BYTES; | |
87 | dma->maxburst = 16; | |
88 | dma->addr = ssp->phys_base + SSDR; | |
2d7e71fa EM |
89 | } |
90 | ||
dee89c4d | 91 | static int pxa_ssp_startup(struct snd_pcm_substream *substream, |
f0fba2ad | 92 | struct snd_soc_dai *cpu_dai) |
1b340bd7 | 93 | { |
f0fba2ad | 94 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 95 | struct ssp_device *ssp = priv->ssp; |
d65a1458 | 96 | struct snd_dmaengine_dai_dma_data *dma; |
1b340bd7 MB |
97 | int ret = 0; |
98 | ||
99 | if (!cpu_dai->active) { | |
6d3efa40 | 100 | clk_prepare_enable(ssp->clk); |
baffe169 | 101 | pxa_ssp_disable(ssp); |
1b340bd7 | 102 | } |
2d7e71fa | 103 | |
d65a1458 | 104 | dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL); |
d93ca1ae | 105 | if (!dma) |
106 | return -ENOMEM; | |
a671468d DM |
107 | |
108 | dma->filter_data = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? | |
109 | &ssp->drcmr_tx : &ssp->drcmr_rx; | |
110 | ||
d65a1458 | 111 | snd_soc_dai_set_dma_data(cpu_dai, substream, dma); |
5f712b2b | 112 | |
1b340bd7 MB |
113 | return ret; |
114 | } | |
115 | ||
dee89c4d | 116 | static void pxa_ssp_shutdown(struct snd_pcm_substream *substream, |
f0fba2ad | 117 | struct snd_soc_dai *cpu_dai) |
1b340bd7 | 118 | { |
f0fba2ad | 119 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 120 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
121 | |
122 | if (!cpu_dai->active) { | |
baffe169 | 123 | pxa_ssp_disable(ssp); |
6d3efa40 | 124 | clk_disable_unprepare(ssp->clk); |
1b340bd7 | 125 | } |
2d7e71fa | 126 | |
5f712b2b DM |
127 | kfree(snd_soc_dai_get_dma_data(cpu_dai, substream)); |
128 | snd_soc_dai_set_dma_data(cpu_dai, substream, NULL); | |
1b340bd7 MB |
129 | } |
130 | ||
131 | #ifdef CONFIG_PM | |
132 | ||
dc7d7b83 | 133 | static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai) |
1b340bd7 | 134 | { |
f0fba2ad | 135 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 136 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
137 | |
138 | if (!cpu_dai->active) | |
6d3efa40 | 139 | clk_prepare_enable(ssp->clk); |
1b340bd7 | 140 | |
f9efc9df EM |
141 | priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0); |
142 | priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1); | |
143 | priv->to = __raw_readl(ssp->mmio_base + SSTO); | |
144 | priv->psp = __raw_readl(ssp->mmio_base + SSPSP); | |
145 | ||
baffe169 | 146 | pxa_ssp_disable(ssp); |
6d3efa40 | 147 | clk_disable_unprepare(ssp->clk); |
1b340bd7 MB |
148 | return 0; |
149 | } | |
150 | ||
dc7d7b83 | 151 | static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai) |
1b340bd7 | 152 | { |
f0fba2ad | 153 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df EM |
154 | struct ssp_device *ssp = priv->ssp; |
155 | uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE; | |
1b340bd7 | 156 | |
6d3efa40 | 157 | clk_prepare_enable(ssp->clk); |
f9efc9df EM |
158 | |
159 | __raw_writel(sssr, ssp->mmio_base + SSSR); | |
f9efc9df EM |
160 | __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0); |
161 | __raw_writel(priv->cr1, ssp->mmio_base + SSCR1); | |
162 | __raw_writel(priv->to, ssp->mmio_base + SSTO); | |
163 | __raw_writel(priv->psp, ssp->mmio_base + SSPSP); | |
026384d6 DM |
164 | |
165 | if (cpu_dai->active) | |
baffe169 | 166 | pxa_ssp_enable(ssp); |
026384d6 | 167 | else |
6d3efa40 | 168 | clk_disable_unprepare(ssp->clk); |
1b340bd7 MB |
169 | |
170 | return 0; | |
171 | } | |
172 | ||
173 | #else | |
174 | #define pxa_ssp_suspend NULL | |
175 | #define pxa_ssp_resume NULL | |
176 | #endif | |
177 | ||
178 | /** | |
179 | * ssp_set_clkdiv - set SSP clock divider | |
180 | * @div: serial clock rate divider | |
181 | */ | |
baffe169 | 182 | static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div) |
1b340bd7 | 183 | { |
baffe169 | 184 | u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
1a297286 | 185 | |
972a55b6 | 186 | if (ssp->type == PXA25x_SSP) { |
1a297286 PZ |
187 | sscr0 &= ~0x0000ff00; |
188 | sscr0 |= ((div - 2)/2) << 8; /* 2..512 */ | |
189 | } else { | |
190 | sscr0 &= ~0x000fff00; | |
191 | sscr0 |= (div - 1) << 8; /* 1..4096 */ | |
192 | } | |
baffe169 | 193 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
1a297286 PZ |
194 | } |
195 | ||
196 | /** | |
baffe169 | 197 | * pxa_ssp_get_clkdiv - get SSP clock divider |
1a297286 | 198 | */ |
baffe169 | 199 | static u32 pxa_ssp_get_scr(struct ssp_device *ssp) |
1a297286 | 200 | { |
baffe169 | 201 | u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
1a297286 | 202 | u32 div; |
1b340bd7 | 203 | |
972a55b6 | 204 | if (ssp->type == PXA25x_SSP) |
1a297286 PZ |
205 | div = ((sscr0 >> 8) & 0xff) * 2 + 2; |
206 | else | |
207 | div = ((sscr0 >> 8) & 0xfff) + 1; | |
208 | return div; | |
1b340bd7 MB |
209 | } |
210 | ||
211 | /* | |
212 | * Set the SSP ports SYSCLK. | |
213 | */ | |
214 | static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
215 | int clk_id, unsigned int freq, int dir) | |
216 | { | |
f0fba2ad | 217 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 218 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
219 | int val; |
220 | ||
baffe169 | 221 | u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & |
20a41eac | 222 | ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); |
1b340bd7 MB |
223 | |
224 | dev_dbg(&ssp->pdev->dev, | |
449bd54d | 225 | "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n", |
1b340bd7 MB |
226 | cpu_dai->id, clk_id, freq); |
227 | ||
228 | switch (clk_id) { | |
229 | case PXA_SSP_CLK_NET_PLL: | |
230 | sscr0 |= SSCR0_MOD; | |
231 | break; | |
232 | case PXA_SSP_CLK_PLL: | |
233 | /* Internal PLL is fixed */ | |
972a55b6 | 234 | if (ssp->type == PXA25x_SSP) |
1b340bd7 MB |
235 | priv->sysclk = 1843200; |
236 | else | |
237 | priv->sysclk = 13000000; | |
238 | break; | |
239 | case PXA_SSP_CLK_EXT: | |
240 | priv->sysclk = freq; | |
241 | sscr0 |= SSCR0_ECS; | |
242 | break; | |
243 | case PXA_SSP_CLK_NET: | |
244 | priv->sysclk = freq; | |
245 | sscr0 |= SSCR0_NCS | SSCR0_MOD; | |
246 | break; | |
247 | case PXA_SSP_CLK_AUDIO: | |
248 | priv->sysclk = 0; | |
baffe169 | 249 | pxa_ssp_set_scr(ssp, 1); |
20a41eac | 250 | sscr0 |= SSCR0_ACS; |
1b340bd7 MB |
251 | break; |
252 | default: | |
253 | return -ENODEV; | |
254 | } | |
255 | ||
256 | /* The SSP clock must be disabled when changing SSP clock mode | |
257 | * on PXA2xx. On PXA3xx it must be enabled when doing so. */ | |
972a55b6 | 258 | if (ssp->type != PXA3xx_SSP) |
6d3efa40 | 259 | clk_disable_unprepare(ssp->clk); |
baffe169 HZ |
260 | val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0; |
261 | pxa_ssp_write_reg(ssp, SSCR0, val); | |
972a55b6 | 262 | if (ssp->type != PXA3xx_SSP) |
6d3efa40 | 263 | clk_prepare_enable(ssp->clk); |
1b340bd7 MB |
264 | |
265 | return 0; | |
266 | } | |
267 | ||
268 | /* | |
269 | * Set the SSP clock dividers. | |
270 | */ | |
271 | static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, | |
272 | int div_id, int div) | |
273 | { | |
f0fba2ad | 274 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 275 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
276 | int val; |
277 | ||
278 | switch (div_id) { | |
279 | case PXA_SSP_AUDIO_DIV_ACDS: | |
baffe169 HZ |
280 | val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div); |
281 | pxa_ssp_write_reg(ssp, SSACD, val); | |
1b340bd7 MB |
282 | break; |
283 | case PXA_SSP_AUDIO_DIV_SCDB: | |
baffe169 | 284 | val = pxa_ssp_read_reg(ssp, SSACD); |
1b340bd7 | 285 | val &= ~SSACD_SCDB; |
972a55b6 | 286 | if (ssp->type == PXA3xx_SSP) |
1b340bd7 | 287 | val &= ~SSACD_SCDX8; |
1b340bd7 MB |
288 | switch (div) { |
289 | case PXA_SSP_CLK_SCDB_1: | |
290 | val |= SSACD_SCDB; | |
291 | break; | |
292 | case PXA_SSP_CLK_SCDB_4: | |
293 | break; | |
1b340bd7 | 294 | case PXA_SSP_CLK_SCDB_8: |
972a55b6 | 295 | if (ssp->type == PXA3xx_SSP) |
1b340bd7 MB |
296 | val |= SSACD_SCDX8; |
297 | else | |
298 | return -EINVAL; | |
299 | break; | |
1b340bd7 MB |
300 | default: |
301 | return -EINVAL; | |
302 | } | |
baffe169 | 303 | pxa_ssp_write_reg(ssp, SSACD, val); |
1b340bd7 MB |
304 | break; |
305 | case PXA_SSP_DIV_SCR: | |
baffe169 | 306 | pxa_ssp_set_scr(ssp, div); |
1b340bd7 MB |
307 | break; |
308 | default: | |
309 | return -ENODEV; | |
310 | } | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
315 | /* | |
316 | * Configure the PLL frequency pxa27x and (afaik - pxa320 only) | |
317 | */ | |
85488037 MB |
318 | static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id, |
319 | int source, unsigned int freq_in, unsigned int freq_out) | |
1b340bd7 | 320 | { |
f0fba2ad | 321 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 322 | struct ssp_device *ssp = priv->ssp; |
baffe169 | 323 | u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70; |
1b340bd7 | 324 | |
972a55b6 | 325 | if (ssp->type == PXA3xx_SSP) |
baffe169 | 326 | pxa_ssp_write_reg(ssp, SSACDD, 0); |
1b340bd7 MB |
327 | |
328 | switch (freq_out) { | |
329 | case 5622000: | |
330 | break; | |
331 | case 11345000: | |
332 | ssacd |= (0x1 << 4); | |
333 | break; | |
334 | case 12235000: | |
335 | ssacd |= (0x2 << 4); | |
336 | break; | |
337 | case 14857000: | |
338 | ssacd |= (0x3 << 4); | |
339 | break; | |
340 | case 32842000: | |
341 | ssacd |= (0x4 << 4); | |
342 | break; | |
343 | case 48000000: | |
344 | ssacd |= (0x5 << 4); | |
345 | break; | |
346 | case 0: | |
347 | /* Disable */ | |
348 | break; | |
349 | ||
350 | default: | |
1b340bd7 MB |
351 | /* PXA3xx has a clock ditherer which can be used to generate |
352 | * a wider range of frequencies - calculate a value for it. | |
353 | */ | |
972a55b6 | 354 | if (ssp->type == PXA3xx_SSP) { |
1b340bd7 MB |
355 | u32 val; |
356 | u64 tmp = 19968; | |
357 | tmp *= 1000000; | |
358 | do_div(tmp, freq_out); | |
359 | val = tmp; | |
360 | ||
a419aef8 | 361 | val = (val << 16) | 64; |
baffe169 | 362 | pxa_ssp_write_reg(ssp, SSACDD, val); |
1b340bd7 MB |
363 | |
364 | ssacd |= (0x6 << 4); | |
365 | ||
366 | dev_dbg(&ssp->pdev->dev, | |
449bd54d | 367 | "Using SSACDD %x to supply %uHz\n", |
1b340bd7 MB |
368 | val, freq_out); |
369 | break; | |
370 | } | |
1b340bd7 MB |
371 | |
372 | return -EINVAL; | |
373 | } | |
374 | ||
baffe169 | 375 | pxa_ssp_write_reg(ssp, SSACD, ssacd); |
1b340bd7 MB |
376 | |
377 | return 0; | |
378 | } | |
379 | ||
380 | /* | |
381 | * Set the active slots in TDM/Network mode | |
382 | */ | |
383 | static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, | |
a5479e38 | 384 | unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) |
1b340bd7 | 385 | { |
f0fba2ad | 386 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 387 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
388 | u32 sscr0; |
389 | ||
baffe169 | 390 | sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
a5479e38 | 391 | sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS); |
1b340bd7 | 392 | |
a5479e38 DR |
393 | /* set slot width */ |
394 | if (slot_width > 16) | |
395 | sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16); | |
396 | else | |
397 | sscr0 |= SSCR0_DataSize(slot_width); | |
398 | ||
399 | if (slots > 1) { | |
400 | /* enable network mode */ | |
401 | sscr0 |= SSCR0_MOD; | |
402 | ||
403 | /* set number of active slots */ | |
404 | sscr0 |= SSCR0_SlotsPerFrm(slots); | |
405 | ||
406 | /* set active slot mask */ | |
baffe169 HZ |
407 | pxa_ssp_write_reg(ssp, SSTSA, tx_mask); |
408 | pxa_ssp_write_reg(ssp, SSRSA, rx_mask); | |
a5479e38 | 409 | } |
baffe169 | 410 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
1b340bd7 | 411 | |
1b340bd7 MB |
412 | return 0; |
413 | } | |
414 | ||
415 | /* | |
416 | * Tristate the SSP DAI lines | |
417 | */ | |
418 | static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai, | |
419 | int tristate) | |
420 | { | |
f0fba2ad | 421 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 422 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
423 | u32 sscr1; |
424 | ||
baffe169 | 425 | sscr1 = pxa_ssp_read_reg(ssp, SSCR1); |
1b340bd7 MB |
426 | if (tristate) |
427 | sscr1 &= ~SSCR1_TTE; | |
428 | else | |
429 | sscr1 |= SSCR1_TTE; | |
baffe169 | 430 | pxa_ssp_write_reg(ssp, SSCR1, sscr1); |
1b340bd7 MB |
431 | |
432 | return 0; | |
433 | } | |
434 | ||
435 | /* | |
436 | * Set up the SSP DAI format. | |
437 | * The SSP Port must be inactive before calling this function as the | |
438 | * physical interface format is changed. | |
439 | */ | |
440 | static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
441 | unsigned int fmt) | |
442 | { | |
f0fba2ad | 443 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 444 | struct ssp_device *ssp = priv->ssp; |
f5d1e5ed | 445 | u32 sscr0, sscr1, sspsp, scfr; |
1b340bd7 | 446 | |
cbf1146d DM |
447 | /* check if we need to change anything at all */ |
448 | if (priv->dai_fmt == fmt) | |
449 | return 0; | |
450 | ||
451 | /* we can only change the settings if the port is not in use */ | |
baffe169 | 452 | if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) { |
cbf1146d DM |
453 | dev_err(&ssp->pdev->dev, |
454 | "can't change hardware dai format: stream is in use"); | |
455 | return -EINVAL; | |
456 | } | |
457 | ||
1b340bd7 | 458 | /* reset port settings */ |
baffe169 | 459 | sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & |
f5d1e5ed | 460 | ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); |
1b340bd7 MB |
461 | sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7); |
462 | sspsp = 0; | |
463 | ||
464 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
465 | case SND_SOC_DAIFMT_CBM_CFM: | |
f5d1e5ed | 466 | sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR; |
1b340bd7 MB |
467 | break; |
468 | case SND_SOC_DAIFMT_CBM_CFS: | |
f5d1e5ed | 469 | sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR; |
1b340bd7 MB |
470 | break; |
471 | case SND_SOC_DAIFMT_CBS_CFS: | |
472 | break; | |
473 | default: | |
474 | return -EINVAL; | |
475 | } | |
476 | ||
fa44c077 DR |
477 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
478 | case SND_SOC_DAIFMT_NB_NF: | |
479 | sspsp |= SSPSP_SFRMP; | |
480 | break; | |
481 | case SND_SOC_DAIFMT_NB_IF: | |
482 | break; | |
483 | case SND_SOC_DAIFMT_IB_IF: | |
484 | sspsp |= SSPSP_SCMODE(2); | |
485 | break; | |
486 | case SND_SOC_DAIFMT_IB_NF: | |
487 | sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP; | |
488 | break; | |
489 | default: | |
490 | return -EINVAL; | |
491 | } | |
1b340bd7 MB |
492 | |
493 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
494 | case SND_SOC_DAIFMT_I2S: | |
72d74664 | 495 | sscr0 |= SSCR0_PSP; |
1b340bd7 | 496 | sscr1 |= SSCR1_RWOT | SSCR1_TRAIL; |
0ce36c5f | 497 | /* See hw_params() */ |
1b340bd7 MB |
498 | break; |
499 | ||
500 | case SND_SOC_DAIFMT_DSP_A: | |
501 | sspsp |= SSPSP_FSRT; | |
502 | case SND_SOC_DAIFMT_DSP_B: | |
503 | sscr0 |= SSCR0_MOD | SSCR0_PSP; | |
504 | sscr1 |= SSCR1_TRAIL | SSCR1_RWOT; | |
1b340bd7 MB |
505 | break; |
506 | ||
507 | default: | |
508 | return -EINVAL; | |
509 | } | |
510 | ||
baffe169 HZ |
511 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
512 | pxa_ssp_write_reg(ssp, SSCR1, sscr1); | |
513 | pxa_ssp_write_reg(ssp, SSPSP, sspsp); | |
1b340bd7 | 514 | |
f5d1e5ed HZ |
515 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
516 | case SND_SOC_DAIFMT_CBM_CFM: | |
517 | case SND_SOC_DAIFMT_CBM_CFS: | |
518 | scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR; | |
519 | pxa_ssp_write_reg(ssp, SSCR1, scfr); | |
520 | ||
521 | while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY) | |
522 | cpu_relax(); | |
523 | break; | |
524 | } | |
525 | ||
1b340bd7 MB |
526 | dump_registers(ssp); |
527 | ||
528 | /* Since we are configuring the timings for the format by hand | |
529 | * we have to defer some things until hw_params() where we | |
530 | * know parameters like the sample size. | |
531 | */ | |
532 | priv->dai_fmt = fmt; | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
537 | /* | |
538 | * Set the SSP audio DMA parameters and sample size. | |
539 | * Can be called multiple times by oss emulation. | |
540 | */ | |
541 | static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d | 542 | struct snd_pcm_hw_params *params, |
f0fba2ad | 543 | struct snd_soc_dai *cpu_dai) |
1b340bd7 | 544 | { |
f0fba2ad | 545 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 546 | struct ssp_device *ssp = priv->ssp; |
2d7e71fa | 547 | int chn = params_channels(params); |
1b340bd7 MB |
548 | u32 sscr0; |
549 | u32 sspsp; | |
550 | int width = snd_pcm_format_physical_width(params_format(params)); | |
baffe169 | 551 | int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf; |
d65a1458 | 552 | struct snd_dmaengine_dai_dma_data *dma_data; |
5f712b2b | 553 | |
f0fba2ad | 554 | dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream); |
1b340bd7 | 555 | |
92429069 PZ |
556 | /* Network mode with one active slot (ttsa == 1) can be used |
557 | * to force 16-bit frame width on the wire (for S16_LE), even | |
558 | * with two channels. Use 16-bit DMA transfers for this case. | |
559 | */ | |
d93ca1ae | 560 | pxa_ssp_set_dma_params(ssp, |
561 | ((chn == 2) && (ttsa != 1)) || (width == 32), | |
562 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data); | |
5f712b2b | 563 | |
1b340bd7 | 564 | /* we can only change the settings if the port is not in use */ |
baffe169 | 565 | if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) |
1b340bd7 MB |
566 | return 0; |
567 | ||
568 | /* clear selected SSP bits */ | |
baffe169 | 569 | sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS); |
1b340bd7 MB |
570 | |
571 | /* bit size */ | |
1b340bd7 MB |
572 | switch (params_format(params)) { |
573 | case SNDRV_PCM_FORMAT_S16_LE: | |
972a55b6 | 574 | if (ssp->type == PXA3xx_SSP) |
1b340bd7 | 575 | sscr0 |= SSCR0_FPCKE; |
1b340bd7 | 576 | sscr0 |= SSCR0_DataSize(16); |
1b340bd7 MB |
577 | break; |
578 | case SNDRV_PCM_FORMAT_S24_LE: | |
579 | sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8)); | |
1b340bd7 MB |
580 | break; |
581 | case SNDRV_PCM_FORMAT_S32_LE: | |
582 | sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16)); | |
1b340bd7 MB |
583 | break; |
584 | } | |
baffe169 | 585 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
1b340bd7 MB |
586 | |
587 | switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
588 | case SND_SOC_DAIFMT_I2S: | |
baffe169 | 589 | sspsp = pxa_ssp_read_reg(ssp, SSPSP); |
72d74664 | 590 | |
baffe169 | 591 | if ((pxa_ssp_get_scr(ssp) == 4) && (width == 16)) { |
72d74664 DM |
592 | /* This is a special case where the bitclk is 64fs |
593 | * and we're not dealing with 2*32 bits of audio | |
594 | * samples. | |
595 | * | |
596 | * The SSP values used for that are all found out by | |
597 | * trying and failing a lot; some of the registers | |
598 | * needed for that mode are only available on PXA3xx. | |
599 | */ | |
972a55b6 | 600 | if (ssp->type != PXA3xx_SSP) |
72d74664 DM |
601 | return -EINVAL; |
602 | ||
603 | sspsp |= SSPSP_SFRMWDTH(width * 2); | |
604 | sspsp |= SSPSP_SFRMDLY(width * 4); | |
605 | sspsp |= SSPSP_EDMYSTOP(3); | |
606 | sspsp |= SSPSP_DMYSTOP(3); | |
607 | sspsp |= SSPSP_DMYSTRT(1); | |
0ce36c5f MB |
608 | } else { |
609 | /* The frame width is the width the LRCLK is | |
610 | * asserted for; the delay is expressed in | |
611 | * half cycle units. We need the extra cycle | |
612 | * because the data starts clocking out one BCLK | |
613 | * after LRCLK changes polarity. | |
614 | */ | |
615 | sspsp |= SSPSP_SFRMWDTH(width + 1); | |
616 | sspsp |= SSPSP_SFRMDLY((width + 1) * 2); | |
617 | sspsp |= SSPSP_DMYSTRT(1); | |
618 | } | |
72d74664 | 619 | |
baffe169 | 620 | pxa_ssp_write_reg(ssp, SSPSP, sspsp); |
1b340bd7 MB |
621 | break; |
622 | default: | |
623 | break; | |
624 | } | |
625 | ||
72d74664 | 626 | /* When we use a network mode, we always require TDM slots |
1b340bd7 MB |
627 | * - complain loudly and fail if they've not been set up yet. |
628 | */ | |
92429069 | 629 | if ((sscr0 & SSCR0_MOD) && !ttsa) { |
1b340bd7 MB |
630 | dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n"); |
631 | return -EINVAL; | |
632 | } | |
633 | ||
634 | dump_registers(ssp); | |
635 | ||
636 | return 0; | |
637 | } | |
638 | ||
273b72c8 DM |
639 | static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream, |
640 | struct ssp_device *ssp, int value) | |
641 | { | |
642 | uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0); | |
643 | uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1); | |
644 | uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP); | |
645 | uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR); | |
646 | ||
647 | if (value && (sscr0 & SSCR0_SSE)) | |
648 | pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE); | |
649 | ||
650 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
651 | if (value) | |
652 | sscr1 |= SSCR1_TSRE; | |
653 | else | |
654 | sscr1 &= ~SSCR1_TSRE; | |
655 | } else { | |
656 | if (value) | |
657 | sscr1 |= SSCR1_RSRE; | |
658 | else | |
659 | sscr1 &= ~SSCR1_RSRE; | |
660 | } | |
661 | ||
662 | pxa_ssp_write_reg(ssp, SSCR1, sscr1); | |
663 | ||
664 | if (value) { | |
665 | pxa_ssp_write_reg(ssp, SSSR, sssr); | |
666 | pxa_ssp_write_reg(ssp, SSPSP, sspsp); | |
667 | pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE); | |
668 | } | |
669 | } | |
670 | ||
dee89c4d | 671 | static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd, |
f0fba2ad | 672 | struct snd_soc_dai *cpu_dai) |
1b340bd7 | 673 | { |
1b340bd7 | 674 | int ret = 0; |
f0fba2ad | 675 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 676 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
677 | int val; |
678 | ||
679 | switch (cmd) { | |
680 | case SNDRV_PCM_TRIGGER_RESUME: | |
baffe169 | 681 | pxa_ssp_enable(ssp); |
1b340bd7 MB |
682 | break; |
683 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
273b72c8 | 684 | pxa_ssp_set_running_bit(substream, ssp, 1); |
baffe169 HZ |
685 | val = pxa_ssp_read_reg(ssp, SSSR); |
686 | pxa_ssp_write_reg(ssp, SSSR, val); | |
1b340bd7 MB |
687 | break; |
688 | case SNDRV_PCM_TRIGGER_START: | |
273b72c8 | 689 | pxa_ssp_set_running_bit(substream, ssp, 1); |
1b340bd7 MB |
690 | break; |
691 | case SNDRV_PCM_TRIGGER_STOP: | |
273b72c8 | 692 | pxa_ssp_set_running_bit(substream, ssp, 0); |
1b340bd7 MB |
693 | break; |
694 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
baffe169 | 695 | pxa_ssp_disable(ssp); |
1b340bd7 MB |
696 | break; |
697 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
273b72c8 | 698 | pxa_ssp_set_running_bit(substream, ssp, 0); |
1b340bd7 MB |
699 | break; |
700 | ||
701 | default: | |
702 | ret = -EINVAL; | |
703 | } | |
704 | ||
705 | dump_registers(ssp); | |
706 | ||
707 | return ret; | |
708 | } | |
709 | ||
f0fba2ad | 710 | static int pxa_ssp_probe(struct snd_soc_dai *dai) |
1b340bd7 | 711 | { |
2023c90c | 712 | struct device *dev = dai->dev; |
1b340bd7 MB |
713 | struct ssp_priv *priv; |
714 | int ret; | |
715 | ||
716 | priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL); | |
717 | if (!priv) | |
718 | return -ENOMEM; | |
719 | ||
2023c90c DM |
720 | if (dev->of_node) { |
721 | struct device_node *ssp_handle; | |
722 | ||
723 | ssp_handle = of_parse_phandle(dev->of_node, "port", 0); | |
724 | if (!ssp_handle) { | |
725 | dev_err(dev, "unable to get 'port' phandle\n"); | |
45487289 DC |
726 | ret = -ENODEV; |
727 | goto err_priv; | |
2023c90c DM |
728 | } |
729 | ||
730 | priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio"); | |
731 | if (priv->ssp == NULL) { | |
732 | ret = -ENODEV; | |
733 | goto err_priv; | |
734 | } | |
735 | } else { | |
736 | priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio"); | |
737 | if (priv->ssp == NULL) { | |
738 | ret = -ENODEV; | |
739 | goto err_priv; | |
740 | } | |
1b340bd7 MB |
741 | } |
742 | ||
a5735b7e | 743 | priv->dai_fmt = (unsigned int) -1; |
f0fba2ad | 744 | snd_soc_dai_set_drvdata(dai, priv); |
1b340bd7 MB |
745 | |
746 | return 0; | |
747 | ||
748 | err_priv: | |
749 | kfree(priv); | |
750 | return ret; | |
751 | } | |
752 | ||
f0fba2ad | 753 | static int pxa_ssp_remove(struct snd_soc_dai *dai) |
1b340bd7 | 754 | { |
f0fba2ad LG |
755 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai); |
756 | ||
baffe169 | 757 | pxa_ssp_free(priv->ssp); |
014a2755 | 758 | kfree(priv); |
f0fba2ad | 759 | return 0; |
1b340bd7 MB |
760 | } |
761 | ||
762 | #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ | |
763 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ | |
8d8bf58b QZ |
764 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ |
765 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \ | |
1b340bd7 MB |
766 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) |
767 | ||
9301503a | 768 | #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) |
1b340bd7 | 769 | |
85e7652d | 770 | static const struct snd_soc_dai_ops pxa_ssp_dai_ops = { |
6335d055 EM |
771 | .startup = pxa_ssp_startup, |
772 | .shutdown = pxa_ssp_shutdown, | |
773 | .trigger = pxa_ssp_trigger, | |
774 | .hw_params = pxa_ssp_hw_params, | |
775 | .set_sysclk = pxa_ssp_set_dai_sysclk, | |
776 | .set_clkdiv = pxa_ssp_set_dai_clkdiv, | |
777 | .set_pll = pxa_ssp_set_dai_pll, | |
778 | .set_fmt = pxa_ssp_set_dai_fmt, | |
779 | .set_tdm_slot = pxa_ssp_set_dai_tdm_slot, | |
780 | .set_tristate = pxa_ssp_set_dai_tristate, | |
781 | }; | |
782 | ||
f0fba2ad | 783 | static struct snd_soc_dai_driver pxa_ssp_dai = { |
1b340bd7 MB |
784 | .probe = pxa_ssp_probe, |
785 | .remove = pxa_ssp_remove, | |
786 | .suspend = pxa_ssp_suspend, | |
787 | .resume = pxa_ssp_resume, | |
788 | .playback = { | |
789 | .channels_min = 1, | |
f34762b6 | 790 | .channels_max = 8, |
1b340bd7 MB |
791 | .rates = PXA_SSP_RATES, |
792 | .formats = PXA_SSP_FORMATS, | |
793 | }, | |
794 | .capture = { | |
795 | .channels_min = 1, | |
f34762b6 | 796 | .channels_max = 8, |
1b340bd7 MB |
797 | .rates = PXA_SSP_RATES, |
798 | .formats = PXA_SSP_FORMATS, | |
799 | }, | |
6335d055 | 800 | .ops = &pxa_ssp_dai_ops, |
f0fba2ad LG |
801 | }; |
802 | ||
e580f1ce KM |
803 | static const struct snd_soc_component_driver pxa_ssp_component = { |
804 | .name = "pxa-ssp", | |
805 | }; | |
806 | ||
2023c90c DM |
807 | #ifdef CONFIG_OF |
808 | static const struct of_device_id pxa_ssp_of_ids[] = { | |
809 | { .compatible = "mrvl,pxa-ssp-dai" }, | |
4c715c75 | 810 | {} |
2023c90c DM |
811 | }; |
812 | #endif | |
813 | ||
570f6fe1 | 814 | static int asoc_ssp_probe(struct platform_device *pdev) |
f0fba2ad | 815 | { |
637ce53a AL |
816 | return devm_snd_soc_register_component(&pdev->dev, &pxa_ssp_component, |
817 | &pxa_ssp_dai, 1); | |
f0fba2ad LG |
818 | } |
819 | ||
820 | static struct platform_driver asoc_ssp_driver = { | |
821 | .driver = { | |
2023c90c | 822 | .name = "pxa-ssp-dai", |
2023c90c | 823 | .of_match_table = of_match_ptr(pxa_ssp_of_ids), |
1b340bd7 | 824 | }, |
f0fba2ad LG |
825 | |
826 | .probe = asoc_ssp_probe, | |
1b340bd7 | 827 | }; |
1b340bd7 | 828 | |
2f702a19 | 829 | module_platform_driver(asoc_ssp_driver); |
3f4b783c | 830 | |
1b340bd7 MB |
831 | /* Module information */ |
832 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
833 | MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface"); | |
834 | MODULE_LICENSE("GPL"); |