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1b340bd7 MB |
1 | /* |
2 | * pxa-ssp.c -- ALSA Soc Audio Layer | |
3 | * | |
4 | * Copyright 2005,2008 Wolfson Microelectronics PLC. | |
5 | * Author: Liam Girdwood | |
6 | * Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * TODO: | |
14 | * o Test network mode for > 16bit sample size | |
15 | */ | |
16 | ||
17 | #include <linux/init.h> | |
18 | #include <linux/module.h> | |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1b340bd7 MB |
20 | #include <linux/platform_device.h> |
21 | #include <linux/clk.h> | |
22 | #include <linux/io.h> | |
8348c259 | 23 | #include <linux/pxa2xx_ssp.h> |
2023c90c | 24 | #include <linux/of.h> |
d65a1458 | 25 | #include <linux/dmaengine.h> |
1b340bd7 | 26 | |
0664678a PZ |
27 | #include <asm/irq.h> |
28 | ||
1b340bd7 MB |
29 | #include <sound/core.h> |
30 | #include <sound/pcm.h> | |
31 | #include <sound/initval.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/soc.h> | |
34 | #include <sound/pxa2xx-lib.h> | |
d65a1458 | 35 | #include <sound/dmaengine_pcm.h> |
1b340bd7 MB |
36 | |
37 | #include <mach/hardware.h> | |
1b340bd7 | 38 | |
dd99a452 | 39 | #include "../../arm/pxa2xx-pcm.h" |
1b340bd7 MB |
40 | #include "pxa-ssp.h" |
41 | ||
42 | /* | |
43 | * SSP audio private data | |
44 | */ | |
45 | struct ssp_priv { | |
f9efc9df | 46 | struct ssp_device *ssp; |
1b340bd7 MB |
47 | unsigned int sysclk; |
48 | int dai_fmt; | |
49 | #ifdef CONFIG_PM | |
f9efc9df EM |
50 | uint32_t cr0; |
51 | uint32_t cr1; | |
52 | uint32_t to; | |
53 | uint32_t psp; | |
1b340bd7 MB |
54 | #endif |
55 | }; | |
56 | ||
1b340bd7 MB |
57 | static void dump_registers(struct ssp_device *ssp) |
58 | { | |
59 | dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n", | |
baffe169 HZ |
60 | pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1), |
61 | pxa_ssp_read_reg(ssp, SSTO)); | |
1b340bd7 MB |
62 | |
63 | dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n", | |
baffe169 HZ |
64 | pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR), |
65 | pxa_ssp_read_reg(ssp, SSACD)); | |
1b340bd7 MB |
66 | } |
67 | ||
baffe169 | 68 | static void pxa_ssp_enable(struct ssp_device *ssp) |
f9efc9df EM |
69 | { |
70 | uint32_t sscr0; | |
71 | ||
72 | sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE; | |
73 | __raw_writel(sscr0, ssp->mmio_base + SSCR0); | |
74 | } | |
75 | ||
baffe169 | 76 | static void pxa_ssp_disable(struct ssp_device *ssp) |
f9efc9df EM |
77 | { |
78 | uint32_t sscr0; | |
79 | ||
80 | sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE; | |
81 | __raw_writel(sscr0, ssp->mmio_base + SSCR0); | |
82 | } | |
83 | ||
d93ca1ae | 84 | static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4, |
d65a1458 | 85 | int out, struct snd_dmaengine_dai_dma_data *dma) |
2d7e71fa | 86 | { |
d65a1458 DM |
87 | dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES : |
88 | DMA_SLAVE_BUSWIDTH_2_BYTES; | |
89 | dma->maxburst = 16; | |
90 | dma->addr = ssp->phys_base + SSDR; | |
2d7e71fa EM |
91 | } |
92 | ||
dee89c4d | 93 | static int pxa_ssp_startup(struct snd_pcm_substream *substream, |
f0fba2ad | 94 | struct snd_soc_dai *cpu_dai) |
1b340bd7 | 95 | { |
f0fba2ad | 96 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 97 | struct ssp_device *ssp = priv->ssp; |
d65a1458 | 98 | struct snd_dmaengine_dai_dma_data *dma; |
1b340bd7 MB |
99 | int ret = 0; |
100 | ||
101 | if (!cpu_dai->active) { | |
f9efc9df | 102 | clk_enable(ssp->clk); |
baffe169 | 103 | pxa_ssp_disable(ssp); |
1b340bd7 | 104 | } |
2d7e71fa | 105 | |
d65a1458 | 106 | dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL); |
d93ca1ae | 107 | if (!dma) |
108 | return -ENOMEM; | |
a671468d DM |
109 | |
110 | dma->filter_data = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? | |
111 | &ssp->drcmr_tx : &ssp->drcmr_rx; | |
112 | ||
d65a1458 | 113 | snd_soc_dai_set_dma_data(cpu_dai, substream, dma); |
5f712b2b | 114 | |
1b340bd7 MB |
115 | return ret; |
116 | } | |
117 | ||
dee89c4d | 118 | static void pxa_ssp_shutdown(struct snd_pcm_substream *substream, |
f0fba2ad | 119 | struct snd_soc_dai *cpu_dai) |
1b340bd7 | 120 | { |
f0fba2ad | 121 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 122 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
123 | |
124 | if (!cpu_dai->active) { | |
baffe169 | 125 | pxa_ssp_disable(ssp); |
f9efc9df | 126 | clk_disable(ssp->clk); |
1b340bd7 | 127 | } |
2d7e71fa | 128 | |
5f712b2b DM |
129 | kfree(snd_soc_dai_get_dma_data(cpu_dai, substream)); |
130 | snd_soc_dai_set_dma_data(cpu_dai, substream, NULL); | |
1b340bd7 MB |
131 | } |
132 | ||
133 | #ifdef CONFIG_PM | |
134 | ||
dc7d7b83 | 135 | static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai) |
1b340bd7 | 136 | { |
f0fba2ad | 137 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 138 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
139 | |
140 | if (!cpu_dai->active) | |
988addf8 | 141 | clk_enable(ssp->clk); |
1b340bd7 | 142 | |
f9efc9df EM |
143 | priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0); |
144 | priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1); | |
145 | priv->to = __raw_readl(ssp->mmio_base + SSTO); | |
146 | priv->psp = __raw_readl(ssp->mmio_base + SSPSP); | |
147 | ||
baffe169 | 148 | pxa_ssp_disable(ssp); |
f9efc9df | 149 | clk_disable(ssp->clk); |
1b340bd7 MB |
150 | return 0; |
151 | } | |
152 | ||
dc7d7b83 | 153 | static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai) |
1b340bd7 | 154 | { |
f0fba2ad | 155 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df EM |
156 | struct ssp_device *ssp = priv->ssp; |
157 | uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE; | |
1b340bd7 | 158 | |
f9efc9df EM |
159 | clk_enable(ssp->clk); |
160 | ||
161 | __raw_writel(sssr, ssp->mmio_base + SSSR); | |
f9efc9df EM |
162 | __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0); |
163 | __raw_writel(priv->cr1, ssp->mmio_base + SSCR1); | |
164 | __raw_writel(priv->to, ssp->mmio_base + SSTO); | |
165 | __raw_writel(priv->psp, ssp->mmio_base + SSPSP); | |
026384d6 DM |
166 | |
167 | if (cpu_dai->active) | |
baffe169 | 168 | pxa_ssp_enable(ssp); |
026384d6 | 169 | else |
988addf8 | 170 | clk_disable(ssp->clk); |
1b340bd7 MB |
171 | |
172 | return 0; | |
173 | } | |
174 | ||
175 | #else | |
176 | #define pxa_ssp_suspend NULL | |
177 | #define pxa_ssp_resume NULL | |
178 | #endif | |
179 | ||
180 | /** | |
181 | * ssp_set_clkdiv - set SSP clock divider | |
182 | * @div: serial clock rate divider | |
183 | */ | |
baffe169 | 184 | static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div) |
1b340bd7 | 185 | { |
baffe169 | 186 | u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
1a297286 | 187 | |
972a55b6 | 188 | if (ssp->type == PXA25x_SSP) { |
1a297286 PZ |
189 | sscr0 &= ~0x0000ff00; |
190 | sscr0 |= ((div - 2)/2) << 8; /* 2..512 */ | |
191 | } else { | |
192 | sscr0 &= ~0x000fff00; | |
193 | sscr0 |= (div - 1) << 8; /* 1..4096 */ | |
194 | } | |
baffe169 | 195 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
1a297286 PZ |
196 | } |
197 | ||
198 | /** | |
baffe169 | 199 | * pxa_ssp_get_clkdiv - get SSP clock divider |
1a297286 | 200 | */ |
baffe169 | 201 | static u32 pxa_ssp_get_scr(struct ssp_device *ssp) |
1a297286 | 202 | { |
baffe169 | 203 | u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
1a297286 | 204 | u32 div; |
1b340bd7 | 205 | |
972a55b6 | 206 | if (ssp->type == PXA25x_SSP) |
1a297286 PZ |
207 | div = ((sscr0 >> 8) & 0xff) * 2 + 2; |
208 | else | |
209 | div = ((sscr0 >> 8) & 0xfff) + 1; | |
210 | return div; | |
1b340bd7 MB |
211 | } |
212 | ||
213 | /* | |
214 | * Set the SSP ports SYSCLK. | |
215 | */ | |
216 | static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
217 | int clk_id, unsigned int freq, int dir) | |
218 | { | |
f0fba2ad | 219 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 220 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
221 | int val; |
222 | ||
baffe169 | 223 | u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & |
20a41eac | 224 | ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); |
1b340bd7 MB |
225 | |
226 | dev_dbg(&ssp->pdev->dev, | |
449bd54d | 227 | "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n", |
1b340bd7 MB |
228 | cpu_dai->id, clk_id, freq); |
229 | ||
230 | switch (clk_id) { | |
231 | case PXA_SSP_CLK_NET_PLL: | |
232 | sscr0 |= SSCR0_MOD; | |
233 | break; | |
234 | case PXA_SSP_CLK_PLL: | |
235 | /* Internal PLL is fixed */ | |
972a55b6 | 236 | if (ssp->type == PXA25x_SSP) |
1b340bd7 MB |
237 | priv->sysclk = 1843200; |
238 | else | |
239 | priv->sysclk = 13000000; | |
240 | break; | |
241 | case PXA_SSP_CLK_EXT: | |
242 | priv->sysclk = freq; | |
243 | sscr0 |= SSCR0_ECS; | |
244 | break; | |
245 | case PXA_SSP_CLK_NET: | |
246 | priv->sysclk = freq; | |
247 | sscr0 |= SSCR0_NCS | SSCR0_MOD; | |
248 | break; | |
249 | case PXA_SSP_CLK_AUDIO: | |
250 | priv->sysclk = 0; | |
baffe169 | 251 | pxa_ssp_set_scr(ssp, 1); |
20a41eac | 252 | sscr0 |= SSCR0_ACS; |
1b340bd7 MB |
253 | break; |
254 | default: | |
255 | return -ENODEV; | |
256 | } | |
257 | ||
258 | /* The SSP clock must be disabled when changing SSP clock mode | |
259 | * on PXA2xx. On PXA3xx it must be enabled when doing so. */ | |
972a55b6 | 260 | if (ssp->type != PXA3xx_SSP) |
f9efc9df | 261 | clk_disable(ssp->clk); |
baffe169 HZ |
262 | val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0; |
263 | pxa_ssp_write_reg(ssp, SSCR0, val); | |
972a55b6 | 264 | if (ssp->type != PXA3xx_SSP) |
f9efc9df | 265 | clk_enable(ssp->clk); |
1b340bd7 MB |
266 | |
267 | return 0; | |
268 | } | |
269 | ||
270 | /* | |
271 | * Set the SSP clock dividers. | |
272 | */ | |
273 | static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, | |
274 | int div_id, int div) | |
275 | { | |
f0fba2ad | 276 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 277 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
278 | int val; |
279 | ||
280 | switch (div_id) { | |
281 | case PXA_SSP_AUDIO_DIV_ACDS: | |
baffe169 HZ |
282 | val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div); |
283 | pxa_ssp_write_reg(ssp, SSACD, val); | |
1b340bd7 MB |
284 | break; |
285 | case PXA_SSP_AUDIO_DIV_SCDB: | |
baffe169 | 286 | val = pxa_ssp_read_reg(ssp, SSACD); |
1b340bd7 | 287 | val &= ~SSACD_SCDB; |
972a55b6 | 288 | if (ssp->type == PXA3xx_SSP) |
1b340bd7 | 289 | val &= ~SSACD_SCDX8; |
1b340bd7 MB |
290 | switch (div) { |
291 | case PXA_SSP_CLK_SCDB_1: | |
292 | val |= SSACD_SCDB; | |
293 | break; | |
294 | case PXA_SSP_CLK_SCDB_4: | |
295 | break; | |
1b340bd7 | 296 | case PXA_SSP_CLK_SCDB_8: |
972a55b6 | 297 | if (ssp->type == PXA3xx_SSP) |
1b340bd7 MB |
298 | val |= SSACD_SCDX8; |
299 | else | |
300 | return -EINVAL; | |
301 | break; | |
1b340bd7 MB |
302 | default: |
303 | return -EINVAL; | |
304 | } | |
baffe169 | 305 | pxa_ssp_write_reg(ssp, SSACD, val); |
1b340bd7 MB |
306 | break; |
307 | case PXA_SSP_DIV_SCR: | |
baffe169 | 308 | pxa_ssp_set_scr(ssp, div); |
1b340bd7 MB |
309 | break; |
310 | default: | |
311 | return -ENODEV; | |
312 | } | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
317 | /* | |
318 | * Configure the PLL frequency pxa27x and (afaik - pxa320 only) | |
319 | */ | |
85488037 MB |
320 | static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id, |
321 | int source, unsigned int freq_in, unsigned int freq_out) | |
1b340bd7 | 322 | { |
f0fba2ad | 323 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 324 | struct ssp_device *ssp = priv->ssp; |
baffe169 | 325 | u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70; |
1b340bd7 | 326 | |
972a55b6 | 327 | if (ssp->type == PXA3xx_SSP) |
baffe169 | 328 | pxa_ssp_write_reg(ssp, SSACDD, 0); |
1b340bd7 MB |
329 | |
330 | switch (freq_out) { | |
331 | case 5622000: | |
332 | break; | |
333 | case 11345000: | |
334 | ssacd |= (0x1 << 4); | |
335 | break; | |
336 | case 12235000: | |
337 | ssacd |= (0x2 << 4); | |
338 | break; | |
339 | case 14857000: | |
340 | ssacd |= (0x3 << 4); | |
341 | break; | |
342 | case 32842000: | |
343 | ssacd |= (0x4 << 4); | |
344 | break; | |
345 | case 48000000: | |
346 | ssacd |= (0x5 << 4); | |
347 | break; | |
348 | case 0: | |
349 | /* Disable */ | |
350 | break; | |
351 | ||
352 | default: | |
1b340bd7 MB |
353 | /* PXA3xx has a clock ditherer which can be used to generate |
354 | * a wider range of frequencies - calculate a value for it. | |
355 | */ | |
972a55b6 | 356 | if (ssp->type == PXA3xx_SSP) { |
1b340bd7 MB |
357 | u32 val; |
358 | u64 tmp = 19968; | |
359 | tmp *= 1000000; | |
360 | do_div(tmp, freq_out); | |
361 | val = tmp; | |
362 | ||
a419aef8 | 363 | val = (val << 16) | 64; |
baffe169 | 364 | pxa_ssp_write_reg(ssp, SSACDD, val); |
1b340bd7 MB |
365 | |
366 | ssacd |= (0x6 << 4); | |
367 | ||
368 | dev_dbg(&ssp->pdev->dev, | |
449bd54d | 369 | "Using SSACDD %x to supply %uHz\n", |
1b340bd7 MB |
370 | val, freq_out); |
371 | break; | |
372 | } | |
1b340bd7 MB |
373 | |
374 | return -EINVAL; | |
375 | } | |
376 | ||
baffe169 | 377 | pxa_ssp_write_reg(ssp, SSACD, ssacd); |
1b340bd7 MB |
378 | |
379 | return 0; | |
380 | } | |
381 | ||
382 | /* | |
383 | * Set the active slots in TDM/Network mode | |
384 | */ | |
385 | static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, | |
a5479e38 | 386 | unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) |
1b340bd7 | 387 | { |
f0fba2ad | 388 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 389 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
390 | u32 sscr0; |
391 | ||
baffe169 | 392 | sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
a5479e38 | 393 | sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS); |
1b340bd7 | 394 | |
a5479e38 DR |
395 | /* set slot width */ |
396 | if (slot_width > 16) | |
397 | sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16); | |
398 | else | |
399 | sscr0 |= SSCR0_DataSize(slot_width); | |
400 | ||
401 | if (slots > 1) { | |
402 | /* enable network mode */ | |
403 | sscr0 |= SSCR0_MOD; | |
404 | ||
405 | /* set number of active slots */ | |
406 | sscr0 |= SSCR0_SlotsPerFrm(slots); | |
407 | ||
408 | /* set active slot mask */ | |
baffe169 HZ |
409 | pxa_ssp_write_reg(ssp, SSTSA, tx_mask); |
410 | pxa_ssp_write_reg(ssp, SSRSA, rx_mask); | |
a5479e38 | 411 | } |
baffe169 | 412 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
1b340bd7 | 413 | |
1b340bd7 MB |
414 | return 0; |
415 | } | |
416 | ||
417 | /* | |
418 | * Tristate the SSP DAI lines | |
419 | */ | |
420 | static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai, | |
421 | int tristate) | |
422 | { | |
f0fba2ad | 423 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 424 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
425 | u32 sscr1; |
426 | ||
baffe169 | 427 | sscr1 = pxa_ssp_read_reg(ssp, SSCR1); |
1b340bd7 MB |
428 | if (tristate) |
429 | sscr1 &= ~SSCR1_TTE; | |
430 | else | |
431 | sscr1 |= SSCR1_TTE; | |
baffe169 | 432 | pxa_ssp_write_reg(ssp, SSCR1, sscr1); |
1b340bd7 MB |
433 | |
434 | return 0; | |
435 | } | |
436 | ||
437 | /* | |
438 | * Set up the SSP DAI format. | |
439 | * The SSP Port must be inactive before calling this function as the | |
440 | * physical interface format is changed. | |
441 | */ | |
442 | static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
443 | unsigned int fmt) | |
444 | { | |
f0fba2ad | 445 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 446 | struct ssp_device *ssp = priv->ssp; |
f5d1e5ed | 447 | u32 sscr0, sscr1, sspsp, scfr; |
1b340bd7 | 448 | |
cbf1146d DM |
449 | /* check if we need to change anything at all */ |
450 | if (priv->dai_fmt == fmt) | |
451 | return 0; | |
452 | ||
453 | /* we can only change the settings if the port is not in use */ | |
baffe169 | 454 | if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) { |
cbf1146d DM |
455 | dev_err(&ssp->pdev->dev, |
456 | "can't change hardware dai format: stream is in use"); | |
457 | return -EINVAL; | |
458 | } | |
459 | ||
1b340bd7 | 460 | /* reset port settings */ |
baffe169 | 461 | sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & |
f5d1e5ed | 462 | ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); |
1b340bd7 MB |
463 | sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7); |
464 | sspsp = 0; | |
465 | ||
466 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
467 | case SND_SOC_DAIFMT_CBM_CFM: | |
f5d1e5ed | 468 | sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR; |
1b340bd7 MB |
469 | break; |
470 | case SND_SOC_DAIFMT_CBM_CFS: | |
f5d1e5ed | 471 | sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR; |
1b340bd7 MB |
472 | break; |
473 | case SND_SOC_DAIFMT_CBS_CFS: | |
474 | break; | |
475 | default: | |
476 | return -EINVAL; | |
477 | } | |
478 | ||
fa44c077 DR |
479 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
480 | case SND_SOC_DAIFMT_NB_NF: | |
481 | sspsp |= SSPSP_SFRMP; | |
482 | break; | |
483 | case SND_SOC_DAIFMT_NB_IF: | |
484 | break; | |
485 | case SND_SOC_DAIFMT_IB_IF: | |
486 | sspsp |= SSPSP_SCMODE(2); | |
487 | break; | |
488 | case SND_SOC_DAIFMT_IB_NF: | |
489 | sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP; | |
490 | break; | |
491 | default: | |
492 | return -EINVAL; | |
493 | } | |
1b340bd7 MB |
494 | |
495 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
496 | case SND_SOC_DAIFMT_I2S: | |
72d74664 | 497 | sscr0 |= SSCR0_PSP; |
1b340bd7 | 498 | sscr1 |= SSCR1_RWOT | SSCR1_TRAIL; |
0ce36c5f | 499 | /* See hw_params() */ |
1b340bd7 MB |
500 | break; |
501 | ||
502 | case SND_SOC_DAIFMT_DSP_A: | |
503 | sspsp |= SSPSP_FSRT; | |
504 | case SND_SOC_DAIFMT_DSP_B: | |
505 | sscr0 |= SSCR0_MOD | SSCR0_PSP; | |
506 | sscr1 |= SSCR1_TRAIL | SSCR1_RWOT; | |
1b340bd7 MB |
507 | break; |
508 | ||
509 | default: | |
510 | return -EINVAL; | |
511 | } | |
512 | ||
baffe169 HZ |
513 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
514 | pxa_ssp_write_reg(ssp, SSCR1, sscr1); | |
515 | pxa_ssp_write_reg(ssp, SSPSP, sspsp); | |
1b340bd7 | 516 | |
f5d1e5ed HZ |
517 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
518 | case SND_SOC_DAIFMT_CBM_CFM: | |
519 | case SND_SOC_DAIFMT_CBM_CFS: | |
520 | scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR; | |
521 | pxa_ssp_write_reg(ssp, SSCR1, scfr); | |
522 | ||
523 | while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY) | |
524 | cpu_relax(); | |
525 | break; | |
526 | } | |
527 | ||
1b340bd7 MB |
528 | dump_registers(ssp); |
529 | ||
530 | /* Since we are configuring the timings for the format by hand | |
531 | * we have to defer some things until hw_params() where we | |
532 | * know parameters like the sample size. | |
533 | */ | |
534 | priv->dai_fmt = fmt; | |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
539 | /* | |
540 | * Set the SSP audio DMA parameters and sample size. | |
541 | * Can be called multiple times by oss emulation. | |
542 | */ | |
543 | static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d | 544 | struct snd_pcm_hw_params *params, |
f0fba2ad | 545 | struct snd_soc_dai *cpu_dai) |
1b340bd7 | 546 | { |
f0fba2ad | 547 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 548 | struct ssp_device *ssp = priv->ssp; |
2d7e71fa | 549 | int chn = params_channels(params); |
1b340bd7 MB |
550 | u32 sscr0; |
551 | u32 sspsp; | |
552 | int width = snd_pcm_format_physical_width(params_format(params)); | |
baffe169 | 553 | int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf; |
d65a1458 | 554 | struct snd_dmaengine_dai_dma_data *dma_data; |
5f712b2b | 555 | |
f0fba2ad | 556 | dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream); |
1b340bd7 | 557 | |
92429069 PZ |
558 | /* Network mode with one active slot (ttsa == 1) can be used |
559 | * to force 16-bit frame width on the wire (for S16_LE), even | |
560 | * with two channels. Use 16-bit DMA transfers for this case. | |
561 | */ | |
d93ca1ae | 562 | pxa_ssp_set_dma_params(ssp, |
563 | ((chn == 2) && (ttsa != 1)) || (width == 32), | |
564 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data); | |
5f712b2b | 565 | |
1b340bd7 | 566 | /* we can only change the settings if the port is not in use */ |
baffe169 | 567 | if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) |
1b340bd7 MB |
568 | return 0; |
569 | ||
570 | /* clear selected SSP bits */ | |
baffe169 | 571 | sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS); |
1b340bd7 MB |
572 | |
573 | /* bit size */ | |
1b340bd7 MB |
574 | switch (params_format(params)) { |
575 | case SNDRV_PCM_FORMAT_S16_LE: | |
972a55b6 | 576 | if (ssp->type == PXA3xx_SSP) |
1b340bd7 | 577 | sscr0 |= SSCR0_FPCKE; |
1b340bd7 | 578 | sscr0 |= SSCR0_DataSize(16); |
1b340bd7 MB |
579 | break; |
580 | case SNDRV_PCM_FORMAT_S24_LE: | |
581 | sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8)); | |
1b340bd7 MB |
582 | break; |
583 | case SNDRV_PCM_FORMAT_S32_LE: | |
584 | sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16)); | |
1b340bd7 MB |
585 | break; |
586 | } | |
baffe169 | 587 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
1b340bd7 MB |
588 | |
589 | switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
590 | case SND_SOC_DAIFMT_I2S: | |
baffe169 | 591 | sspsp = pxa_ssp_read_reg(ssp, SSPSP); |
72d74664 | 592 | |
baffe169 | 593 | if ((pxa_ssp_get_scr(ssp) == 4) && (width == 16)) { |
72d74664 DM |
594 | /* This is a special case where the bitclk is 64fs |
595 | * and we're not dealing with 2*32 bits of audio | |
596 | * samples. | |
597 | * | |
598 | * The SSP values used for that are all found out by | |
599 | * trying and failing a lot; some of the registers | |
600 | * needed for that mode are only available on PXA3xx. | |
601 | */ | |
972a55b6 | 602 | if (ssp->type != PXA3xx_SSP) |
72d74664 DM |
603 | return -EINVAL; |
604 | ||
605 | sspsp |= SSPSP_SFRMWDTH(width * 2); | |
606 | sspsp |= SSPSP_SFRMDLY(width * 4); | |
607 | sspsp |= SSPSP_EDMYSTOP(3); | |
608 | sspsp |= SSPSP_DMYSTOP(3); | |
609 | sspsp |= SSPSP_DMYSTRT(1); | |
0ce36c5f MB |
610 | } else { |
611 | /* The frame width is the width the LRCLK is | |
612 | * asserted for; the delay is expressed in | |
613 | * half cycle units. We need the extra cycle | |
614 | * because the data starts clocking out one BCLK | |
615 | * after LRCLK changes polarity. | |
616 | */ | |
617 | sspsp |= SSPSP_SFRMWDTH(width + 1); | |
618 | sspsp |= SSPSP_SFRMDLY((width + 1) * 2); | |
619 | sspsp |= SSPSP_DMYSTRT(1); | |
620 | } | |
72d74664 | 621 | |
baffe169 | 622 | pxa_ssp_write_reg(ssp, SSPSP, sspsp); |
1b340bd7 MB |
623 | break; |
624 | default: | |
625 | break; | |
626 | } | |
627 | ||
72d74664 | 628 | /* When we use a network mode, we always require TDM slots |
1b340bd7 MB |
629 | * - complain loudly and fail if they've not been set up yet. |
630 | */ | |
92429069 | 631 | if ((sscr0 & SSCR0_MOD) && !ttsa) { |
1b340bd7 MB |
632 | dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n"); |
633 | return -EINVAL; | |
634 | } | |
635 | ||
636 | dump_registers(ssp); | |
637 | ||
638 | return 0; | |
639 | } | |
640 | ||
273b72c8 DM |
641 | static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream, |
642 | struct ssp_device *ssp, int value) | |
643 | { | |
644 | uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0); | |
645 | uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1); | |
646 | uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP); | |
647 | uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR); | |
648 | ||
649 | if (value && (sscr0 & SSCR0_SSE)) | |
650 | pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE); | |
651 | ||
652 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
653 | if (value) | |
654 | sscr1 |= SSCR1_TSRE; | |
655 | else | |
656 | sscr1 &= ~SSCR1_TSRE; | |
657 | } else { | |
658 | if (value) | |
659 | sscr1 |= SSCR1_RSRE; | |
660 | else | |
661 | sscr1 &= ~SSCR1_RSRE; | |
662 | } | |
663 | ||
664 | pxa_ssp_write_reg(ssp, SSCR1, sscr1); | |
665 | ||
666 | if (value) { | |
667 | pxa_ssp_write_reg(ssp, SSSR, sssr); | |
668 | pxa_ssp_write_reg(ssp, SSPSP, sspsp); | |
669 | pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE); | |
670 | } | |
671 | } | |
672 | ||
dee89c4d | 673 | static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd, |
f0fba2ad | 674 | struct snd_soc_dai *cpu_dai) |
1b340bd7 | 675 | { |
1b340bd7 | 676 | int ret = 0; |
f0fba2ad | 677 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 678 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
679 | int val; |
680 | ||
681 | switch (cmd) { | |
682 | case SNDRV_PCM_TRIGGER_RESUME: | |
baffe169 | 683 | pxa_ssp_enable(ssp); |
1b340bd7 MB |
684 | break; |
685 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
273b72c8 | 686 | pxa_ssp_set_running_bit(substream, ssp, 1); |
baffe169 HZ |
687 | val = pxa_ssp_read_reg(ssp, SSSR); |
688 | pxa_ssp_write_reg(ssp, SSSR, val); | |
1b340bd7 MB |
689 | break; |
690 | case SNDRV_PCM_TRIGGER_START: | |
273b72c8 | 691 | pxa_ssp_set_running_bit(substream, ssp, 1); |
1b340bd7 MB |
692 | break; |
693 | case SNDRV_PCM_TRIGGER_STOP: | |
273b72c8 | 694 | pxa_ssp_set_running_bit(substream, ssp, 0); |
1b340bd7 MB |
695 | break; |
696 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
baffe169 | 697 | pxa_ssp_disable(ssp); |
1b340bd7 MB |
698 | break; |
699 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
273b72c8 | 700 | pxa_ssp_set_running_bit(substream, ssp, 0); |
1b340bd7 MB |
701 | break; |
702 | ||
703 | default: | |
704 | ret = -EINVAL; | |
705 | } | |
706 | ||
707 | dump_registers(ssp); | |
708 | ||
709 | return ret; | |
710 | } | |
711 | ||
f0fba2ad | 712 | static int pxa_ssp_probe(struct snd_soc_dai *dai) |
1b340bd7 | 713 | { |
2023c90c | 714 | struct device *dev = dai->dev; |
1b340bd7 MB |
715 | struct ssp_priv *priv; |
716 | int ret; | |
717 | ||
718 | priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL); | |
719 | if (!priv) | |
720 | return -ENOMEM; | |
721 | ||
2023c90c DM |
722 | if (dev->of_node) { |
723 | struct device_node *ssp_handle; | |
724 | ||
725 | ssp_handle = of_parse_phandle(dev->of_node, "port", 0); | |
726 | if (!ssp_handle) { | |
727 | dev_err(dev, "unable to get 'port' phandle\n"); | |
728 | return -ENODEV; | |
729 | } | |
730 | ||
731 | priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio"); | |
732 | if (priv->ssp == NULL) { | |
733 | ret = -ENODEV; | |
734 | goto err_priv; | |
735 | } | |
736 | } else { | |
737 | priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio"); | |
738 | if (priv->ssp == NULL) { | |
739 | ret = -ENODEV; | |
740 | goto err_priv; | |
741 | } | |
1b340bd7 MB |
742 | } |
743 | ||
a5735b7e | 744 | priv->dai_fmt = (unsigned int) -1; |
f0fba2ad | 745 | snd_soc_dai_set_drvdata(dai, priv); |
1b340bd7 MB |
746 | |
747 | return 0; | |
748 | ||
749 | err_priv: | |
750 | kfree(priv); | |
751 | return ret; | |
752 | } | |
753 | ||
f0fba2ad | 754 | static int pxa_ssp_remove(struct snd_soc_dai *dai) |
1b340bd7 | 755 | { |
f0fba2ad LG |
756 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai); |
757 | ||
baffe169 | 758 | pxa_ssp_free(priv->ssp); |
014a2755 | 759 | kfree(priv); |
f0fba2ad | 760 | return 0; |
1b340bd7 MB |
761 | } |
762 | ||
763 | #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ | |
764 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ | |
8d8bf58b QZ |
765 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ |
766 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \ | |
1b340bd7 MB |
767 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) |
768 | ||
769 | #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
770 | SNDRV_PCM_FMTBIT_S24_LE | \ | |
771 | SNDRV_PCM_FMTBIT_S32_LE) | |
772 | ||
85e7652d | 773 | static const struct snd_soc_dai_ops pxa_ssp_dai_ops = { |
6335d055 EM |
774 | .startup = pxa_ssp_startup, |
775 | .shutdown = pxa_ssp_shutdown, | |
776 | .trigger = pxa_ssp_trigger, | |
777 | .hw_params = pxa_ssp_hw_params, | |
778 | .set_sysclk = pxa_ssp_set_dai_sysclk, | |
779 | .set_clkdiv = pxa_ssp_set_dai_clkdiv, | |
780 | .set_pll = pxa_ssp_set_dai_pll, | |
781 | .set_fmt = pxa_ssp_set_dai_fmt, | |
782 | .set_tdm_slot = pxa_ssp_set_dai_tdm_slot, | |
783 | .set_tristate = pxa_ssp_set_dai_tristate, | |
784 | }; | |
785 | ||
f0fba2ad | 786 | static struct snd_soc_dai_driver pxa_ssp_dai = { |
1b340bd7 MB |
787 | .probe = pxa_ssp_probe, |
788 | .remove = pxa_ssp_remove, | |
789 | .suspend = pxa_ssp_suspend, | |
790 | .resume = pxa_ssp_resume, | |
791 | .playback = { | |
792 | .channels_min = 1, | |
f34762b6 | 793 | .channels_max = 8, |
1b340bd7 MB |
794 | .rates = PXA_SSP_RATES, |
795 | .formats = PXA_SSP_FORMATS, | |
796 | }, | |
797 | .capture = { | |
798 | .channels_min = 1, | |
f34762b6 | 799 | .channels_max = 8, |
1b340bd7 MB |
800 | .rates = PXA_SSP_RATES, |
801 | .formats = PXA_SSP_FORMATS, | |
802 | }, | |
6335d055 | 803 | .ops = &pxa_ssp_dai_ops, |
f0fba2ad LG |
804 | }; |
805 | ||
e580f1ce KM |
806 | static const struct snd_soc_component_driver pxa_ssp_component = { |
807 | .name = "pxa-ssp", | |
808 | }; | |
809 | ||
2023c90c DM |
810 | #ifdef CONFIG_OF |
811 | static const struct of_device_id pxa_ssp_of_ids[] = { | |
812 | { .compatible = "mrvl,pxa-ssp-dai" }, | |
813 | }; | |
814 | #endif | |
815 | ||
570f6fe1 | 816 | static int asoc_ssp_probe(struct platform_device *pdev) |
f0fba2ad | 817 | { |
e580f1ce KM |
818 | return snd_soc_register_component(&pdev->dev, &pxa_ssp_component, |
819 | &pxa_ssp_dai, 1); | |
f0fba2ad LG |
820 | } |
821 | ||
570f6fe1 | 822 | static int asoc_ssp_remove(struct platform_device *pdev) |
f0fba2ad | 823 | { |
e580f1ce | 824 | snd_soc_unregister_component(&pdev->dev); |
f0fba2ad LG |
825 | return 0; |
826 | } | |
827 | ||
828 | static struct platform_driver asoc_ssp_driver = { | |
829 | .driver = { | |
2023c90c DM |
830 | .name = "pxa-ssp-dai", |
831 | .owner = THIS_MODULE, | |
832 | .of_match_table = of_match_ptr(pxa_ssp_of_ids), | |
1b340bd7 | 833 | }, |
f0fba2ad LG |
834 | |
835 | .probe = asoc_ssp_probe, | |
570f6fe1 | 836 | .remove = asoc_ssp_remove, |
1b340bd7 | 837 | }; |
1b340bd7 | 838 | |
2f702a19 | 839 | module_platform_driver(asoc_ssp_driver); |
3f4b783c | 840 | |
1b340bd7 MB |
841 | /* Module information */ |
842 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
843 | MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface"); | |
844 | MODULE_LICENSE("GPL"); |