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1 | #define DEBUG |
2 | /* | |
3 | * pxa-ssp.c -- ALSA Soc Audio Layer | |
4 | * | |
5 | * Copyright 2005,2008 Wolfson Microelectronics PLC. | |
6 | * Author: Liam Girdwood | |
7 | * Mark Brown <broonie@opensource.wolfsonmicro.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | * TODO: | |
15 | * o Test network mode for > 16bit sample size | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/io.h> | |
23 | ||
0664678a PZ |
24 | #include <asm/irq.h> |
25 | ||
1b340bd7 MB |
26 | #include <sound/core.h> |
27 | #include <sound/pcm.h> | |
28 | #include <sound/initval.h> | |
29 | #include <sound/pcm_params.h> | |
30 | #include <sound/soc.h> | |
31 | #include <sound/pxa2xx-lib.h> | |
32 | ||
33 | #include <mach/hardware.h> | |
34 | #include <mach/pxa-regs.h> | |
35 | #include <mach/regs-ssp.h> | |
36 | #include <mach/audio.h> | |
37 | #include <mach/ssp.h> | |
38 | ||
39 | #include "pxa2xx-pcm.h" | |
40 | #include "pxa-ssp.h" | |
41 | ||
42 | /* | |
43 | * SSP audio private data | |
44 | */ | |
45 | struct ssp_priv { | |
46 | struct ssp_dev dev; | |
47 | unsigned int sysclk; | |
48 | int dai_fmt; | |
49 | #ifdef CONFIG_PM | |
50 | struct ssp_state state; | |
51 | #endif | |
52 | }; | |
53 | ||
54 | #define PXA2xx_SSP1_BASE 0x41000000 | |
55 | #define PXA27x_SSP2_BASE 0x41700000 | |
56 | #define PXA27x_SSP3_BASE 0x41900000 | |
57 | #define PXA3xx_SSP4_BASE 0x41a00000 | |
58 | ||
59 | static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_out = { | |
60 | .name = "SSP1 PCM Mono out", | |
61 | .dev_addr = PXA2xx_SSP1_BASE + SSDR, | |
62 | .drcmr = &DRCMR(14), | |
63 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
64 | DCMD_BURST16 | DCMD_WIDTH2, | |
65 | }; | |
66 | ||
67 | static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_in = { | |
68 | .name = "SSP1 PCM Mono in", | |
69 | .dev_addr = PXA2xx_SSP1_BASE + SSDR, | |
70 | .drcmr = &DRCMR(13), | |
71 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
72 | DCMD_BURST16 | DCMD_WIDTH2, | |
73 | }; | |
74 | ||
75 | static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_out = { | |
76 | .name = "SSP1 PCM Stereo out", | |
77 | .dev_addr = PXA2xx_SSP1_BASE + SSDR, | |
78 | .drcmr = &DRCMR(14), | |
79 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
80 | DCMD_BURST16 | DCMD_WIDTH4, | |
81 | }; | |
82 | ||
83 | static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_in = { | |
84 | .name = "SSP1 PCM Stereo in", | |
85 | .dev_addr = PXA2xx_SSP1_BASE + SSDR, | |
86 | .drcmr = &DRCMR(13), | |
87 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
88 | DCMD_BURST16 | DCMD_WIDTH4, | |
89 | }; | |
90 | ||
91 | static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_out = { | |
92 | .name = "SSP2 PCM Mono out", | |
93 | .dev_addr = PXA27x_SSP2_BASE + SSDR, | |
94 | .drcmr = &DRCMR(16), | |
95 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
96 | DCMD_BURST16 | DCMD_WIDTH2, | |
97 | }; | |
98 | ||
99 | static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_in = { | |
100 | .name = "SSP2 PCM Mono in", | |
101 | .dev_addr = PXA27x_SSP2_BASE + SSDR, | |
102 | .drcmr = &DRCMR(15), | |
103 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
104 | DCMD_BURST16 | DCMD_WIDTH2, | |
105 | }; | |
106 | ||
107 | static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_out = { | |
108 | .name = "SSP2 PCM Stereo out", | |
109 | .dev_addr = PXA27x_SSP2_BASE + SSDR, | |
110 | .drcmr = &DRCMR(16), | |
111 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
112 | DCMD_BURST16 | DCMD_WIDTH4, | |
113 | }; | |
114 | ||
115 | static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_in = { | |
116 | .name = "SSP2 PCM Stereo in", | |
117 | .dev_addr = PXA27x_SSP2_BASE + SSDR, | |
118 | .drcmr = &DRCMR(15), | |
119 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
120 | DCMD_BURST16 | DCMD_WIDTH4, | |
121 | }; | |
122 | ||
123 | static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_out = { | |
124 | .name = "SSP3 PCM Mono out", | |
125 | .dev_addr = PXA27x_SSP3_BASE + SSDR, | |
126 | .drcmr = &DRCMR(67), | |
127 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
128 | DCMD_BURST16 | DCMD_WIDTH2, | |
129 | }; | |
130 | ||
131 | static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_in = { | |
132 | .name = "SSP3 PCM Mono in", | |
133 | .dev_addr = PXA27x_SSP3_BASE + SSDR, | |
134 | .drcmr = &DRCMR(66), | |
135 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
136 | DCMD_BURST16 | DCMD_WIDTH2, | |
137 | }; | |
138 | ||
139 | static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_out = { | |
140 | .name = "SSP3 PCM Stereo out", | |
141 | .dev_addr = PXA27x_SSP3_BASE + SSDR, | |
142 | .drcmr = &DRCMR(67), | |
143 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
144 | DCMD_BURST16 | DCMD_WIDTH4, | |
145 | }; | |
146 | ||
147 | static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_in = { | |
148 | .name = "SSP3 PCM Stereo in", | |
149 | .dev_addr = PXA27x_SSP3_BASE + SSDR, | |
150 | .drcmr = &DRCMR(66), | |
151 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
152 | DCMD_BURST16 | DCMD_WIDTH4, | |
153 | }; | |
154 | ||
155 | static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_out = { | |
156 | .name = "SSP4 PCM Mono out", | |
157 | .dev_addr = PXA3xx_SSP4_BASE + SSDR, | |
158 | .drcmr = &DRCMR(67), | |
159 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
160 | DCMD_BURST16 | DCMD_WIDTH2, | |
161 | }; | |
162 | ||
163 | static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_in = { | |
164 | .name = "SSP4 PCM Mono in", | |
165 | .dev_addr = PXA3xx_SSP4_BASE + SSDR, | |
166 | .drcmr = &DRCMR(66), | |
167 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
168 | DCMD_BURST16 | DCMD_WIDTH2, | |
169 | }; | |
170 | ||
171 | static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_out = { | |
172 | .name = "SSP4 PCM Stereo out", | |
173 | .dev_addr = PXA3xx_SSP4_BASE + SSDR, | |
174 | .drcmr = &DRCMR(67), | |
175 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
176 | DCMD_BURST16 | DCMD_WIDTH4, | |
177 | }; | |
178 | ||
179 | static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_in = { | |
180 | .name = "SSP4 PCM Stereo in", | |
181 | .dev_addr = PXA3xx_SSP4_BASE + SSDR, | |
182 | .drcmr = &DRCMR(66), | |
183 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
184 | DCMD_BURST16 | DCMD_WIDTH4, | |
185 | }; | |
186 | ||
187 | static void dump_registers(struct ssp_device *ssp) | |
188 | { | |
189 | dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n", | |
190 | ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1), | |
191 | ssp_read_reg(ssp, SSTO)); | |
192 | ||
193 | dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n", | |
194 | ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR), | |
195 | ssp_read_reg(ssp, SSACD)); | |
196 | } | |
197 | ||
198 | static struct pxa2xx_pcm_dma_params *ssp_dma_params[4][4] = { | |
199 | { | |
200 | &pxa_ssp1_pcm_mono_out, &pxa_ssp1_pcm_mono_in, | |
201 | &pxa_ssp1_pcm_stereo_out, &pxa_ssp1_pcm_stereo_in, | |
202 | }, | |
203 | { | |
204 | &pxa_ssp2_pcm_mono_out, &pxa_ssp2_pcm_mono_in, | |
205 | &pxa_ssp2_pcm_stereo_out, &pxa_ssp2_pcm_stereo_in, | |
206 | }, | |
207 | { | |
208 | &pxa_ssp3_pcm_mono_out, &pxa_ssp3_pcm_mono_in, | |
209 | &pxa_ssp3_pcm_stereo_out, &pxa_ssp3_pcm_stereo_in, | |
210 | }, | |
211 | { | |
212 | &pxa_ssp4_pcm_mono_out, &pxa_ssp4_pcm_mono_in, | |
213 | &pxa_ssp4_pcm_stereo_out, &pxa_ssp4_pcm_stereo_in, | |
214 | }, | |
215 | }; | |
216 | ||
dee89c4d MB |
217 | static int pxa_ssp_startup(struct snd_pcm_substream *substream, |
218 | struct snd_soc_dai *dai) | |
1b340bd7 MB |
219 | { |
220 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
221 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; | |
222 | struct ssp_priv *priv = cpu_dai->private_data; | |
223 | int ret = 0; | |
224 | ||
225 | if (!cpu_dai->active) { | |
0664678a PZ |
226 | priv->dev.port = cpu_dai->id + 1; |
227 | priv->dev.irq = NO_IRQ; | |
228 | clk_enable(priv->dev.ssp->clk); | |
1b340bd7 MB |
229 | ssp_disable(&priv->dev); |
230 | } | |
231 | return ret; | |
232 | } | |
233 | ||
dee89c4d MB |
234 | static void pxa_ssp_shutdown(struct snd_pcm_substream *substream, |
235 | struct snd_soc_dai *dai) | |
1b340bd7 MB |
236 | { |
237 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
238 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; | |
239 | struct ssp_priv *priv = cpu_dai->private_data; | |
240 | ||
241 | if (!cpu_dai->active) { | |
242 | ssp_disable(&priv->dev); | |
0664678a | 243 | clk_disable(priv->dev.ssp->clk); |
1b340bd7 MB |
244 | } |
245 | } | |
246 | ||
247 | #ifdef CONFIG_PM | |
248 | ||
dc7d7b83 | 249 | static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai) |
1b340bd7 MB |
250 | { |
251 | struct ssp_priv *priv = cpu_dai->private_data; | |
252 | ||
253 | if (!cpu_dai->active) | |
254 | return 0; | |
255 | ||
256 | ssp_save_state(&priv->dev, &priv->state); | |
257 | clk_disable(priv->dev.ssp->clk); | |
258 | return 0; | |
259 | } | |
260 | ||
dc7d7b83 | 261 | static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai) |
1b340bd7 MB |
262 | { |
263 | struct ssp_priv *priv = cpu_dai->private_data; | |
264 | ||
265 | if (!cpu_dai->active) | |
266 | return 0; | |
267 | ||
268 | clk_enable(priv->dev.ssp->clk); | |
269 | ssp_restore_state(&priv->dev, &priv->state); | |
270 | ssp_enable(&priv->dev); | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
275 | #else | |
276 | #define pxa_ssp_suspend NULL | |
277 | #define pxa_ssp_resume NULL | |
278 | #endif | |
279 | ||
280 | /** | |
281 | * ssp_set_clkdiv - set SSP clock divider | |
282 | * @div: serial clock rate divider | |
283 | */ | |
284 | static void ssp_set_scr(struct ssp_dev *dev, u32 div) | |
285 | { | |
286 | struct ssp_device *ssp = dev->ssp; | |
287 | u32 sscr0 = ssp_read_reg(dev->ssp, SSCR0) & ~SSCR0_SCR; | |
288 | ||
289 | ssp_write_reg(ssp, SSCR0, (sscr0 | SSCR0_SerClkDiv(div))); | |
290 | } | |
291 | ||
292 | /* | |
293 | * Set the SSP ports SYSCLK. | |
294 | */ | |
295 | static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
296 | int clk_id, unsigned int freq, int dir) | |
297 | { | |
298 | struct ssp_priv *priv = cpu_dai->private_data; | |
299 | struct ssp_device *ssp = priv->dev.ssp; | |
300 | int val; | |
301 | ||
302 | u32 sscr0 = ssp_read_reg(ssp, SSCR0) & | |
20a41eac | 303 | ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); |
1b340bd7 MB |
304 | |
305 | dev_dbg(&ssp->pdev->dev, | |
306 | "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %d\n", | |
307 | cpu_dai->id, clk_id, freq); | |
308 | ||
309 | switch (clk_id) { | |
310 | case PXA_SSP_CLK_NET_PLL: | |
311 | sscr0 |= SSCR0_MOD; | |
312 | break; | |
313 | case PXA_SSP_CLK_PLL: | |
314 | /* Internal PLL is fixed */ | |
315 | if (cpu_is_pxa25x()) | |
316 | priv->sysclk = 1843200; | |
317 | else | |
318 | priv->sysclk = 13000000; | |
319 | break; | |
320 | case PXA_SSP_CLK_EXT: | |
321 | priv->sysclk = freq; | |
322 | sscr0 |= SSCR0_ECS; | |
323 | break; | |
324 | case PXA_SSP_CLK_NET: | |
325 | priv->sysclk = freq; | |
326 | sscr0 |= SSCR0_NCS | SSCR0_MOD; | |
327 | break; | |
328 | case PXA_SSP_CLK_AUDIO: | |
329 | priv->sysclk = 0; | |
330 | ssp_set_scr(&priv->dev, 1); | |
20a41eac | 331 | sscr0 |= SSCR0_ACS; |
1b340bd7 MB |
332 | break; |
333 | default: | |
334 | return -ENODEV; | |
335 | } | |
336 | ||
337 | /* The SSP clock must be disabled when changing SSP clock mode | |
338 | * on PXA2xx. On PXA3xx it must be enabled when doing so. */ | |
339 | if (!cpu_is_pxa3xx()) | |
340 | clk_disable(priv->dev.ssp->clk); | |
341 | val = ssp_read_reg(ssp, SSCR0) | sscr0; | |
342 | ssp_write_reg(ssp, SSCR0, val); | |
343 | if (!cpu_is_pxa3xx()) | |
344 | clk_enable(priv->dev.ssp->clk); | |
345 | ||
346 | return 0; | |
347 | } | |
348 | ||
349 | /* | |
350 | * Set the SSP clock dividers. | |
351 | */ | |
352 | static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, | |
353 | int div_id, int div) | |
354 | { | |
355 | struct ssp_priv *priv = cpu_dai->private_data; | |
356 | struct ssp_device *ssp = priv->dev.ssp; | |
357 | int val; | |
358 | ||
359 | switch (div_id) { | |
360 | case PXA_SSP_AUDIO_DIV_ACDS: | |
361 | val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div); | |
362 | ssp_write_reg(ssp, SSACD, val); | |
363 | break; | |
364 | case PXA_SSP_AUDIO_DIV_SCDB: | |
365 | val = ssp_read_reg(ssp, SSACD); | |
366 | val &= ~SSACD_SCDB; | |
367 | #if defined(CONFIG_PXA3xx) | |
368 | if (cpu_is_pxa3xx()) | |
369 | val &= ~SSACD_SCDX8; | |
370 | #endif | |
371 | switch (div) { | |
372 | case PXA_SSP_CLK_SCDB_1: | |
373 | val |= SSACD_SCDB; | |
374 | break; | |
375 | case PXA_SSP_CLK_SCDB_4: | |
376 | break; | |
377 | #if defined(CONFIG_PXA3xx) | |
378 | case PXA_SSP_CLK_SCDB_8: | |
379 | if (cpu_is_pxa3xx()) | |
380 | val |= SSACD_SCDX8; | |
381 | else | |
382 | return -EINVAL; | |
383 | break; | |
384 | #endif | |
385 | default: | |
386 | return -EINVAL; | |
387 | } | |
388 | ssp_write_reg(ssp, SSACD, val); | |
389 | break; | |
390 | case PXA_SSP_DIV_SCR: | |
391 | ssp_set_scr(&priv->dev, div); | |
392 | break; | |
393 | default: | |
394 | return -ENODEV; | |
395 | } | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
400 | /* | |
401 | * Configure the PLL frequency pxa27x and (afaik - pxa320 only) | |
402 | */ | |
403 | static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, | |
404 | int pll_id, unsigned int freq_in, unsigned int freq_out) | |
405 | { | |
406 | struct ssp_priv *priv = cpu_dai->private_data; | |
407 | struct ssp_device *ssp = priv->dev.ssp; | |
408 | u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70; | |
409 | ||
410 | #if defined(CONFIG_PXA3xx) | |
411 | if (cpu_is_pxa3xx()) | |
412 | ssp_write_reg(ssp, SSACDD, 0); | |
413 | #endif | |
414 | ||
415 | switch (freq_out) { | |
416 | case 5622000: | |
417 | break; | |
418 | case 11345000: | |
419 | ssacd |= (0x1 << 4); | |
420 | break; | |
421 | case 12235000: | |
422 | ssacd |= (0x2 << 4); | |
423 | break; | |
424 | case 14857000: | |
425 | ssacd |= (0x3 << 4); | |
426 | break; | |
427 | case 32842000: | |
428 | ssacd |= (0x4 << 4); | |
429 | break; | |
430 | case 48000000: | |
431 | ssacd |= (0x5 << 4); | |
432 | break; | |
433 | case 0: | |
434 | /* Disable */ | |
435 | break; | |
436 | ||
437 | default: | |
438 | #ifdef CONFIG_PXA3xx | |
439 | /* PXA3xx has a clock ditherer which can be used to generate | |
440 | * a wider range of frequencies - calculate a value for it. | |
441 | */ | |
442 | if (cpu_is_pxa3xx()) { | |
443 | u32 val; | |
444 | u64 tmp = 19968; | |
445 | tmp *= 1000000; | |
446 | do_div(tmp, freq_out); | |
447 | val = tmp; | |
448 | ||
449 | val = (val << 16) | 64;; | |
450 | ssp_write_reg(ssp, SSACDD, val); | |
451 | ||
452 | ssacd |= (0x6 << 4); | |
453 | ||
454 | dev_dbg(&ssp->pdev->dev, | |
455 | "Using SSACDD %x to supply %dHz\n", | |
456 | val, freq_out); | |
457 | break; | |
458 | } | |
459 | #endif | |
460 | ||
461 | return -EINVAL; | |
462 | } | |
463 | ||
464 | ssp_write_reg(ssp, SSACD, ssacd); | |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
469 | /* | |
470 | * Set the active slots in TDM/Network mode | |
471 | */ | |
472 | static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, | |
473 | unsigned int mask, int slots) | |
474 | { | |
475 | struct ssp_priv *priv = cpu_dai->private_data; | |
476 | struct ssp_device *ssp = priv->dev.ssp; | |
477 | u32 sscr0; | |
478 | ||
479 | sscr0 = ssp_read_reg(ssp, SSCR0) & ~SSCR0_SlotsPerFrm(7); | |
480 | ||
481 | /* set number of active slots */ | |
482 | sscr0 |= SSCR0_SlotsPerFrm(slots); | |
483 | ssp_write_reg(ssp, SSCR0, sscr0); | |
484 | ||
485 | /* set active slot mask */ | |
486 | ssp_write_reg(ssp, SSTSA, mask); | |
487 | ssp_write_reg(ssp, SSRSA, mask); | |
488 | return 0; | |
489 | } | |
490 | ||
491 | /* | |
492 | * Tristate the SSP DAI lines | |
493 | */ | |
494 | static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai, | |
495 | int tristate) | |
496 | { | |
497 | struct ssp_priv *priv = cpu_dai->private_data; | |
498 | struct ssp_device *ssp = priv->dev.ssp; | |
499 | u32 sscr1; | |
500 | ||
501 | sscr1 = ssp_read_reg(ssp, SSCR1); | |
502 | if (tristate) | |
503 | sscr1 &= ~SSCR1_TTE; | |
504 | else | |
505 | sscr1 |= SSCR1_TTE; | |
506 | ssp_write_reg(ssp, SSCR1, sscr1); | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
511 | /* | |
512 | * Set up the SSP DAI format. | |
513 | * The SSP Port must be inactive before calling this function as the | |
514 | * physical interface format is changed. | |
515 | */ | |
516 | static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
517 | unsigned int fmt) | |
518 | { | |
519 | struct ssp_priv *priv = cpu_dai->private_data; | |
520 | struct ssp_device *ssp = priv->dev.ssp; | |
521 | u32 sscr0; | |
522 | u32 sscr1; | |
523 | u32 sspsp; | |
524 | ||
cbf1146d DM |
525 | /* check if we need to change anything at all */ |
526 | if (priv->dai_fmt == fmt) | |
527 | return 0; | |
528 | ||
529 | /* we can only change the settings if the port is not in use */ | |
530 | if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) { | |
531 | dev_err(&ssp->pdev->dev, | |
532 | "can't change hardware dai format: stream is in use"); | |
533 | return -EINVAL; | |
534 | } | |
535 | ||
1b340bd7 MB |
536 | /* reset port settings */ |
537 | sscr0 = ssp_read_reg(ssp, SSCR0) & | |
20a41eac | 538 | (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); |
1b340bd7 MB |
539 | sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7); |
540 | sspsp = 0; | |
541 | ||
542 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
543 | case SND_SOC_DAIFMT_CBM_CFM: | |
544 | sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR; | |
545 | break; | |
546 | case SND_SOC_DAIFMT_CBM_CFS: | |
547 | sscr1 |= SSCR1_SCLKDIR; | |
548 | break; | |
549 | case SND_SOC_DAIFMT_CBS_CFS: | |
550 | break; | |
551 | default: | |
552 | return -EINVAL; | |
553 | } | |
554 | ||
555 | ssp_write_reg(ssp, SSCR0, sscr0); | |
556 | ssp_write_reg(ssp, SSCR1, sscr1); | |
557 | ssp_write_reg(ssp, SSPSP, sspsp); | |
558 | ||
559 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
560 | case SND_SOC_DAIFMT_I2S: | |
561 | sscr0 |= SSCR0_MOD | SSCR0_PSP; | |
562 | sscr1 |= SSCR1_RWOT | SSCR1_TRAIL; | |
563 | ||
564 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
565 | case SND_SOC_DAIFMT_NB_NF: | |
566 | sspsp |= SSPSP_FSRT; | |
567 | break; | |
568 | case SND_SOC_DAIFMT_NB_IF: | |
569 | sspsp |= SSPSP_SFRMP | SSPSP_FSRT; | |
570 | break; | |
571 | case SND_SOC_DAIFMT_IB_IF: | |
572 | sspsp |= SSPSP_SFRMP; | |
573 | break; | |
574 | default: | |
575 | return -EINVAL; | |
576 | } | |
577 | break; | |
578 | ||
579 | case SND_SOC_DAIFMT_DSP_A: | |
580 | sspsp |= SSPSP_FSRT; | |
581 | case SND_SOC_DAIFMT_DSP_B: | |
582 | sscr0 |= SSCR0_MOD | SSCR0_PSP; | |
583 | sscr1 |= SSCR1_TRAIL | SSCR1_RWOT; | |
584 | ||
585 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
586 | case SND_SOC_DAIFMT_NB_NF: | |
587 | sspsp |= SSPSP_SFRMP; | |
588 | break; | |
589 | case SND_SOC_DAIFMT_IB_IF: | |
590 | break; | |
591 | default: | |
592 | return -EINVAL; | |
593 | } | |
594 | break; | |
595 | ||
596 | default: | |
597 | return -EINVAL; | |
598 | } | |
599 | ||
600 | ssp_write_reg(ssp, SSCR0, sscr0); | |
601 | ssp_write_reg(ssp, SSCR1, sscr1); | |
602 | ssp_write_reg(ssp, SSPSP, sspsp); | |
603 | ||
604 | dump_registers(ssp); | |
605 | ||
606 | /* Since we are configuring the timings for the format by hand | |
607 | * we have to defer some things until hw_params() where we | |
608 | * know parameters like the sample size. | |
609 | */ | |
610 | priv->dai_fmt = fmt; | |
611 | ||
612 | return 0; | |
613 | } | |
614 | ||
615 | /* | |
616 | * Set the SSP audio DMA parameters and sample size. | |
617 | * Can be called multiple times by oss emulation. | |
618 | */ | |
619 | static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
620 | struct snd_pcm_hw_params *params, |
621 | struct snd_soc_dai *dai) | |
1b340bd7 MB |
622 | { |
623 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
624 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; | |
625 | struct ssp_priv *priv = cpu_dai->private_data; | |
626 | struct ssp_device *ssp = priv->dev.ssp; | |
627 | int dma = 0, chn = params_channels(params); | |
628 | u32 sscr0; | |
629 | u32 sspsp; | |
630 | int width = snd_pcm_format_physical_width(params_format(params)); | |
631 | ||
632 | /* select correct DMA params */ | |
633 | if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) | |
634 | dma = 1; /* capture DMA offset is 1,3 */ | |
635 | if (chn == 2) | |
636 | dma += 2; /* stereo DMA offset is 2, mono is 0 */ | |
637 | cpu_dai->dma_data = ssp_dma_params[cpu_dai->id][dma]; | |
638 | ||
639 | dev_dbg(&ssp->pdev->dev, "pxa_ssp_hw_params: dma %d\n", dma); | |
640 | ||
641 | /* we can only change the settings if the port is not in use */ | |
642 | if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) | |
643 | return 0; | |
644 | ||
645 | /* clear selected SSP bits */ | |
646 | sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS); | |
647 | ssp_write_reg(ssp, SSCR0, sscr0); | |
648 | ||
649 | /* bit size */ | |
650 | sscr0 = ssp_read_reg(ssp, SSCR0); | |
651 | switch (params_format(params)) { | |
652 | case SNDRV_PCM_FORMAT_S16_LE: | |
653 | #ifdef CONFIG_PXA3xx | |
654 | if (cpu_is_pxa3xx()) | |
655 | sscr0 |= SSCR0_FPCKE; | |
656 | #endif | |
657 | sscr0 |= SSCR0_DataSize(16); | |
aa4ef01d | 658 | /* use network mode (2 slots) for 16 bit stereo */ |
1b340bd7 MB |
659 | break; |
660 | case SNDRV_PCM_FORMAT_S24_LE: | |
661 | sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8)); | |
662 | /* we must be in network mode (2 slots) for 24 bit stereo */ | |
663 | break; | |
664 | case SNDRV_PCM_FORMAT_S32_LE: | |
665 | sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16)); | |
666 | /* we must be in network mode (2 slots) for 32 bit stereo */ | |
667 | break; | |
668 | } | |
669 | ssp_write_reg(ssp, SSCR0, sscr0); | |
670 | ||
671 | switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
672 | case SND_SOC_DAIFMT_I2S: | |
673 | /* Cleared when the DAI format is set */ | |
674 | sspsp = ssp_read_reg(ssp, SSPSP) | SSPSP_SFRMWDTH(width); | |
675 | ssp_write_reg(ssp, SSPSP, sspsp); | |
676 | break; | |
677 | default: | |
678 | break; | |
679 | } | |
680 | ||
681 | /* We always use a network mode so we always require TDM slots | |
682 | * - complain loudly and fail if they've not been set up yet. | |
683 | */ | |
684 | if (!(ssp_read_reg(ssp, SSTSA) & 0xf)) { | |
685 | dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n"); | |
686 | return -EINVAL; | |
687 | } | |
688 | ||
689 | dump_registers(ssp); | |
690 | ||
691 | return 0; | |
692 | } | |
693 | ||
dee89c4d MB |
694 | static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd, |
695 | struct snd_soc_dai *dai) | |
1b340bd7 MB |
696 | { |
697 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
698 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; | |
699 | int ret = 0; | |
700 | struct ssp_priv *priv = cpu_dai->private_data; | |
701 | struct ssp_device *ssp = priv->dev.ssp; | |
702 | int val; | |
703 | ||
704 | switch (cmd) { | |
705 | case SNDRV_PCM_TRIGGER_RESUME: | |
706 | ssp_enable(&priv->dev); | |
707 | break; | |
708 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
709 | val = ssp_read_reg(ssp, SSCR1); | |
710 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
711 | val |= SSCR1_TSRE; | |
712 | else | |
713 | val |= SSCR1_RSRE; | |
714 | ssp_write_reg(ssp, SSCR1, val); | |
715 | val = ssp_read_reg(ssp, SSSR); | |
716 | ssp_write_reg(ssp, SSSR, val); | |
717 | break; | |
718 | case SNDRV_PCM_TRIGGER_START: | |
719 | val = ssp_read_reg(ssp, SSCR1); | |
720 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
721 | val |= SSCR1_TSRE; | |
722 | else | |
723 | val |= SSCR1_RSRE; | |
724 | ssp_write_reg(ssp, SSCR1, val); | |
725 | ssp_enable(&priv->dev); | |
726 | break; | |
727 | case SNDRV_PCM_TRIGGER_STOP: | |
728 | val = ssp_read_reg(ssp, SSCR1); | |
729 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
730 | val &= ~SSCR1_TSRE; | |
731 | else | |
732 | val &= ~SSCR1_RSRE; | |
733 | ssp_write_reg(ssp, SSCR1, val); | |
734 | break; | |
735 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
736 | ssp_disable(&priv->dev); | |
737 | break; | |
738 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
739 | val = ssp_read_reg(ssp, SSCR1); | |
740 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
741 | val &= ~SSCR1_TSRE; | |
742 | else | |
743 | val &= ~SSCR1_RSRE; | |
744 | ssp_write_reg(ssp, SSCR1, val); | |
745 | break; | |
746 | ||
747 | default: | |
748 | ret = -EINVAL; | |
749 | } | |
750 | ||
751 | dump_registers(ssp); | |
752 | ||
753 | return ret; | |
754 | } | |
755 | ||
756 | static int pxa_ssp_probe(struct platform_device *pdev, | |
757 | struct snd_soc_dai *dai) | |
758 | { | |
759 | struct ssp_priv *priv; | |
760 | int ret; | |
761 | ||
762 | priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL); | |
763 | if (!priv) | |
764 | return -ENOMEM; | |
765 | ||
0664678a | 766 | priv->dev.ssp = ssp_request(dai->id + 1, "SoC audio"); |
1b340bd7 MB |
767 | if (priv->dev.ssp == NULL) { |
768 | ret = -ENODEV; | |
769 | goto err_priv; | |
770 | } | |
771 | ||
772 | dai->private_data = priv; | |
773 | ||
774 | return 0; | |
775 | ||
776 | err_priv: | |
777 | kfree(priv); | |
778 | return ret; | |
779 | } | |
780 | ||
781 | static void pxa_ssp_remove(struct platform_device *pdev, | |
782 | struct snd_soc_dai *dai) | |
783 | { | |
784 | struct ssp_priv *priv = dai->private_data; | |
785 | ssp_free(priv->dev.ssp); | |
786 | } | |
787 | ||
788 | #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ | |
789 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ | |
790 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ | |
791 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) | |
792 | ||
793 | #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
794 | SNDRV_PCM_FMTBIT_S24_LE | \ | |
795 | SNDRV_PCM_FMTBIT_S32_LE) | |
796 | ||
6335d055 EM |
797 | static struct snd_soc_dai_ops pxa_ssp_dai_ops = { |
798 | .startup = pxa_ssp_startup, | |
799 | .shutdown = pxa_ssp_shutdown, | |
800 | .trigger = pxa_ssp_trigger, | |
801 | .hw_params = pxa_ssp_hw_params, | |
802 | .set_sysclk = pxa_ssp_set_dai_sysclk, | |
803 | .set_clkdiv = pxa_ssp_set_dai_clkdiv, | |
804 | .set_pll = pxa_ssp_set_dai_pll, | |
805 | .set_fmt = pxa_ssp_set_dai_fmt, | |
806 | .set_tdm_slot = pxa_ssp_set_dai_tdm_slot, | |
807 | .set_tristate = pxa_ssp_set_dai_tristate, | |
808 | }; | |
809 | ||
1b340bd7 MB |
810 | struct snd_soc_dai pxa_ssp_dai[] = { |
811 | { | |
812 | .name = "pxa2xx-ssp1", | |
813 | .id = 0, | |
1b340bd7 MB |
814 | .probe = pxa_ssp_probe, |
815 | .remove = pxa_ssp_remove, | |
816 | .suspend = pxa_ssp_suspend, | |
817 | .resume = pxa_ssp_resume, | |
818 | .playback = { | |
819 | .channels_min = 1, | |
820 | .channels_max = 2, | |
821 | .rates = PXA_SSP_RATES, | |
822 | .formats = PXA_SSP_FORMATS, | |
823 | }, | |
824 | .capture = { | |
825 | .channels_min = 1, | |
826 | .channels_max = 2, | |
827 | .rates = PXA_SSP_RATES, | |
828 | .formats = PXA_SSP_FORMATS, | |
829 | }, | |
6335d055 | 830 | .ops = &pxa_ssp_dai_ops, |
1b340bd7 MB |
831 | }, |
832 | { .name = "pxa2xx-ssp2", | |
833 | .id = 1, | |
1b340bd7 MB |
834 | .probe = pxa_ssp_probe, |
835 | .remove = pxa_ssp_remove, | |
836 | .suspend = pxa_ssp_suspend, | |
837 | .resume = pxa_ssp_resume, | |
838 | .playback = { | |
839 | .channels_min = 1, | |
840 | .channels_max = 2, | |
841 | .rates = PXA_SSP_RATES, | |
842 | .formats = PXA_SSP_FORMATS, | |
843 | }, | |
844 | .capture = { | |
845 | .channels_min = 1, | |
846 | .channels_max = 2, | |
847 | .rates = PXA_SSP_RATES, | |
848 | .formats = PXA_SSP_FORMATS, | |
849 | }, | |
6335d055 | 850 | .ops = &pxa_ssp_dai_ops, |
1b340bd7 MB |
851 | }, |
852 | { | |
853 | .name = "pxa2xx-ssp3", | |
854 | .id = 2, | |
1b340bd7 MB |
855 | .probe = pxa_ssp_probe, |
856 | .remove = pxa_ssp_remove, | |
857 | .suspend = pxa_ssp_suspend, | |
858 | .resume = pxa_ssp_resume, | |
859 | .playback = { | |
860 | .channels_min = 1, | |
861 | .channels_max = 2, | |
862 | .rates = PXA_SSP_RATES, | |
863 | .formats = PXA_SSP_FORMATS, | |
864 | }, | |
865 | .capture = { | |
866 | .channels_min = 1, | |
867 | .channels_max = 2, | |
868 | .rates = PXA_SSP_RATES, | |
869 | .formats = PXA_SSP_FORMATS, | |
870 | }, | |
6335d055 | 871 | .ops = &pxa_ssp_dai_ops, |
1b340bd7 MB |
872 | }, |
873 | { | |
874 | .name = "pxa2xx-ssp4", | |
875 | .id = 3, | |
1b340bd7 MB |
876 | .probe = pxa_ssp_probe, |
877 | .remove = pxa_ssp_remove, | |
878 | .suspend = pxa_ssp_suspend, | |
879 | .resume = pxa_ssp_resume, | |
880 | .playback = { | |
881 | .channels_min = 1, | |
882 | .channels_max = 2, | |
883 | .rates = PXA_SSP_RATES, | |
884 | .formats = PXA_SSP_FORMATS, | |
885 | }, | |
886 | .capture = { | |
887 | .channels_min = 1, | |
888 | .channels_max = 2, | |
889 | .rates = PXA_SSP_RATES, | |
890 | .formats = PXA_SSP_FORMATS, | |
891 | }, | |
6335d055 | 892 | .ops = &pxa_ssp_dai_ops, |
1b340bd7 MB |
893 | }, |
894 | }; | |
895 | EXPORT_SYMBOL_GPL(pxa_ssp_dai); | |
896 | ||
c9b3a40f | 897 | static int __init pxa_ssp_init(void) |
3f4b783c MB |
898 | { |
899 | return snd_soc_register_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai)); | |
900 | } | |
901 | module_init(pxa_ssp_init); | |
902 | ||
903 | static void __exit pxa_ssp_exit(void) | |
904 | { | |
905 | snd_soc_unregister_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai)); | |
906 | } | |
907 | module_exit(pxa_ssp_exit); | |
908 | ||
1b340bd7 MB |
909 | /* Module information */ |
910 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
911 | MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface"); | |
912 | MODULE_LICENSE("GPL"); |