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ASoC: move dma_data from snd_soc_dai to snd_soc_pcm_stream
[deliverable/linux.git] / sound / soc / pxa / pxa-ssp.c
CommitLineData
1b340bd7
MB		 1/*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22
0664678a
PZ		 23#include <asm/irq.h>
24
1b340bd7
MB		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/initval.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/pxa2xx-lib.h>
31
32#include <mach/hardware.h>
7ebc8d56 33#include <mach/dma.h>
1b340bd7
MB		 34#include <mach/regs-ssp.h>
35#include <mach/audio.h>
36#include <mach/ssp.h>
37
38#include "pxa2xx-pcm.h"
39#include "pxa-ssp.h"
40
41/*
42 * SSP audio private data
43 */
44struct ssp_priv {
45 struct ssp_dev dev;
46 unsigned int sysclk;
47 int dai_fmt;
48#ifdef CONFIG_PM
49 struct ssp_state state;
50#endif
51};
52
1b340bd7
MB		 53static void dump_registers(struct ssp_device *ssp)
54{
55 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
56 ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1),
57 ssp_read_reg(ssp, SSTO));
58
59 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
60 ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR),
61 ssp_read_reg(ssp, SSACD));
62}
63
2d7e71fa
EM		 64struct pxa2xx_pcm_dma_data {
65 struct pxa2xx_pcm_dma_params params;
66 char name[20];
1b340bd7
MB		 67};
68
2d7e71fa 69static struct pxa2xx_pcm_dma_params *
8eb9feab 70ssp_get_dma_params(struct ssp_device *ssp, int width4, int out)
2d7e71fa
EM		 71{
72 struct pxa2xx_pcm_dma_data *dma;
73
74 dma = kzalloc(sizeof(struct pxa2xx_pcm_dma_data), GFP_KERNEL);
75 if (dma == NULL)
76 return NULL;
77
78 snprintf(dma->name, 20, "SSP%d PCM %s %s", ssp->port_id,
8eb9feab 79 width4 ? "32-bit" : "16-bit", out ? "out" : "in");
2d7e71fa
EM		 80
81 dma->params.name = dma->name;
82 dma->params.drcmr = &DRCMR(out ? ssp->drcmr_tx : ssp->drcmr_rx);
83 dma->params.dcmd = (out ? (DCMD_INCSRCADDR | DCMD_FLOWTRG) :
84 (DCMD_INCTRGADDR | DCMD_FLOWSRC)) |
8eb9feab 85 (width4 ? DCMD_WIDTH4 : DCMD_WIDTH2) | DCMD_BURST16;
2d7e71fa
EM		 86 dma->params.dev_addr = ssp->phys_base + SSDR;
87
88 return &dma->params;
89}
90
dee89c4d
MB		 91static int pxa_ssp_startup(struct snd_pcm_substream *substream,
92 struct snd_soc_dai *dai)
1b340bd7
MB		 93{
94 struct snd_soc_pcm_runtime *rtd = substream->private_data;
95 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
96 struct ssp_priv *priv = cpu_dai->private_data;
97 int ret = 0;
98
99 if (!cpu_dai->active) {
0664678a
PZ		 100 priv->dev.port = cpu_dai->id + 1;
101 priv->dev.irq = NO_IRQ;
102 clk_enable(priv->dev.ssp->clk);
1b340bd7
MB		 103 ssp_disable(&priv->dev);
104 }
2d7e71fa 105
fd23b7de
DM		 106 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
107 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
108
1b340bd7
MB		 109 return ret;
110}
111
dee89c4d
MB		 112static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
113 struct snd_soc_dai *dai)
1b340bd7
MB		 114{
115 struct snd_soc_pcm_runtime *rtd = substream->private_data;
116 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
117 struct ssp_priv *priv = cpu_dai->private_data;
118
119 if (!cpu_dai->active) {
120 ssp_disable(&priv->dev);
0664678a 121 clk_disable(priv->dev.ssp->clk);
1b340bd7 122 }
2d7e71fa 123
fd23b7de
DM		 124 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
125 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
1b340bd7
MB		 126}
127
128#ifdef CONFIG_PM
129
dc7d7b83 130static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 131{
132 struct ssp_priv *priv = cpu_dai->private_data;
133
134 if (!cpu_dai->active)
026384d6 135 clk_enable(priv->dev.ssp->clk);
1b340bd7
MB		 136
137 ssp_save_state(&priv->dev, &priv->state);
138 clk_disable(priv->dev.ssp->clk);
026384d6 139
1b340bd7
MB		 140 return 0;
141}
142
dc7d7b83 143static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 144{
145 struct ssp_priv *priv = cpu_dai->private_data;
146
1b340bd7
MB		 147 clk_enable(priv->dev.ssp->clk);
148 ssp_restore_state(&priv->dev, &priv->state);
026384d6
DM		 149
150 if (cpu_dai->active)
151 ssp_enable(&priv->dev);
152 else
153 clk_disable(priv->dev.ssp->clk);
1b340bd7
MB		 154
155 return 0;
156}
157
158#else
159#define pxa_ssp_suspend NULL
160#define pxa_ssp_resume NULL
161#endif
162
163/**
164 * ssp_set_clkdiv - set SSP clock divider
165 * @div: serial clock rate divider
166 */
1a297286 167static void ssp_set_scr(struct ssp_device *ssp, u32 div)
1b340bd7 168{
1a297286
PZ		 169 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
170
171 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) {
172 sscr0 &= ~0x0000ff00;
173 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
174 } else {
175 sscr0 &= ~0x000fff00;
176 sscr0 |= (div - 1) << 8; /* 1..4096 */
177 }
178 ssp_write_reg(ssp, SSCR0, sscr0);
179}
180
181/**
182 * ssp_get_clkdiv - get SSP clock divider
183 */
184static u32 ssp_get_scr(struct ssp_device *ssp)
185{
186 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
187 u32 div;
1b340bd7 188
1a297286
PZ		 189 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP)
190 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
191 else
192 div = ((sscr0 >> 8) & 0xfff) + 1;
193 return div;
1b340bd7
MB		 194}
195
196/*
197 * Set the SSP ports SYSCLK.
198 */
199static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
200 int clk_id, unsigned int freq, int dir)
201{
202 struct ssp_priv *priv = cpu_dai->private_data;
203 struct ssp_device *ssp = priv->dev.ssp;
204 int val;
205
206 u32 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 207 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 208
209 dev_dbg(&ssp->pdev->dev,
449bd54d 210 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
1b340bd7
MB		 211 cpu_dai->id, clk_id, freq);
212
213 switch (clk_id) {
214 case PXA_SSP_CLK_NET_PLL:
215 sscr0 |= SSCR0_MOD;
216 break;
217 case PXA_SSP_CLK_PLL:
218 /* Internal PLL is fixed */
219 if (cpu_is_pxa25x())
220 priv->sysclk = 1843200;
221 else
222 priv->sysclk = 13000000;
223 break;
224 case PXA_SSP_CLK_EXT:
225 priv->sysclk = freq;
226 sscr0 |= SSCR0_ECS;
227 break;
228 case PXA_SSP_CLK_NET:
229 priv->sysclk = freq;
230 sscr0 |= SSCR0_NCS | SSCR0_MOD;
231 break;
232 case PXA_SSP_CLK_AUDIO:
233 priv->sysclk = 0;
1a297286 234 ssp_set_scr(ssp, 1);
20a41eac 235 sscr0 |= SSCR0_ACS;
1b340bd7
MB		 236 break;
237 default:
238 return -ENODEV;
239 }
240
241 /* The SSP clock must be disabled when changing SSP clock mode
242 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
243 if (!cpu_is_pxa3xx())
244 clk_disable(priv->dev.ssp->clk);
245 val = ssp_read_reg(ssp, SSCR0) | sscr0;
246 ssp_write_reg(ssp, SSCR0, val);
247 if (!cpu_is_pxa3xx())
248 clk_enable(priv->dev.ssp->clk);
249
250 return 0;
251}
252
253/*
254 * Set the SSP clock dividers.
255 */
256static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
257 int div_id, int div)
258{
259 struct ssp_priv *priv = cpu_dai->private_data;
260 struct ssp_device *ssp = priv->dev.ssp;
261 int val;
262
263 switch (div_id) {
264 case PXA_SSP_AUDIO_DIV_ACDS:
265 val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
266 ssp_write_reg(ssp, SSACD, val);
267 break;
268 case PXA_SSP_AUDIO_DIV_SCDB:
269 val = ssp_read_reg(ssp, SSACD);
270 val &= ~SSACD_SCDB;
271#if defined(CONFIG_PXA3xx)
272 if (cpu_is_pxa3xx())
273 val &= ~SSACD_SCDX8;
274#endif
275 switch (div) {
276 case PXA_SSP_CLK_SCDB_1:
277 val |= SSACD_SCDB;
278 break;
279 case PXA_SSP_CLK_SCDB_4:
280 break;
281#if defined(CONFIG_PXA3xx)
282 case PXA_SSP_CLK_SCDB_8:
283 if (cpu_is_pxa3xx())
284 val |= SSACD_SCDX8;
285 else
286 return -EINVAL;
287 break;
288#endif
289 default:
290 return -EINVAL;
291 }
292 ssp_write_reg(ssp, SSACD, val);
293 break;
294 case PXA_SSP_DIV_SCR:
1a297286 295 ssp_set_scr(ssp, div);
1b340bd7
MB		 296 break;
297 default:
298 return -ENODEV;
299 }
300
301 return 0;
302}
303
304/*
305 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
306 */
85488037
MB		 307static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
308 int source, unsigned int freq_in, unsigned int freq_out)
1b340bd7
MB		 309{
310 struct ssp_priv *priv = cpu_dai->private_data;
311 struct ssp_device *ssp = priv->dev.ssp;
312 u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70;
313
314#if defined(CONFIG_PXA3xx)
315 if (cpu_is_pxa3xx())
316 ssp_write_reg(ssp, SSACDD, 0);
317#endif
318
319 switch (freq_out) {
320 case 5622000:
321 break;
322 case 11345000:
323 ssacd |= (0x1 << 4);
324 break;
325 case 12235000:
326 ssacd |= (0x2 << 4);
327 break;
328 case 14857000:
329 ssacd |= (0x3 << 4);
330 break;
331 case 32842000:
332 ssacd |= (0x4 << 4);
333 break;
334 case 48000000:
335 ssacd |= (0x5 << 4);
336 break;
337 case 0:
338 /* Disable */
339 break;
340
341 default:
342#ifdef CONFIG_PXA3xx
343 /* PXA3xx has a clock ditherer which can be used to generate
344 * a wider range of frequencies - calculate a value for it.
345 */
346 if (cpu_is_pxa3xx()) {
347 u32 val;
348 u64 tmp = 19968;
349 tmp *= 1000000;
350 do_div(tmp, freq_out);
351 val = tmp;
352
a419aef8 353 val = (val << 16) | 64;
1b340bd7
MB		 354 ssp_write_reg(ssp, SSACDD, val);
355
356 ssacd |= (0x6 << 4);
357
358 dev_dbg(&ssp->pdev->dev,
449bd54d 359 "Using SSACDD %x to supply %uHz\n",
1b340bd7
MB		 360 val, freq_out);
361 break;
362 }
363#endif
364
365 return -EINVAL;
366 }
367
368 ssp_write_reg(ssp, SSACD, ssacd);
369
370 return 0;
371}
372
373/*
374 * Set the active slots in TDM/Network mode
375 */
376static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
a5479e38 377 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1b340bd7
MB		 378{
379 struct ssp_priv *priv = cpu_dai->private_data;
380 struct ssp_device *ssp = priv->dev.ssp;
381 u32 sscr0;
382
a5479e38
DR		 383 sscr0 = ssp_read_reg(ssp, SSCR0);
384 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
1b340bd7 385
a5479e38
DR		 386 /* set slot width */
387 if (slot_width > 16)
388 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
389 else
390 sscr0 |= SSCR0_DataSize(slot_width);
391
392 if (slots > 1) {
393 /* enable network mode */
394 sscr0 |= SSCR0_MOD;
395
396 /* set number of active slots */
397 sscr0 |= SSCR0_SlotsPerFrm(slots);
398
399 /* set active slot mask */
400 ssp_write_reg(ssp, SSTSA, tx_mask);
401 ssp_write_reg(ssp, SSRSA, rx_mask);
402 }
1b340bd7
MB		 403 ssp_write_reg(ssp, SSCR0, sscr0);
404
1b340bd7
MB		 405 return 0;
406}
407
408/*
409 * Tristate the SSP DAI lines
410 */
411static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
412 int tristate)
413{
414 struct ssp_priv *priv = cpu_dai->private_data;
415 struct ssp_device *ssp = priv->dev.ssp;
416 u32 sscr1;
417
418 sscr1 = ssp_read_reg(ssp, SSCR1);
419 if (tristate)
420 sscr1 &= ~SSCR1_TTE;
421 else
422 sscr1 |= SSCR1_TTE;
423 ssp_write_reg(ssp, SSCR1, sscr1);
424
425 return 0;
426}
427
428/*
429 * Set up the SSP DAI format.
430 * The SSP Port must be inactive before calling this function as the
431 * physical interface format is changed.
432 */
433static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
434 unsigned int fmt)
435{
436 struct ssp_priv *priv = cpu_dai->private_data;
437 struct ssp_device *ssp = priv->dev.ssp;
438 u32 sscr0;
439 u32 sscr1;
440 u32 sspsp;
441
cbf1146d
DM		 442 /* check if we need to change anything at all */
443 if (priv->dai_fmt == fmt)
444 return 0;
445
446 /* we can only change the settings if the port is not in use */
447 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
448 dev_err(&ssp->pdev->dev,
449 "can't change hardware dai format: stream is in use");
450 return -EINVAL;
451 }
452
1b340bd7
MB		 453 /* reset port settings */
454 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 455 (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 456 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
457 sspsp = 0;
458
459 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
460 case SND_SOC_DAIFMT_CBM_CFM:
461 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
462 break;
463 case SND_SOC_DAIFMT_CBM_CFS:
464 sscr1 |= SSCR1_SCLKDIR;
465 break;
466 case SND_SOC_DAIFMT_CBS_CFS:
467 break;
468 default:
469 return -EINVAL;
470 }
471
fa44c077
DR		 472 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
473 case SND_SOC_DAIFMT_NB_NF:
474 sspsp |= SSPSP_SFRMP;
475 break;
476 case SND_SOC_DAIFMT_NB_IF:
477 break;
478 case SND_SOC_DAIFMT_IB_IF:
479 sspsp |= SSPSP_SCMODE(2);
480 break;
481 case SND_SOC_DAIFMT_IB_NF:
482 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
483 break;
484 default:
485 return -EINVAL;
486 }
1b340bd7
MB		 487
488 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
489 case SND_SOC_DAIFMT_I2S:
72d74664 490 sscr0 |= SSCR0_PSP;
1b340bd7 491 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
0ce36c5f 492 /* See hw_params() */
1b340bd7
MB		 493 break;
494
495 case SND_SOC_DAIFMT_DSP_A:
496 sspsp |= SSPSP_FSRT;
497 case SND_SOC_DAIFMT_DSP_B:
498 sscr0 |= SSCR0_MOD | SSCR0_PSP;
499 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
1b340bd7
MB		 500 break;
501
502 default:
503 return -EINVAL;
504 }
505
506 ssp_write_reg(ssp, SSCR0, sscr0);
507 ssp_write_reg(ssp, SSCR1, sscr1);
508 ssp_write_reg(ssp, SSPSP, sspsp);
509
510 dump_registers(ssp);
511
512 /* Since we are configuring the timings for the format by hand
513 * we have to defer some things until hw_params() where we
514 * know parameters like the sample size.
515 */
516 priv->dai_fmt = fmt;
517
518 return 0;
519}
520
521/*
522 * Set the SSP audio DMA parameters and sample size.
523 * Can be called multiple times by oss emulation.
524 */
525static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 526 struct snd_pcm_hw_params *params,
527 struct snd_soc_dai *dai)
1b340bd7
MB		 528{
529 struct snd_soc_pcm_runtime *rtd = substream->private_data;
530 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
531 struct ssp_priv *priv = cpu_dai->private_data;
532 struct ssp_device *ssp = priv->dev.ssp;
2d7e71fa 533 int chn = params_channels(params);
1b340bd7
MB		 534 u32 sscr0;
535 u32 sspsp;
536 int width = snd_pcm_format_physical_width(params_format(params));
92429069 537 int ttsa = ssp_read_reg(ssp, SSTSA) & 0xf;
fd23b7de
DM		 538 struct pxa2xx_pcm_dma_params *dma_data;
539
540 dma_data = snd_soc_dai_get_dma_data(dai, substream);
1b340bd7 541
2d7e71fa 542 /* generate correct DMA params */
fd23b7de 543 kfree(dma_data);
2d7e71fa 544
92429069
PZ		 545 /* Network mode with one active slot (ttsa == 1) can be used
546 * to force 16-bit frame width on the wire (for S16_LE), even
547 * with two channels. Use 16-bit DMA transfers for this case.
548 */
fd23b7de 549 dma_data = ssp_get_dma_params(ssp,
2d7e71fa
EM		 550 ((chn == 2) && (ttsa != 1)) || (width == 32),
551 substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
1b340bd7 552
fd23b7de
DM		 553 snd_soc_dai_set_dma_data(dai, substream, dma_data);
554
1b340bd7
MB		 555 /* we can only change the settings if the port is not in use */
556 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
557 return 0;
558
559 /* clear selected SSP bits */
560 sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
561 ssp_write_reg(ssp, SSCR0, sscr0);
562
563 /* bit size */
564 sscr0 = ssp_read_reg(ssp, SSCR0);
565 switch (params_format(params)) {
566 case SNDRV_PCM_FORMAT_S16_LE:
567#ifdef CONFIG_PXA3xx
568 if (cpu_is_pxa3xx())
569 sscr0 |= SSCR0_FPCKE;
570#endif
571 sscr0 |= SSCR0_DataSize(16);
1b340bd7
MB		 572 break;
573 case SNDRV_PCM_FORMAT_S24_LE:
574 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
1b340bd7
MB		 575 break;
576 case SNDRV_PCM_FORMAT_S32_LE:
577 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
1b340bd7
MB		 578 break;
579 }
580 ssp_write_reg(ssp, SSCR0, sscr0);
581
582 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
583 case SND_SOC_DAIFMT_I2S:
72d74664
DM		 584 sspsp = ssp_read_reg(ssp, SSPSP);
585
1a297286 586 if ((ssp_get_scr(ssp) == 4) && (width == 16)) {
72d74664
DM		 587 /* This is a special case where the bitclk is 64fs
588 * and we're not dealing with 2*32 bits of audio
589 * samples.
590 *
591 * The SSP values used for that are all found out by
592 * trying and failing a lot; some of the registers
593 * needed for that mode are only available on PXA3xx.
594 */
595
596#ifdef CONFIG_PXA3xx
597 if (!cpu_is_pxa3xx())
598 return -EINVAL;
599
600 sspsp |= SSPSP_SFRMWDTH(width * 2);
601 sspsp |= SSPSP_SFRMDLY(width * 4);
602 sspsp |= SSPSP_EDMYSTOP(3);
603 sspsp |= SSPSP_DMYSTOP(3);
604 sspsp |= SSPSP_DMYSTRT(1);
605#else
606 return -EINVAL;
607#endif
0ce36c5f
MB		 608 } else {
609 /* The frame width is the width the LRCLK is
610 * asserted for; the delay is expressed in
611 * half cycle units. We need the extra cycle
612 * because the data starts clocking out one BCLK
613 * after LRCLK changes polarity.
614 */
615 sspsp |= SSPSP_SFRMWDTH(width + 1);
616 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
617 sspsp |= SSPSP_DMYSTRT(1);
618 }
72d74664 619
1b340bd7
MB		 620 ssp_write_reg(ssp, SSPSP, sspsp);
621 break;
622 default:
623 break;
624 }
625
72d74664 626 /* When we use a network mode, we always require TDM slots
1b340bd7
MB		 627 * - complain loudly and fail if they've not been set up yet.
628 */
92429069 629 if ((sscr0 & SSCR0_MOD) && !ttsa) {
1b340bd7
MB		 630 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
631 return -EINVAL;
632 }
633
634 dump_registers(ssp);
635
636 return 0;
637}
638
dee89c4d
MB		 639static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
640 struct snd_soc_dai *dai)
1b340bd7
MB		 641{
642 struct snd_soc_pcm_runtime *rtd = substream->private_data;
643 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
644 int ret = 0;
645 struct ssp_priv *priv = cpu_dai->private_data;
646 struct ssp_device *ssp = priv->dev.ssp;
647 int val;
648
649 switch (cmd) {
650 case SNDRV_PCM_TRIGGER_RESUME:
651 ssp_enable(&priv->dev);
652 break;
653 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
654 val = ssp_read_reg(ssp, SSCR1);
655 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
656 val |= SSCR1_TSRE;
657 else
658 val |= SSCR1_RSRE;
659 ssp_write_reg(ssp, SSCR1, val);
660 val = ssp_read_reg(ssp, SSSR);
661 ssp_write_reg(ssp, SSSR, val);
662 break;
663 case SNDRV_PCM_TRIGGER_START:
664 val = ssp_read_reg(ssp, SSCR1);
665 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
666 val |= SSCR1_TSRE;
667 else
668 val |= SSCR1_RSRE;
669 ssp_write_reg(ssp, SSCR1, val);
670 ssp_enable(&priv->dev);
671 break;
672 case SNDRV_PCM_TRIGGER_STOP:
673 val = ssp_read_reg(ssp, SSCR1);
674 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
675 val &= ~SSCR1_TSRE;
676 else
677 val &= ~SSCR1_RSRE;
678 ssp_write_reg(ssp, SSCR1, val);
679 break;
680 case SNDRV_PCM_TRIGGER_SUSPEND:
681 ssp_disable(&priv->dev);
682 break;
683 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
684 val = ssp_read_reg(ssp, SSCR1);
685 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
686 val &= ~SSCR1_TSRE;
687 else
688 val &= ~SSCR1_RSRE;
689 ssp_write_reg(ssp, SSCR1, val);
690 break;
691
692 default:
693 ret = -EINVAL;
694 }
695
696 dump_registers(ssp);
697
698 return ret;
699}
700
701static int pxa_ssp_probe(struct platform_device *pdev,
702 struct snd_soc_dai *dai)
703{
704 struct ssp_priv *priv;
705 int ret;
706
707 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
708 if (!priv)
709 return -ENOMEM;
710
0664678a 711 priv->dev.ssp = ssp_request(dai->id + 1, "SoC audio");
1b340bd7
MB		 712 if (priv->dev.ssp == NULL) {
713 ret = -ENODEV;
714 goto err_priv;
715 }
716
a5735b7e 717 priv->dai_fmt = (unsigned int) -1;
1b340bd7
MB		 718 dai->private_data = priv;
719
720 return 0;
721
722err_priv:
723 kfree(priv);
724 return ret;
725}
726
727static void pxa_ssp_remove(struct platform_device *pdev,
728 struct snd_soc_dai *dai)
729{
730 struct ssp_priv *priv = dai->private_data;
731 ssp_free(priv->dev.ssp);
732}
733
734#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
735 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
736 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
737 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
738
739#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
740 SNDRV_PCM_FMTBIT_S24_LE | \
741 SNDRV_PCM_FMTBIT_S32_LE)
742
6335d055
EM		 743static struct snd_soc_dai_ops pxa_ssp_dai_ops = {
744 .startup = pxa_ssp_startup,
745 .shutdown = pxa_ssp_shutdown,
746 .trigger = pxa_ssp_trigger,
747 .hw_params = pxa_ssp_hw_params,
748 .set_sysclk = pxa_ssp_set_dai_sysclk,
749 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
750 .set_pll = pxa_ssp_set_dai_pll,
751 .set_fmt = pxa_ssp_set_dai_fmt,
752 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
753 .set_tristate = pxa_ssp_set_dai_tristate,
754};
755
1b340bd7
MB		 756struct snd_soc_dai pxa_ssp_dai[] = {
757 {
758 .name = "pxa2xx-ssp1",
759 .id = 0,
1b340bd7
MB		 760 .probe = pxa_ssp_probe,
761 .remove = pxa_ssp_remove,
762 .suspend = pxa_ssp_suspend,
763 .resume = pxa_ssp_resume,
764 .playback = {
765 .channels_min = 1,
f34762b6 766 .channels_max = 8,
1b340bd7
MB		 767 .rates = PXA_SSP_RATES,
768 .formats = PXA_SSP_FORMATS,
769 },
770 .capture = {
771 .channels_min = 1,
f34762b6 772 .channels_max = 8,
1b340bd7
MB		 773 .rates = PXA_SSP_RATES,
774 .formats = PXA_SSP_FORMATS,
775 },
6335d055 776 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 777 },
778 { .name = "pxa2xx-ssp2",
779 .id = 1,
1b340bd7
MB		 780 .probe = pxa_ssp_probe,
781 .remove = pxa_ssp_remove,
782 .suspend = pxa_ssp_suspend,
783 .resume = pxa_ssp_resume,
784 .playback = {
785 .channels_min = 1,
f34762b6 786 .channels_max = 8,
1b340bd7
MB		 787 .rates = PXA_SSP_RATES,
788 .formats = PXA_SSP_FORMATS,
789 },
790 .capture = {
791 .channels_min = 1,
f34762b6 792 .channels_max = 8,
1b340bd7
MB		 793 .rates = PXA_SSP_RATES,
794 .formats = PXA_SSP_FORMATS,
795 },
6335d055 796 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 797 },
798 {
799 .name = "pxa2xx-ssp3",
800 .id = 2,
1b340bd7
MB		 801 .probe = pxa_ssp_probe,
802 .remove = pxa_ssp_remove,
803 .suspend = pxa_ssp_suspend,
804 .resume = pxa_ssp_resume,
805 .playback = {
806 .channels_min = 1,
f34762b6 807 .channels_max = 8,
1b340bd7
MB		 808 .rates = PXA_SSP_RATES,
809 .formats = PXA_SSP_FORMATS,
810 },
811 .capture = {
812 .channels_min = 1,
f34762b6 813 .channels_max = 8,
1b340bd7
MB		 814 .rates = PXA_SSP_RATES,
815 .formats = PXA_SSP_FORMATS,
816 },
6335d055 817 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 818 },
819 {
820 .name = "pxa2xx-ssp4",
821 .id = 3,
1b340bd7
MB		 822 .probe = pxa_ssp_probe,
823 .remove = pxa_ssp_remove,
824 .suspend = pxa_ssp_suspend,
825 .resume = pxa_ssp_resume,
826 .playback = {
827 .channels_min = 1,
f34762b6 828 .channels_max = 8,
1b340bd7
MB		 829 .rates = PXA_SSP_RATES,
830 .formats = PXA_SSP_FORMATS,
831 },
832 .capture = {
833 .channels_min = 1,
f34762b6 834 .channels_max = 8,
1b340bd7
MB		 835 .rates = PXA_SSP_RATES,
836 .formats = PXA_SSP_FORMATS,
837 },
6335d055 838 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 839 },
840};
841EXPORT_SYMBOL_GPL(pxa_ssp_dai);
842
c9b3a40f 843static int __init pxa_ssp_init(void)
3f4b783c
MB		 844{
845 return snd_soc_register_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
846}
847module_init(pxa_ssp_init);
848
849static void __exit pxa_ssp_exit(void)
850{
851 snd_soc_unregister_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
852}
853module_exit(pxa_ssp_exit);
854
1b340bd7
MB		 855/* Module information */
856MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
857MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
858MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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