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75b41027 LG |
1 | /* |
2 | * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip. | |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Dec 02, 2004 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/wait.h> | |
942de47b | 18 | #include <linux/clk.h> |
75b41027 LG |
19 | #include <linux/delay.h> |
20 | ||
75b41027 LG |
21 | #include <sound/core.h> |
22 | #include <sound/pcm.h> | |
23 | #include <sound/ac97_codec.h> | |
24 | #include <sound/initval.h> | |
25 | #include <sound/soc.h> | |
26 | ||
27 | #include <asm/irq.h> | |
28 | #include <linux/mutex.h> | |
29 | #include <asm/hardware.h> | |
30 | #include <asm/arch/pxa-regs.h> | |
a683b14d | 31 | #include <asm/arch/pxa2xx-gpio.h> |
75b41027 LG |
32 | #include <asm/arch/audio.h> |
33 | ||
34 | #include "pxa2xx-pcm.h" | |
596ce32b | 35 | #include "pxa2xx-ac97.h" |
75b41027 LG |
36 | |
37 | static DEFINE_MUTEX(car_mutex); | |
38 | static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); | |
39 | static volatile long gsr_bits; | |
942de47b MB |
40 | static struct clk *ac97_clk; |
41 | #ifdef CONFIG_PXA27x | |
42 | static struct clk *ac97conf_clk; | |
43 | #endif | |
75b41027 | 44 | |
75b41027 LG |
45 | /* |
46 | * Beware PXA27x bugs: | |
47 | * | |
48 | * o Slot 12 read from modem space will hang controller. | |
49 | * o CDONE, SDONE interrupt fails after any slot 12 IO. | |
50 | * | |
51 | * We therefore have an hybrid approach for waiting on SDONE (interrupt or | |
52 | * 1 jiffy timeout if interrupt never comes). | |
53 | */ | |
54 | ||
55 | static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, | |
56 | unsigned short reg) | |
57 | { | |
58 | unsigned short val = -1; | |
59 | volatile u32 *reg_addr; | |
60 | ||
61 | mutex_lock(&car_mutex); | |
62 | ||
63 | /* set up primary or secondary codec/modem space */ | |
7a22323b | 64 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
75b41027 LG |
65 | reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; |
66 | #else | |
67 | if (reg == AC97_GPIO_STATUS) | |
68 | reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; | |
69 | else | |
70 | reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; | |
71 | #endif | |
72 | reg_addr += (reg >> 1); | |
73 | ||
74 | #ifndef CONFIG_PXA27x | |
75 | if (reg == AC97_GPIO_STATUS) { | |
76 | /* read from controller cache */ | |
77 | val = *reg_addr; | |
78 | goto out; | |
79 | } | |
80 | #endif | |
81 | ||
82 | /* start read access across the ac97 link */ | |
83 | GSR = GSR_CDONE | GSR_SDONE; | |
84 | gsr_bits = 0; | |
85 | val = *reg_addr; | |
86 | ||
87 | wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); | |
88 | if (!((GSR | gsr_bits) & GSR_SDONE)) { | |
89 | printk(KERN_ERR "%s: read error (ac97_reg=%x GSR=%#lx)\n", | |
9bf8e7dd | 90 | __func__, reg, GSR | gsr_bits); |
75b41027 LG |
91 | val = -1; |
92 | goto out; | |
93 | } | |
94 | ||
95 | /* valid data now */ | |
96 | GSR = GSR_CDONE | GSR_SDONE; | |
97 | gsr_bits = 0; | |
98 | val = *reg_addr; | |
99 | /* but we've just started another cycle... */ | |
100 | wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); | |
101 | ||
102 | out: mutex_unlock(&car_mutex); | |
103 | return val; | |
104 | } | |
105 | ||
106 | static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, | |
107 | unsigned short val) | |
108 | { | |
109 | volatile u32 *reg_addr; | |
110 | ||
111 | mutex_lock(&car_mutex); | |
112 | ||
113 | /* set up primary or secondary codec/modem space */ | |
7a22323b | 114 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
75b41027 LG |
115 | reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; |
116 | #else | |
117 | if (reg == AC97_GPIO_STATUS) | |
118 | reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; | |
119 | else | |
120 | reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; | |
121 | #endif | |
122 | reg_addr += (reg >> 1); | |
123 | ||
124 | GSR = GSR_CDONE | GSR_SDONE; | |
125 | gsr_bits = 0; | |
126 | *reg_addr = val; | |
127 | wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1); | |
128 | if (!((GSR | gsr_bits) & GSR_CDONE)) | |
129 | printk(KERN_ERR "%s: write error (ac97_reg=%x GSR=%#lx)\n", | |
9bf8e7dd | 130 | __func__, reg, GSR | gsr_bits); |
75b41027 LG |
131 | |
132 | mutex_unlock(&car_mutex); | |
133 | } | |
134 | ||
135 | static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97) | |
136 | { | |
7a22323b MB |
137 | #ifdef CONFIG_PXA3xx |
138 | int timeout = 100; | |
139 | #endif | |
75b41027 LG |
140 | gsr_bits = 0; |
141 | ||
142 | #ifdef CONFIG_PXA27x | |
143 | /* warm reset broken on Bulverde, | |
144 | so manually keep AC97 reset high */ | |
145 | pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH); | |
146 | udelay(10); | |
147 | GCR |= GCR_WARM_RST; | |
148 | pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); | |
149 | udelay(500); | |
7a22323b MB |
150 | #elif defined(CONFIG_PXA3xx) |
151 | /* Can't use interrupts */ | |
152 | GCR |= GCR_WARM_RST; | |
153 | while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--) | |
154 | mdelay(1); | |
75b41027 LG |
155 | #else |
156 | GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN; | |
157 | wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); | |
158 | #endif | |
159 | ||
160 | if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) | |
161 | printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n", | |
9bf8e7dd | 162 | __func__, gsr_bits); |
75b41027 LG |
163 | |
164 | GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); | |
165 | GCR |= GCR_SDONE_IE|GCR_CDONE_IE; | |
166 | } | |
167 | ||
168 | static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97) | |
169 | { | |
7a22323b MB |
170 | #ifdef CONFIG_PXA3xx |
171 | int timeout = 1000; | |
172 | ||
173 | /* Hold CLKBPB for 100us */ | |
174 | GCR = 0; | |
175 | GCR = GCR_CLKBPB; | |
176 | udelay(100); | |
177 | GCR = 0; | |
178 | #endif | |
179 | ||
75b41027 LG |
180 | GCR &= GCR_COLD_RST; /* clear everything but nCRST */ |
181 | GCR &= ~GCR_COLD_RST; /* then assert nCRST */ | |
182 | ||
183 | gsr_bits = 0; | |
184 | #ifdef CONFIG_PXA27x | |
185 | /* PXA27x Developers Manual section 13.5.2.2.1 */ | |
942de47b | 186 | clk_enable(ac97conf_clk); |
75b41027 | 187 | udelay(5); |
942de47b | 188 | clk_disable(ac97conf_clk); |
75b41027 LG |
189 | GCR = GCR_COLD_RST; |
190 | udelay(50); | |
7a22323b MB |
191 | #elif defined(CONFIG_PXA3xx) |
192 | /* Can't use interrupts on PXA3xx */ | |
193 | GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); | |
194 | ||
195 | GCR = GCR_WARM_RST | GCR_COLD_RST; | |
196 | while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--) | |
197 | mdelay(10); | |
75b41027 LG |
198 | #else |
199 | GCR = GCR_COLD_RST; | |
200 | GCR |= GCR_CDONE_IE|GCR_SDONE_IE; | |
201 | wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); | |
202 | #endif | |
203 | ||
204 | if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) | |
205 | printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n", | |
9bf8e7dd | 206 | __func__, gsr_bits); |
75b41027 LG |
207 | |
208 | GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); | |
209 | GCR |= GCR_SDONE_IE|GCR_CDONE_IE; | |
210 | } | |
211 | ||
212 | static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id) | |
213 | { | |
214 | long status; | |
215 | ||
216 | status = GSR; | |
217 | if (status) { | |
218 | GSR = status; | |
219 | gsr_bits |= status; | |
220 | wake_up(&gsr_wq); | |
221 | ||
222 | #ifdef CONFIG_PXA27x | |
223 | /* Although we don't use those we still need to clear them | |
224 | since they tend to spuriously trigger when MMC is used | |
225 | (hardware bug? go figure)... */ | |
226 | MISR = MISR_EOC; | |
227 | PISR = PISR_EOC; | |
228 | MCSR = MCSR_EOC; | |
229 | #endif | |
230 | ||
231 | return IRQ_HANDLED; | |
232 | } | |
233 | ||
234 | return IRQ_NONE; | |
235 | } | |
236 | ||
237 | struct snd_ac97_bus_ops soc_ac97_ops = { | |
238 | .read = pxa2xx_ac97_read, | |
239 | .write = pxa2xx_ac97_write, | |
240 | .warm_reset = pxa2xx_ac97_warm_reset, | |
241 | .reset = pxa2xx_ac97_cold_reset, | |
242 | }; | |
243 | ||
244 | static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = { | |
245 | .name = "AC97 PCM Stereo out", | |
246 | .dev_addr = __PREG(PCDR), | |
247 | .drcmr = &DRCMRTXPCDR, | |
248 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
249 | DCMD_BURST32 | DCMD_WIDTH4, | |
250 | }; | |
251 | ||
252 | static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = { | |
253 | .name = "AC97 PCM Stereo in", | |
254 | .dev_addr = __PREG(PCDR), | |
255 | .drcmr = &DRCMRRXPCDR, | |
256 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
257 | DCMD_BURST32 | DCMD_WIDTH4, | |
258 | }; | |
259 | ||
260 | static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = { | |
261 | .name = "AC97 Aux PCM (Slot 5) Mono out", | |
262 | .dev_addr = __PREG(MODR), | |
263 | .drcmr = &DRCMRTXMODR, | |
264 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
265 | DCMD_BURST16 | DCMD_WIDTH2, | |
266 | }; | |
267 | ||
268 | static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = { | |
269 | .name = "AC97 Aux PCM (Slot 5) Mono in", | |
270 | .dev_addr = __PREG(MODR), | |
271 | .drcmr = &DRCMRRXMODR, | |
272 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
273 | DCMD_BURST16 | DCMD_WIDTH2, | |
274 | }; | |
275 | ||
276 | static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_mic_mono_in = { | |
277 | .name = "AC97 Mic PCM (Slot 6) Mono in", | |
278 | .dev_addr = __PREG(MCDR), | |
279 | .drcmr = &DRCMRRXMCDR, | |
280 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
281 | DCMD_BURST16 | DCMD_WIDTH2, | |
282 | }; | |
283 | ||
284 | #ifdef CONFIG_PM | |
285 | static int pxa2xx_ac97_suspend(struct platform_device *pdev, | |
286 | struct snd_soc_cpu_dai *dai) | |
287 | { | |
288 | GCR |= GCR_ACLINK_OFF; | |
942de47b | 289 | clk_disable(ac97_clk); |
75b41027 LG |
290 | return 0; |
291 | } | |
292 | ||
293 | static int pxa2xx_ac97_resume(struct platform_device *pdev, | |
294 | struct snd_soc_cpu_dai *dai) | |
295 | { | |
296 | pxa_gpio_mode(GPIO31_SYNC_AC97_MD); | |
297 | pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); | |
298 | pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); | |
299 | pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); | |
300 | #ifdef CONFIG_PXA27x | |
301 | /* Use GPIO 113 as AC97 Reset on Bulverde */ | |
302 | pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); | |
303 | #endif | |
942de47b | 304 | clk_enable(ac97_clk); |
75b41027 LG |
305 | return 0; |
306 | } | |
307 | ||
308 | #else | |
309 | #define pxa2xx_ac97_suspend NULL | |
310 | #define pxa2xx_ac97_resume NULL | |
311 | #endif | |
312 | ||
313 | static int pxa2xx_ac97_probe(struct platform_device *pdev) | |
314 | { | |
315 | int ret; | |
316 | ||
317 | ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL); | |
318 | if (ret < 0) | |
319 | goto err; | |
320 | ||
321 | pxa_gpio_mode(GPIO31_SYNC_AC97_MD); | |
322 | pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); | |
323 | pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); | |
324 | pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); | |
325 | #ifdef CONFIG_PXA27x | |
326 | /* Use GPIO 113 as AC97 Reset on Bulverde */ | |
327 | pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); | |
942de47b MB |
328 | |
329 | ac97conf_clk = clk_get(&pdev->dev, "AC97CONFCLK"); | |
330 | if (IS_ERR(ac97conf_clk)) { | |
331 | ret = PTR_ERR(ac97conf_clk); | |
332 | ac97conf_clk = NULL; | |
333 | goto err_irq; | |
334 | } | |
75b41027 | 335 | #endif |
942de47b MB |
336 | ac97_clk = clk_get(&pdev->dev, "AC97CLK"); |
337 | if (IS_ERR(ac97_clk)) { | |
338 | ret = PTR_ERR(ac97_clk); | |
339 | ac97_clk = NULL; | |
340 | goto err_irq; | |
341 | } | |
b907ef68 | 342 | clk_enable(ac97_clk); |
75b41027 LG |
343 | return 0; |
344 | ||
942de47b MB |
345 | err_irq: |
346 | GCR |= GCR_ACLINK_OFF; | |
347 | #ifdef CONFIG_PXA27x | |
348 | if (ac97conf_clk) { | |
349 | clk_put(ac97conf_clk); | |
350 | ac97conf_clk = NULL; | |
75b41027 | 351 | } |
942de47b MB |
352 | #endif |
353 | free_irq(IRQ_AC97, NULL); | |
354 | err: | |
75b41027 LG |
355 | return ret; |
356 | } | |
357 | ||
358 | static void pxa2xx_ac97_remove(struct platform_device *pdev) | |
359 | { | |
360 | GCR |= GCR_ACLINK_OFF; | |
361 | free_irq(IRQ_AC97, NULL); | |
942de47b MB |
362 | #ifdef CONFIG_PXA27x |
363 | clk_put(ac97conf_clk); | |
364 | ac97conf_clk = NULL; | |
365 | #endif | |
366 | clk_disable(ac97_clk); | |
367 | clk_put(ac97_clk); | |
368 | ac97_clk = NULL; | |
75b41027 LG |
369 | } |
370 | ||
371 | static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream, | |
372 | struct snd_pcm_hw_params *params) | |
373 | { | |
374 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
596ce32b | 375 | struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; |
75b41027 LG |
376 | |
377 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
596ce32b | 378 | cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_out; |
75b41027 | 379 | else |
596ce32b | 380 | cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_in; |
75b41027 LG |
381 | |
382 | return 0; | |
383 | } | |
384 | ||
385 | static int pxa2xx_ac97_hw_aux_params(struct snd_pcm_substream *substream, | |
386 | struct snd_pcm_hw_params *params) | |
387 | { | |
388 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
596ce32b | 389 | struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; |
75b41027 LG |
390 | |
391 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
596ce32b | 392 | cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_out; |
75b41027 | 393 | else |
596ce32b | 394 | cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_in; |
75b41027 LG |
395 | |
396 | return 0; | |
397 | } | |
398 | ||
399 | static int pxa2xx_ac97_hw_mic_params(struct snd_pcm_substream *substream, | |
400 | struct snd_pcm_hw_params *params) | |
401 | { | |
402 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
596ce32b | 403 | struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; |
75b41027 LG |
404 | |
405 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
406 | return -ENODEV; | |
407 | else | |
596ce32b | 408 | cpu_dai->dma_data = &pxa2xx_ac97_pcm_mic_mono_in; |
75b41027 LG |
409 | |
410 | return 0; | |
411 | } | |
412 | ||
596ce32b LG |
413 | #define PXA2XX_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ |
414 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ | |
415 | SNDRV_PCM_RATE_48000) | |
416 | ||
75b41027 LG |
417 | /* |
418 | * There is only 1 physical AC97 interface for pxa2xx, but it | |
419 | * has extra fifo's that can be used for aux DACs and ADCs. | |
420 | */ | |
421 | struct snd_soc_cpu_dai pxa_ac97_dai[] = { | |
422 | { | |
423 | .name = "pxa2xx-ac97", | |
424 | .id = 0, | |
425 | .type = SND_SOC_DAI_AC97, | |
426 | .probe = pxa2xx_ac97_probe, | |
427 | .remove = pxa2xx_ac97_remove, | |
428 | .suspend = pxa2xx_ac97_suspend, | |
429 | .resume = pxa2xx_ac97_resume, | |
430 | .playback = { | |
431 | .stream_name = "AC97 Playback", | |
432 | .channels_min = 2, | |
596ce32b LG |
433 | .channels_max = 2, |
434 | .rates = PXA2XX_AC97_RATES, | |
435 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
75b41027 LG |
436 | .capture = { |
437 | .stream_name = "AC97 Capture", | |
438 | .channels_min = 2, | |
596ce32b LG |
439 | .channels_max = 2, |
440 | .rates = PXA2XX_AC97_RATES, | |
441 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
75b41027 LG |
442 | .ops = { |
443 | .hw_params = pxa2xx_ac97_hw_params,}, | |
75b41027 LG |
444 | }, |
445 | { | |
446 | .name = "pxa2xx-ac97-aux", | |
447 | .id = 1, | |
448 | .type = SND_SOC_DAI_AC97, | |
449 | .playback = { | |
450 | .stream_name = "AC97 Aux Playback", | |
451 | .channels_min = 1, | |
596ce32b LG |
452 | .channels_max = 1, |
453 | .rates = PXA2XX_AC97_RATES, | |
454 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
75b41027 LG |
455 | .capture = { |
456 | .stream_name = "AC97 Aux Capture", | |
457 | .channels_min = 1, | |
596ce32b LG |
458 | .channels_max = 1, |
459 | .rates = PXA2XX_AC97_RATES, | |
460 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
75b41027 LG |
461 | .ops = { |
462 | .hw_params = pxa2xx_ac97_hw_aux_params,}, | |
75b41027 LG |
463 | }, |
464 | { | |
465 | .name = "pxa2xx-ac97-mic", | |
466 | .id = 2, | |
467 | .type = SND_SOC_DAI_AC97, | |
468 | .capture = { | |
469 | .stream_name = "AC97 Mic Capture", | |
470 | .channels_min = 1, | |
596ce32b LG |
471 | .channels_max = 1, |
472 | .rates = PXA2XX_AC97_RATES, | |
473 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
75b41027 LG |
474 | .ops = { |
475 | .hw_params = pxa2xx_ac97_hw_mic_params,}, | |
596ce32b | 476 | }, |
75b41027 LG |
477 | }; |
478 | ||
479 | EXPORT_SYMBOL_GPL(pxa_ac97_dai); | |
480 | EXPORT_SYMBOL_GPL(soc_ac97_ops); | |
481 | ||
482 | MODULE_AUTHOR("Nicolas Pitre"); | |
483 | MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip"); | |
484 | MODULE_LICENSE("GPL"); |