projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| cd59f138 KW |
1 | /* |
| 2 | * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 and | |
| 6 | * only version 2 as published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope that it will be useful, | |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 11 | * GNU General Public License for more details. | |
| cd59f138 KW |
12 | */ |
| 13 | ||
| 9bae4880 SK |
14 | #ifndef __LPASS_LPAIF_REG_H__ |
| 15 | #define __LPASS_LPAIF_REG_H__ | |
| cd59f138 KW |
16 | |
| 17 | /* LPAIF I2S */ | |
| 18 | ||
| 9bae4880 SK |
19 | #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \ |
| 20 | (v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port)) | |
| cd59f138 | 21 | |
| 9bae4880 | 22 | #define LPAIF_I2SCTL_REG(v, port) LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port)) |
| cd59f138 KW |
23 | #define LPAIF_I2SCTL_LOOPBACK_MASK 0x8000 |
| 24 | #define LPAIF_I2SCTL_LOOPBACK_SHIFT 15 | |
| 25 | #define LPAIF_I2SCTL_LOOPBACK_DISABLE (0 << LPAIF_I2SCTL_LOOPBACK_SHIFT) | |
| 26 | #define LPAIF_I2SCTL_LOOPBACK_ENABLE (1 << LPAIF_I2SCTL_LOOPBACK_SHIFT) | |
| 27 | ||
| 28 | #define LPAIF_I2SCTL_SPKEN_MASK 0x4000 | |
| 29 | #define LPAIF_I2SCTL_SPKEN_SHIFT 14 | |
| 30 | #define LPAIF_I2SCTL_SPKEN_DISABLE (0 << LPAIF_I2SCTL_SPKEN_SHIFT) | |
| 31 | #define LPAIF_I2SCTL_SPKEN_ENABLE (1 << LPAIF_I2SCTL_SPKEN_SHIFT) | |
| 32 | ||
| 33 | #define LPAIF_I2SCTL_SPKMODE_MASK 0x3C00 | |
| 34 | #define LPAIF_I2SCTL_SPKMODE_SHIFT 10 | |
| 35 | #define LPAIF_I2SCTL_SPKMODE_NONE (0 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 36 | #define LPAIF_I2SCTL_SPKMODE_SD0 (1 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 37 | #define LPAIF_I2SCTL_SPKMODE_SD1 (2 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 38 | #define LPAIF_I2SCTL_SPKMODE_SD2 (3 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 39 | #define LPAIF_I2SCTL_SPKMODE_SD3 (4 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 40 | #define LPAIF_I2SCTL_SPKMODE_QUAD01 (5 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 41 | #define LPAIF_I2SCTL_SPKMODE_QUAD23 (6 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 42 | #define LPAIF_I2SCTL_SPKMODE_6CH (7 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 43 | #define LPAIF_I2SCTL_SPKMODE_8CH (8 << LPAIF_I2SCTL_SPKMODE_SHIFT) | |
| 44 | ||
| 45 | #define LPAIF_I2SCTL_SPKMONO_MASK 0x0200 | |
| 46 | #define LPAIF_I2SCTL_SPKMONO_SHIFT 9 | |
| 47 | #define LPAIF_I2SCTL_SPKMONO_STEREO (0 << LPAIF_I2SCTL_SPKMONO_SHIFT) | |
| 48 | #define LPAIF_I2SCTL_SPKMONO_MONO (1 << LPAIF_I2SCTL_SPKMONO_SHIFT) | |
| 49 | ||
| 50 | #define LPAIF_I2SCTL_WSSRC_MASK 0x0004 | |
| 51 | #define LPAIF_I2SCTL_WSSRC_SHIFT 2 | |
| 52 | #define LPAIF_I2SCTL_WSSRC_INTERNAL (0 << LPAIF_I2SCTL_WSSRC_SHIFT) | |
| 53 | #define LPAIF_I2SCTL_WSSRC_EXTERNAL (1 << LPAIF_I2SCTL_WSSRC_SHIFT) | |
| 54 | ||
| 55 | #define LPAIF_I2SCTL_BITWIDTH_MASK 0x0003 | |
| 56 | #define LPAIF_I2SCTL_BITWIDTH_SHIFT 0 | |
| 57 | #define LPAIF_I2SCTL_BITWIDTH_16 (0 << LPAIF_I2SCTL_BITWIDTH_SHIFT) | |
| 58 | #define LPAIF_I2SCTL_BITWIDTH_24 (1 << LPAIF_I2SCTL_BITWIDTH_SHIFT) | |
| 59 | #define LPAIF_I2SCTL_BITWIDTH_32 (2 << LPAIF_I2SCTL_BITWIDTH_SHIFT) | |
| 60 | ||
| 61 | /* LPAIF IRQ */ | |
| 9bae4880 SK |
62 | #define LPAIF_IRQ_REG_ADDR(v, addr, port) \ |
| 63 | (v->irq_reg_base + (addr) + v->irq_reg_stride * (port)) | |
| cd59f138 | 64 | |
| 9bae4880 | 65 | #define LPAIF_IRQ_PORT_HOST 0 |
| cd59f138 | 66 | |
| 9bae4880 SK |
67 | #define LPAIF_IRQEN_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x0, (port)) |
| 68 | #define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4, (port)) | |
| 69 | #define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC, (port)) | |
| cd59f138 KW |
70 | |
| 71 | #define LPAIF_IRQ_BITSTRIDE 3 | |
| 9bae4880 | 72 | |
| cd59f138 KW |
73 | #define LPAIF_IRQ_PER(chan) (1 << (LPAIF_IRQ_BITSTRIDE * (chan))) |
| 74 | #define LPAIF_IRQ_XRUN(chan) (2 << (LPAIF_IRQ_BITSTRIDE * (chan))) | |
| 75 | #define LPAIF_IRQ_ERR(chan) (4 << (LPAIF_IRQ_BITSTRIDE * (chan))) | |
| 9bae4880 | 76 | |
| cd59f138 KW |
77 | #define LPAIF_IRQ_ALL(chan) (7 << (LPAIF_IRQ_BITSTRIDE * (chan))) |
| 78 | ||
| 79 | /* LPAIF DMA */ | |
| 80 | ||
| 9bae4880 SK |
81 | #define LPAIF_RDMA_REG_ADDR(v, addr, chan) \ |
| 82 | (v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan)) | |
| cd59f138 | 83 | |
| 9bae4880 | 84 | #define LPAIF_RDMACTL_AUDINTF(id) (id << LPAIF_RDMACTL_AUDINTF_SHIFT) |
| cd59f138 | 85 | |
| 9bae4880 SK |
86 | #define LPAIF_RDMACTL_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x00, (chan)) |
| 87 | #define LPAIF_RDMABASE_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x04, (chan)) | |
| 88 | #define LPAIF_RDMABUFF_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x08, (chan)) | |
| 89 | #define LPAIF_RDMACURR_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x0C, (chan)) | |
| 90 | #define LPAIF_RDMAPER_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x10, (chan)) | |
| 91 | #define LPAIF_RDMAPERCNT_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x14, (chan)) | |
| cd59f138 KW |
92 | |
| 93 | #define LPAIF_RDMACTL_BURSTEN_MASK 0x800 | |
| 94 | #define LPAIF_RDMACTL_BURSTEN_SHIFT 11 | |
| 95 | #define LPAIF_RDMACTL_BURSTEN_SINGLE (0 << LPAIF_RDMACTL_BURSTEN_SHIFT) | |
| 96 | #define LPAIF_RDMACTL_BURSTEN_INCR4 (1 << LPAIF_RDMACTL_BURSTEN_SHIFT) | |
| 97 | ||
| 98 | #define LPAIF_RDMACTL_WPSCNT_MASK 0x700 | |
| 99 | #define LPAIF_RDMACTL_WPSCNT_SHIFT 8 | |
| 100 | #define LPAIF_RDMACTL_WPSCNT_ONE (0 << LPAIF_RDMACTL_WPSCNT_SHIFT) | |
| 101 | #define LPAIF_RDMACTL_WPSCNT_TWO (1 << LPAIF_RDMACTL_WPSCNT_SHIFT) | |
| 102 | #define LPAIF_RDMACTL_WPSCNT_THREE (2 << LPAIF_RDMACTL_WPSCNT_SHIFT) | |
| 103 | #define LPAIF_RDMACTL_WPSCNT_FOUR (3 << LPAIF_RDMACTL_WPSCNT_SHIFT) | |
| 104 | #define LPAIF_RDMACTL_WPSCNT_SIX (5 << LPAIF_RDMACTL_WPSCNT_SHIFT) | |
| 105 | #define LPAIF_RDMACTL_WPSCNT_EIGHT (7 << LPAIF_RDMACTL_WPSCNT_SHIFT) | |
| 106 | ||
| 107 | #define LPAIF_RDMACTL_AUDINTF_MASK 0x0F0 | |
| 108 | #define LPAIF_RDMACTL_AUDINTF_SHIFT 4 | |
| cd59f138 KW |
109 | |
| 110 | #define LPAIF_RDMACTL_FIFOWM_MASK 0x00E | |
| 111 | #define LPAIF_RDMACTL_FIFOWM_SHIFT 1 | |
| 112 | #define LPAIF_RDMACTL_FIFOWM_1 (0 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 113 | #define LPAIF_RDMACTL_FIFOWM_2 (1 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 114 | #define LPAIF_RDMACTL_FIFOWM_3 (2 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 115 | #define LPAIF_RDMACTL_FIFOWM_4 (3 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 116 | #define LPAIF_RDMACTL_FIFOWM_5 (4 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 117 | #define LPAIF_RDMACTL_FIFOWM_6 (5 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 118 | #define LPAIF_RDMACTL_FIFOWM_7 (6 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 119 | #define LPAIF_RDMACTL_FIFOWM_8 (7 << LPAIF_RDMACTL_FIFOWM_SHIFT) | |
| 120 | ||
| 121 | #define LPAIF_RDMACTL_ENABLE_MASK 0x1 | |
| 122 | #define LPAIF_RDMACTL_ENABLE_SHIFT 0 | |
| 123 | #define LPAIF_RDMACTL_ENABLE_OFF (0 << LPAIF_RDMACTL_ENABLE_SHIFT) | |
| 124 | #define LPAIF_RDMACTL_ENABLE_ON (1 << LPAIF_RDMACTL_ENABLE_SHIFT) | |
| 125 | ||
| 9bae4880 | 126 | #endif /* __LPASS_LPAIF_REG_H__ */ |