[deliverable/linux.git] / sound / soc / qcom / lpass-platform.c

/*
 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
 */

#include <linux/dma-mapping.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/pcm_params.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"

struct lpass_pcm_data {
	int rdma_ch;
	int i2s_port;
};

#define LPASS_PLATFORM_BUFFER_SIZE	(16 * 1024)
#define LPASS_PLATFORM_PERIODS		2

static struct snd_pcm_hardware lpass_platform_pcm_hardware = {
	.info			=	SNDRV_PCM_INFO_MMAP |
					SNDRV_PCM_INFO_MMAP_VALID |
					SNDRV_PCM_INFO_INTERLEAVED |
					SNDRV_PCM_INFO_PAUSE |
					SNDRV_PCM_INFO_RESUME,
	.formats		=	SNDRV_PCM_FMTBIT_S16 |
					SNDRV_PCM_FMTBIT_S24 |
					SNDRV_PCM_FMTBIT_S32,
	.rates			=	SNDRV_PCM_RATE_8000_192000,
	.rate_min		=	8000,
	.rate_max		=	192000,
	.channels_min		=	1,
	.channels_max		=	8,
	.buffer_bytes_max	=	LPASS_PLATFORM_BUFFER_SIZE,
	.period_bytes_max	=	LPASS_PLATFORM_BUFFER_SIZE /
						LPASS_PLATFORM_PERIODS,
	.period_bytes_min	=	LPASS_PLATFORM_BUFFER_SIZE /
						LPASS_PLATFORM_PERIODS,
	.periods_min		=	LPASS_PLATFORM_PERIODS,
	.periods_max		=	LPASS_PLATFORM_PERIODS,
	.fifo_size		=	0,
};

static int lpass_platform_pcmops_open(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	int ret;

	snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);

	runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;

	ret = snd_pcm_hw_constraint_integer(runtime,
			SNDRV_PCM_HW_PARAM_PERIODS);
	if (ret < 0) {
		dev_err(soc_runtime->dev, "%s() setting constraints failed: %d\n",
				__func__, ret);
		return -EINVAL;
	}

	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);

	return 0;
}

static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
		struct snd_pcm_hw_params *params)
{
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_variant *v = drvdata->variant;
	snd_pcm_format_t format = params_format(params);
	unsigned int channels = params_channels(params);
	unsigned int regval;
	int bitwidth;
	int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;

	bitwidth = snd_pcm_format_width(format);
	if (bitwidth < 0) {
		dev_err(soc_runtime->dev, "%s() invalid bit width given: %d\n",
				__func__, bitwidth);
		return bitwidth;
	}

	regval = LPAIF_RDMACTL_BURSTEN_INCR4 |
			LPAIF_RDMACTL_AUDINTF(dma_port) |
			LPAIF_RDMACTL_FIFOWM_8;

	switch (bitwidth) {
	case 16:
		switch (channels) {
		case 1:
		case 2:
			regval |= LPAIF_RDMACTL_WPSCNT_ONE;
			break;
		case 4:
			regval |= LPAIF_RDMACTL_WPSCNT_TWO;
			break;
		case 6:
			regval |= LPAIF_RDMACTL_WPSCNT_THREE;
			break;
		case 8:
			regval |= LPAIF_RDMACTL_WPSCNT_FOUR;
			break;
		default:
			dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
					__func__, bitwidth, channels);
			return -EINVAL;
		}
		break;
	case 24:
	case 32:
		switch (channels) {
		case 1:
			regval |= LPAIF_RDMACTL_WPSCNT_ONE;
			break;
		case 2:
			regval |= LPAIF_RDMACTL_WPSCNT_TWO;
			break;
		case 4:
			regval |= LPAIF_RDMACTL_WPSCNT_FOUR;
			break;
		case 6:
			regval |= LPAIF_RDMACTL_WPSCNT_SIX;
			break;
		case 8:
			regval |= LPAIF_RDMACTL_WPSCNT_EIGHT;
			break;
		default:
			dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
					__func__, bitwidth, channels);
			return -EINVAL;
		}
		break;
	default:
		dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
				__func__, bitwidth, channels);
		return -EINVAL;
	}

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_RDMACTL_REG(v, pcm_data->rdma_ch), regval);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
				__func__, ret);
		return ret;
	}

	return 0;
}

static int lpass_platform_pcmops_hw_free(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_variant *v = drvdata->variant;
	int ret;

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_RDMACTL_REG(v, pcm_data->rdma_ch), 0);
	if (ret)
		dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
				__func__, ret);

	return ret;
}

static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_variant *v = drvdata->variant;
	int ret, ch = pcm_data->rdma_ch;

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_RDMABASE_REG(v, ch),
			runtime->dma_addr);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmabase reg: %d\n",
				__func__, ret);
		return ret;
	}

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_RDMABUFF_REG(v, ch),
			(snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmabuff reg: %d\n",
				__func__, ret);
		return ret;
	}

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_RDMAPER_REG(v, ch),
			(snd_pcm_lib_period_bytes(substream) >> 2) - 1);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmaper reg: %d\n",
				__func__, ret);
		return ret;
	}

	ret = regmap_update_bits(drvdata->lpaif_map,
			LPAIF_RDMACTL_REG(v, ch),
			LPAIF_RDMACTL_ENABLE_MASK, LPAIF_RDMACTL_ENABLE_ON);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
				__func__, ret);
		return ret;
	}

	return 0;
}

static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
		int cmd)
{
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_variant *v = drvdata->variant;
	int ret, ch = pcm_data->rdma_ch;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		/* clear status before enabling interrupts */
		ret = regmap_write(drvdata->lpaif_map,
				LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_ALL(ch));
		if (ret) {
			dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
					__func__, ret);
			return ret;
		}

		ret = regmap_update_bits(drvdata->lpaif_map,
				LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_ALL(ch),
				LPAIF_IRQ_ALL(ch));
		if (ret) {
			dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
					__func__, ret);
			return ret;
		}

		ret = regmap_update_bits(drvdata->lpaif_map,
				LPAIF_RDMACTL_REG(v, ch),
				LPAIF_RDMACTL_ENABLE_MASK,
				LPAIF_RDMACTL_ENABLE_ON);
		if (ret) {
			dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
					__func__, ret);
			return ret;
		}
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		ret = regmap_update_bits(drvdata->lpaif_map,
				LPAIF_RDMACTL_REG(v, ch),
				LPAIF_RDMACTL_ENABLE_MASK,
				LPAIF_RDMACTL_ENABLE_OFF);
		if (ret) {
			dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
					__func__, ret);
			return ret;
		}

		ret = regmap_update_bits(drvdata->lpaif_map,
				LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_ALL(ch), 0);
		if (ret) {
			dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
					__func__, ret);
			return ret;
		}
		break;
	}

	return 0;
}

static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
		struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
	struct lpass_data *drvdata =
			snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_variant *v = drvdata->variant;
	unsigned int base_addr, curr_addr;
	int ret, ch = pcm_data->rdma_ch;

	ret = regmap_read(drvdata->lpaif_map,
			LPAIF_RDMABASE_REG(v, ch), &base_addr);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error reading from rdmabase reg: %d\n",
				__func__, ret);
		return ret;
	}

	ret = regmap_read(drvdata->lpaif_map,
			LPAIF_RDMACURR_REG(v, ch), &curr_addr);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error reading from rdmacurr reg: %d\n",
				__func__, ret);
		return ret;
	}

	return bytes_to_frames(substream->runtime, curr_addr - base_addr);
}

static int lpass_platform_pcmops_mmap(struct snd_pcm_substream *substream,
		struct vm_area_struct *vma)
{
	struct snd_pcm_runtime *runtime = substream->runtime;

	return dma_mmap_coherent(substream->pcm->card->dev, vma,
			runtime->dma_area, runtime->dma_addr,
			runtime->dma_bytes);
}

static struct snd_pcm_ops lpass_platform_pcm_ops = {
	.open		= lpass_platform_pcmops_open,
	.ioctl		= snd_pcm_lib_ioctl,
	.hw_params	= lpass_platform_pcmops_hw_params,
	.hw_free	= lpass_platform_pcmops_hw_free,
	.prepare	= lpass_platform_pcmops_prepare,
	.trigger	= lpass_platform_pcmops_trigger,
	.pointer	= lpass_platform_pcmops_pointer,
	.mmap		= lpass_platform_pcmops_mmap,
};

static irqreturn_t lpass_dma_interrupt_handler(
			struct snd_pcm_substream *substream,
			struct lpass_data *drvdata,
			int chan, u32 interrupts)
{
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_variant *v = drvdata->variant;
	irqreturn_t ret = IRQ_NONE;
	int rv;

	if (interrupts & LPAIF_IRQ_PER(chan)) {
		rv = regmap_write(drvdata->lpaif_map,
				LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_PER(chan));
		if (rv) {
			dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
					__func__, rv);
			return IRQ_NONE;
		}
		snd_pcm_period_elapsed(substream);
		ret = IRQ_HANDLED;
	}

	if (interrupts & LPAIF_IRQ_XRUN(chan)) {
		rv = regmap_write(drvdata->lpaif_map,
				LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_XRUN(chan));
		if (rv) {
			dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
					__func__, rv);
			return IRQ_NONE;
		}
		dev_warn(soc_runtime->dev, "%s() xrun warning\n", __func__);
		snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
		ret = IRQ_HANDLED;
	}

	if (interrupts & LPAIF_IRQ_ERR(chan)) {
		rv = regmap_write(drvdata->lpaif_map,
				LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_ERR(chan));
		if (rv) {
			dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
					__func__, rv);
			return IRQ_NONE;
		}
		dev_err(soc_runtime->dev, "%s() bus access error\n", __func__);
		snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
		ret = IRQ_HANDLED;
	}

	return ret;
}

static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
{
	struct lpass_data *drvdata = data;
	struct lpass_variant *v = drvdata->variant;
	unsigned int irqs;
	int rv, chan;

	rv = regmap_read(drvdata->lpaif_map,
			LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
	if (rv) {
		pr_err("%s() error reading from irqstat reg: %d\n",
				__func__, rv);
		return IRQ_NONE;
	}

	/* Handle per channel interrupts */
	for (chan = 0; chan < LPASS_MAX_DMA_CHANNELS; chan++) {
		if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->substream[chan]) {
			rv = lpass_dma_interrupt_handler(
						drvdata->substream[chan],
						drvdata, chan, irqs);
			if (rv != IRQ_HANDLED)
				return rv;
		}
	}

	return IRQ_HANDLED;
}

static int lpass_platform_pcm_new(struct snd_soc_pcm_runtime *soc_runtime)
{
	struct snd_pcm *pcm = soc_runtime->pcm;
	struct snd_pcm_substream *substream =
		pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
	struct snd_soc_dai *cpu_dai = soc_runtime->cpu_dai;
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_variant *v = drvdata->variant;
	int ret;
	struct lpass_pcm_data *data;
	size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;

	data = devm_kzalloc(soc_runtime->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	if (v->alloc_dma_channel)
		data->rdma_ch = v->alloc_dma_channel(drvdata,
						SNDRV_PCM_STREAM_PLAYBACK);

	if (IS_ERR_VALUE(data->rdma_ch))
		return data->rdma_ch;

	drvdata->substream[data->rdma_ch] = substream;
	data->i2s_port = cpu_dai->driver->id;

	snd_soc_pcm_set_drvdata(soc_runtime, data);

	ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
				soc_runtime->platform->dev,
				size, &substream->dma_buffer);
	if (ret)
		return ret;

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_RDMACTL_REG(v, data->rdma_ch), 0);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
				__func__, ret);
		goto err_buf;
	}

	return 0;

err_buf:
	snd_dma_free_pages(&substream->dma_buffer);
	return ret;
}

static void lpass_platform_pcm_free(struct snd_pcm *pcm)
{
	struct snd_pcm_substream *substream =
		pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_pcm_data *data = snd_soc_pcm_get_drvdata(soc_runtime);
	struct lpass_variant *v = drvdata->variant;

	drvdata->substream[data->rdma_ch] = NULL;

	if (v->free_dma_channel)
		v->free_dma_channel(drvdata, data->rdma_ch);

	snd_dma_free_pages(&substream->dma_buffer);
}

static struct snd_soc_platform_driver lpass_platform_driver = {
	.pcm_new	= lpass_platform_pcm_new,
	.pcm_free	= lpass_platform_pcm_free,
	.ops		= &lpass_platform_pcm_ops,
};

int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
{
	struct lpass_data *drvdata = platform_get_drvdata(pdev);
	struct lpass_variant *v = drvdata->variant;
	int ret;

	drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
	if (drvdata->lpaif_irq < 0) {
		dev_err(&pdev->dev, "%s() error getting irq handle: %d\n",
				__func__, drvdata->lpaif_irq);
		return -ENODEV;
	}

	/* ensure audio hardware is disabled */
	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0);
	if (ret) {
		dev_err(&pdev->dev, "%s() error writing to irqen reg: %d\n",
				__func__, ret);
		return ret;
	}

	ret = devm_request_irq(&pdev->dev, drvdata->lpaif_irq,
			lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
			"lpass-irq-lpaif", drvdata);
	if (ret) {
		dev_err(&pdev->dev, "%s() irq request failed: %d\n",
				__func__, ret);
		return ret;
	}


	return devm_snd_soc_register_platform(&pdev->dev,
			&lpass_platform_driver);
}
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);

MODULE_DESCRIPTION("QTi LPASS Platform Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
c5c8635a KW	1	/*
	2	* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
	14	*/
	15
c5c8635a	16	#include <linux/dma-mapping.h>
c5c8635a KW	17	#include <linux/export.h>
	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
c5c8635a	20	#include <linux/platform_device.h>
c5c8635a KW	21	#include <sound/pcm_params.h>
	22	#include <linux/regmap.h>
	23	#include <sound/soc.h>
9bae4880	24	#include "lpass-lpaif-reg.h"
c5c8635a KW	25	#include "lpass.h"
c5c8635a KW	26
6db1c6ba SK	27	struct lpass_pcm_data {
	28	int rdma_ch;
	29	int i2s_port;
	30	};
	31
c5c8635a KW	32	#define LPASS_PLATFORM_BUFFER_SIZE (16 * 1024)
	33	#define LPASS_PLATFORM_PERIODS 2
	34
	35	static struct snd_pcm_hardware lpass_platform_pcm_hardware = {
	36	.info = SNDRV_PCM_INFO_MMAP \|
	37	SNDRV_PCM_INFO_MMAP_VALID \|
	38	SNDRV_PCM_INFO_INTERLEAVED \|
	39	SNDRV_PCM_INFO_PAUSE \|
	40	SNDRV_PCM_INFO_RESUME,
	41	.formats = SNDRV_PCM_FMTBIT_S16 \|
	42	SNDRV_PCM_FMTBIT_S24 \|
	43	SNDRV_PCM_FMTBIT_S32,
	44	.rates = SNDRV_PCM_RATE_8000_192000,
	45	.rate_min = 8000,
	46	.rate_max = 192000,
	47	.channels_min = 1,
	48	.channels_max = 8,
	49	.buffer_bytes_max = LPASS_PLATFORM_BUFFER_SIZE,
	50	.period_bytes_max = LPASS_PLATFORM_BUFFER_SIZE /
	51	LPASS_PLATFORM_PERIODS,
	52	.period_bytes_min = LPASS_PLATFORM_BUFFER_SIZE /
	53	LPASS_PLATFORM_PERIODS,
	54	.periods_min = LPASS_PLATFORM_PERIODS,
	55	.periods_max = LPASS_PLATFORM_PERIODS,
	56	.fifo_size = 0,
	57	};
	58
	59	static int lpass_platform_pcmops_open(struct snd_pcm_substream *substream)
	60	{
	61	struct snd_pcm_runtime *runtime = substream->runtime;
	62	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	63	int ret;
	64
	65	snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);
	66
	67	runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;
	68
	69	ret = snd_pcm_hw_constraint_integer(runtime,
	70	SNDRV_PCM_HW_PARAM_PERIODS);
	71	if (ret < 0) {
	72	dev_err(soc_runtime->dev, "%s() setting constraints failed: %d\n",
	73	__func__, ret);
	74	return -EINVAL;
	75	}
	76
	77	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
	78
	79	return 0;
	80	}
	81
	82	static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
	83	struct snd_pcm_hw_params *params)
	84	{
	85	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
6db1c6ba	86	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
c5c8635a KW	87	struct lpass_data *drvdata =
c5c8635a KW	88	snd_soc_platform_get_drvdata(soc_runtime->platform);
9bae4880	89	struct lpass_variant *v = drvdata->variant;
c5c8635a KW	90	snd_pcm_format_t format = params_format(params);
	91	unsigned int channels = params_channels(params);
	92	unsigned int regval;
	93	int bitwidth;
ec5b8287	94	int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;
c5c8635a KW	95
	96	bitwidth = snd_pcm_format_width(format);
	97	if (bitwidth < 0) {
	98	dev_err(soc_runtime->dev, "%s() invalid bit width given: %d\n",
	99	__func__, bitwidth);
	100	return bitwidth;
	101	}
	102
	103	regval = LPAIF_RDMACTL_BURSTEN_INCR4 \|
ec5b8287	104	LPAIF_RDMACTL_AUDINTF(dma_port) \|
c5c8635a KW	105	LPAIF_RDMACTL_FIFOWM_8;
	106
	107	switch (bitwidth) {
	108	case 16:
	109	switch (channels) {
	110	case 1:
	111	case 2:
	112	regval \|= LPAIF_RDMACTL_WPSCNT_ONE;
	113	break;
	114	case 4:
	115	regval \|= LPAIF_RDMACTL_WPSCNT_TWO;
	116	break;
	117	case 6:
	118	regval \|= LPAIF_RDMACTL_WPSCNT_THREE;
	119	break;
	120	case 8:
	121	regval \|= LPAIF_RDMACTL_WPSCNT_FOUR;
	122	break;
	123	default:
	124	dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
	125	__func__, bitwidth, channels);
	126	return -EINVAL;
	127	}
	128	break;
	129	case 24:
	130	case 32:
	131	switch (channels) {
	132	case 1:
	133	regval \|= LPAIF_RDMACTL_WPSCNT_ONE;
	134	break;
	135	case 2:
	136	regval \|= LPAIF_RDMACTL_WPSCNT_TWO;
	137	break;
	138	case 4:
	139	regval \|= LPAIF_RDMACTL_WPSCNT_FOUR;
	140	break;
	141	case 6:
	142	regval \|= LPAIF_RDMACTL_WPSCNT_SIX;
	143	break;
	144	case 8:
	145	regval \|= LPAIF_RDMACTL_WPSCNT_EIGHT;
	146	break;
	147	default:
	148	dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
	149	__func__, bitwidth, channels);
	150	return -EINVAL;
	151	}
	152	break;
	153	default:
	154	dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
	155	__func__, bitwidth, channels);
	156	return -EINVAL;
	157	}
	158
	159	ret = regmap_write(drvdata->lpaif_map,
6db1c6ba	160	LPAIF_RDMACTL_REG(v, pcm_data->rdma_ch), regval);
c5c8635a KW	161	if (ret) {
	162	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	163	__func__, ret);
	164	return ret;
	165	}
	166
	167	return 0;
	168	}
	169
	170	static int lpass_platform_pcmops_hw_free(struct snd_pcm_substream *substream)
	171	{
	172	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
6db1c6ba	173	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
c5c8635a KW	174	struct lpass_data *drvdata =
c5c8635a KW	175	snd_soc_platform_get_drvdata(soc_runtime->platform);
9bae4880	176	struct lpass_variant *v = drvdata->variant;
c5c8635a KW	177	int ret;
	178
	179	ret = regmap_write(drvdata->lpaif_map,
6db1c6ba	180	LPAIF_RDMACTL_REG(v, pcm_data->rdma_ch), 0);
c5c8635a KW	181	if (ret)
	182	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	183	__func__, ret);
	184
	185	return ret;
	186	}
	187
	188	static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
	189	{
	190	struct snd_pcm_runtime *runtime = substream->runtime;
	191	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
6db1c6ba	192	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
c5c8635a KW	193	struct lpass_data *drvdata =
c5c8635a KW	194	snd_soc_platform_get_drvdata(soc_runtime->platform);
9bae4880	195	struct lpass_variant *v = drvdata->variant;
6db1c6ba	196	int ret, ch = pcm_data->rdma_ch;
c5c8635a KW	197
c5c8635a KW	198	ret = regmap_write(drvdata->lpaif_map,
6db1c6ba	199	LPAIF_RDMABASE_REG(v, ch),
c5c8635a KW	200	runtime->dma_addr);
	201	if (ret) {
	202	dev_err(soc_runtime->dev, "%s() error writing to rdmabase reg: %d\n",
	203	__func__, ret);
	204	return ret;
	205	}
	206
	207	ret = regmap_write(drvdata->lpaif_map,
6db1c6ba	208	LPAIF_RDMABUFF_REG(v, ch),
c5c8635a KW	209	(snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
	210	if (ret) {
	211	dev_err(soc_runtime->dev, "%s() error writing to rdmabuff reg: %d\n",
	212	__func__, ret);
	213	return ret;
	214	}
	215
	216	ret = regmap_write(drvdata->lpaif_map,
6db1c6ba	217	LPAIF_RDMAPER_REG(v, ch),
c5c8635a KW	218	(snd_pcm_lib_period_bytes(substream) >> 2) - 1);
	219	if (ret) {
	220	dev_err(soc_runtime->dev, "%s() error writing to rdmaper reg: %d\n",
	221	__func__, ret);
	222	return ret;
	223	}
	224
	225	ret = regmap_update_bits(drvdata->lpaif_map,
6db1c6ba	226	LPAIF_RDMACTL_REG(v, ch),
c5c8635a KW	227	LPAIF_RDMACTL_ENABLE_MASK, LPAIF_RDMACTL_ENABLE_ON);
	228	if (ret) {
	229	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	230	__func__, ret);
	231	return ret;
	232	}
	233
	234	return 0;
	235	}
	236
	237	static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
	238	int cmd)
	239	{
	240	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
6db1c6ba	241	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
c5c8635a KW	242	struct lpass_data *drvdata =
c5c8635a KW	243	snd_soc_platform_get_drvdata(soc_runtime->platform);
9bae4880	244	struct lpass_variant *v = drvdata->variant;
6db1c6ba	245	int ret, ch = pcm_data->rdma_ch;
c5c8635a KW	246
	247	switch (cmd) {
	248	case SNDRV_PCM_TRIGGER_START:
	249	case SNDRV_PCM_TRIGGER_RESUME:
	250	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	251	/* clear status before enabling interrupts */
	252	ret = regmap_write(drvdata->lpaif_map,
9bae4880	253	LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba	254	LPAIF_IRQ_ALL(ch));
c5c8635a KW	255	if (ret) {
	256	dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
	257	__func__, ret);
	258	return ret;
	259	}
	260
	261	ret = regmap_update_bits(drvdata->lpaif_map,
9bae4880	262	LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba SK	263	LPAIF_IRQ_ALL(ch),
6db1c6ba SK	264	LPAIF_IRQ_ALL(ch));
c5c8635a KW	265	if (ret) {
	266	dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
	267	__func__, ret);
	268	return ret;
	269	}
	270
	271	ret = regmap_update_bits(drvdata->lpaif_map,
6db1c6ba	272	LPAIF_RDMACTL_REG(v, ch),
c5c8635a KW	273	LPAIF_RDMACTL_ENABLE_MASK,
	274	LPAIF_RDMACTL_ENABLE_ON);
	275	if (ret) {
	276	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	277	__func__, ret);
	278	return ret;
	279	}
	280	break;
	281	case SNDRV_PCM_TRIGGER_STOP:
	282	case SNDRV_PCM_TRIGGER_SUSPEND:
	283	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	284	ret = regmap_update_bits(drvdata->lpaif_map,
6db1c6ba	285	LPAIF_RDMACTL_REG(v, ch),
c5c8635a KW	286	LPAIF_RDMACTL_ENABLE_MASK,
	287	LPAIF_RDMACTL_ENABLE_OFF);
	288	if (ret) {
	289	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	290	__func__, ret);
	291	return ret;
	292	}
	293
	294	ret = regmap_update_bits(drvdata->lpaif_map,
9bae4880	295	LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba	296	LPAIF_IRQ_ALL(ch), 0);
c5c8635a KW	297	if (ret) {
	298	dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
	299	__func__, ret);
	300	return ret;
	301	}
	302	break;
	303	}
	304
	305	return 0;
	306	}
	307
	308	static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
	309	struct snd_pcm_substream *substream)
	310	{
	311	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
6db1c6ba	312	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
c5c8635a KW	313	struct lpass_data *drvdata =
c5c8635a KW	314	snd_soc_platform_get_drvdata(soc_runtime->platform);
9bae4880	315	struct lpass_variant *v = drvdata->variant;
c5c8635a	316	unsigned int base_addr, curr_addr;
6db1c6ba	317	int ret, ch = pcm_data->rdma_ch;
c5c8635a KW	318
c5c8635a KW	319	ret = regmap_read(drvdata->lpaif_map,
6db1c6ba	320	LPAIF_RDMABASE_REG(v, ch), &base_addr);
c5c8635a KW	321	if (ret) {
	322	dev_err(soc_runtime->dev, "%s() error reading from rdmabase reg: %d\n",
	323	__func__, ret);
	324	return ret;
	325	}
	326
	327	ret = regmap_read(drvdata->lpaif_map,
6db1c6ba	328	LPAIF_RDMACURR_REG(v, ch), &curr_addr);
c5c8635a KW	329	if (ret) {
	330	dev_err(soc_runtime->dev, "%s() error reading from rdmacurr reg: %d\n",
	331	__func__, ret);
	332	return ret;
	333	}
	334
	335	return bytes_to_frames(substream->runtime, curr_addr - base_addr);
	336	}
	337
	338	static int lpass_platform_pcmops_mmap(struct snd_pcm_substream *substream,
	339	struct vm_area_struct *vma)
	340	{
	341	struct snd_pcm_runtime *runtime = substream->runtime;
	342
	343	return dma_mmap_coherent(substream->pcm->card->dev, vma,
	344	runtime->dma_area, runtime->dma_addr,
	345	runtime->dma_bytes);
	346	}
	347
	348	static struct snd_pcm_ops lpass_platform_pcm_ops = {
	349	.open = lpass_platform_pcmops_open,
	350	.ioctl = snd_pcm_lib_ioctl,
	351	.hw_params = lpass_platform_pcmops_hw_params,
	352	.hw_free = lpass_platform_pcmops_hw_free,
	353	.prepare = lpass_platform_pcmops_prepare,
	354	.trigger = lpass_platform_pcmops_trigger,
	355	.pointer = lpass_platform_pcmops_pointer,
	356	.mmap = lpass_platform_pcmops_mmap,
	357	};
	358
4f629e4b SK	359	static irqreturn_t lpass_dma_interrupt_handler(
	360	struct snd_pcm_substream *substream,
	361	struct lpass_data *drvdata,
	362	int chan, u32 interrupts)
c5c8635a	363	{
c5c8635a	364	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
9bae4880	365	struct lpass_variant *v = drvdata->variant;
c5c8635a	366	irqreturn_t ret = IRQ_NONE;
4f629e4b	367	int rv;
6db1c6ba SK	368
6db1c6ba SK	369	if (interrupts & LPAIF_IRQ_PER(chan)) {
c5c8635a	370	rv = regmap_write(drvdata->lpaif_map,
9bae4880	371	LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba	372	LPAIF_IRQ_PER(chan));
c5c8635a KW	373	if (rv) {
	374	dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
	375	__func__, rv);
	376	return IRQ_NONE;
	377	}
	378	snd_pcm_period_elapsed(substream);
	379	ret = IRQ_HANDLED;
	380	}
	381
6db1c6ba	382	if (interrupts & LPAIF_IRQ_XRUN(chan)) {
c5c8635a	383	rv = regmap_write(drvdata->lpaif_map,
9bae4880	384	LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba	385	LPAIF_IRQ_XRUN(chan));
c5c8635a KW	386	if (rv) {
	387	dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
	388	__func__, rv);
	389	return IRQ_NONE;
	390	}
	391	dev_warn(soc_runtime->dev, "%s() xrun warning\n", __func__);
	392	snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
	393	ret = IRQ_HANDLED;
	394	}
	395
6db1c6ba	396	if (interrupts & LPAIF_IRQ_ERR(chan)) {
c5c8635a	397	rv = regmap_write(drvdata->lpaif_map,
9bae4880	398	LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba	399	LPAIF_IRQ_ERR(chan));
c5c8635a KW	400	if (rv) {
	401	dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
	402	__func__, rv);
	403	return IRQ_NONE;
	404	}
	405	dev_err(soc_runtime->dev, "%s() bus access error\n", __func__);
	406	snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
	407	ret = IRQ_HANDLED;
	408	}
	409
	410	return ret;
	411	}
	412
4f629e4b SK	413	static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
	414	{
	415	struct lpass_data *drvdata = data;
	416	struct lpass_variant *v = drvdata->variant;
	417	unsigned int irqs;
	418	int rv, chan;
	419
	420	rv = regmap_read(drvdata->lpaif_map,
	421	LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
	422	if (rv) {
	423	pr_err("%s() error reading from irqstat reg: %d\n",
	424	__func__, rv);
	425	return IRQ_NONE;
	426	}
	427
	428	/* Handle per channel interrupts */
	429	for (chan = 0; chan < LPASS_MAX_DMA_CHANNELS; chan++) {
	430	if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->substream[chan]) {
	431	rv = lpass_dma_interrupt_handler(
	432	drvdata->substream[chan],
	433	drvdata, chan, irqs);
	434	if (rv != IRQ_HANDLED)
	435	return rv;
	436	}
	437	}
	438
	439	return IRQ_HANDLED;
	440	}
	441
c5c8635a KW	442	static int lpass_platform_pcm_new(struct snd_soc_pcm_runtime *soc_runtime)
	443	{
	444	struct snd_pcm *pcm = soc_runtime->pcm;
	445	struct snd_pcm_substream *substream =
	446	pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
6db1c6ba	447	struct snd_soc_dai *cpu_dai = soc_runtime->cpu_dai;
c5c8635a KW	448	struct lpass_data *drvdata =
c5c8635a KW	449	snd_soc_platform_get_drvdata(soc_runtime->platform);
9bae4880	450	struct lpass_variant *v = drvdata->variant;
c5c8635a	451	int ret;
6db1c6ba	452	struct lpass_pcm_data *data;
144a9883	453	size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;
6db1c6ba SK	454
	455	data = devm_kzalloc(soc_runtime->dev, sizeof(*data), GFP_KERNEL);
	456	if (!data)
	457	return -ENOMEM;
	458
	459	if (v->alloc_dma_channel)
73c847b6 SK	460	data->rdma_ch = v->alloc_dma_channel(drvdata,
73c847b6 SK	461	SNDRV_PCM_STREAM_PLAYBACK);
6db1c6ba SK	462
	463	if (IS_ERR_VALUE(data->rdma_ch))
	464	return data->rdma_ch;
	465
4f629e4b	466	drvdata->substream[data->rdma_ch] = substream;
6db1c6ba SK	467	data->i2s_port = cpu_dai->driver->id;
	468
	469	snd_soc_pcm_set_drvdata(soc_runtime, data);
c5c8635a	470
144a9883 SK	471	ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
	472	soc_runtime->platform->dev,
	473	size, &substream->dma_buffer);
c5c8635a KW	474	if (ret)
	475	return ret;
	476
c5c8635a	477	ret = regmap_write(drvdata->lpaif_map,
6db1c6ba	478	LPAIF_RDMACTL_REG(v, data->rdma_ch), 0);
c5c8635a KW	479	if (ret) {
	480	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	481	__func__, ret);
4f629e4b	482	goto err_buf;
c5c8635a KW	483	}
	484
	485	return 0;
	486
	487	err_buf:
144a9883	488	snd_dma_free_pages(&substream->dma_buffer);
c5c8635a KW	489	return ret;
	490	}
	491
	492	static void lpass_platform_pcm_free(struct snd_pcm *pcm)
	493	{
	494	struct snd_pcm_substream *substream =
	495	pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
	496	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
6db1c6ba SK	497	struct lpass_data *drvdata =
	498	snd_soc_platform_get_drvdata(soc_runtime->platform);
	499	struct lpass_pcm_data *data = snd_soc_pcm_get_drvdata(soc_runtime);
	500	struct lpass_variant *v = drvdata->variant;
	501
4f629e4b SK	502	drvdata->substream[data->rdma_ch] = NULL;
4f629e4b SK	503
6db1c6ba SK	504	if (v->free_dma_channel)
6db1c6ba SK	505	v->free_dma_channel(drvdata, data->rdma_ch);
c5c8635a	506
144a9883	507	snd_dma_free_pages(&substream->dma_buffer);
c5c8635a KW	508	}
	509
	510	static struct snd_soc_platform_driver lpass_platform_driver = {
	511	.pcm_new = lpass_platform_pcm_new,
	512	.pcm_free = lpass_platform_pcm_free,
	513	.ops = &lpass_platform_pcm_ops,
	514	};
	515
	516	int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
	517	{
	518	struct lpass_data *drvdata = platform_get_drvdata(pdev);
4f629e4b SK	519	struct lpass_variant *v = drvdata->variant;
4f629e4b SK	520	int ret;
c5c8635a KW	521
	522	drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
	523	if (drvdata->lpaif_irq < 0) {
	524	dev_err(&pdev->dev, "%s() error getting irq handle: %d\n",
	525	__func__, drvdata->lpaif_irq);
	526	return -ENODEV;
	527	}
	528
4f629e4b SK	529	/* ensure audio hardware is disabled */
	530	ret = regmap_write(drvdata->lpaif_map,
	531	LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0);
	532	if (ret) {
	533	dev_err(&pdev->dev, "%s() error writing to irqen reg: %d\n",
	534	__func__, ret);
	535	return ret;
	536	}
	537
	538	ret = devm_request_irq(&pdev->dev, drvdata->lpaif_irq,
	539	lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
	540	"lpass-irq-lpaif", drvdata);
	541	if (ret) {
	542	dev_err(&pdev->dev, "%s() irq request failed: %d\n",
	543	__func__, ret);
	544	return ret;
	545	}
	546
	547
c5c8635a KW	548	return devm_snd_soc_register_platform(&pdev->dev,
	549	&lpass_platform_driver);
	550	}
	551	EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);
	552
	553	MODULE_DESCRIPTION("QTi LPASS Platform Driver");
	554	MODULE_LICENSE("GPL v2");