[deliverable/linux.git] / sound / soc / qcom / lpass-platform.c

/*
 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
 */

#include <linux/dma-mapping.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/pcm_params.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"

struct lpass_pcm_data {
	int rdma_ch;
	int i2s_port;
};

#define LPASS_PLATFORM_BUFFER_SIZE	(16 * 1024)
#define LPASS_PLATFORM_PERIODS		2

static struct snd_pcm_hardware lpass_platform_pcm_hardware = {
	.info			=	SNDRV_PCM_INFO_MMAP |
					SNDRV_PCM_INFO_MMAP_VALID |
					SNDRV_PCM_INFO_INTERLEAVED |
					SNDRV_PCM_INFO_PAUSE |
					SNDRV_PCM_INFO_RESUME,
	.formats		=	SNDRV_PCM_FMTBIT_S16 |
					SNDRV_PCM_FMTBIT_S24 |
					SNDRV_PCM_FMTBIT_S32,
	.rates			=	SNDRV_PCM_RATE_8000_192000,
	.rate_min		=	8000,
	.rate_max		=	192000,
	.channels_min		=	1,
	.channels_max		=	8,
	.buffer_bytes_max	=	LPASS_PLATFORM_BUFFER_SIZE,
	.period_bytes_max	=	LPASS_PLATFORM_BUFFER_SIZE /
						LPASS_PLATFORM_PERIODS,
	.period_bytes_min	=	LPASS_PLATFORM_BUFFER_SIZE /
						LPASS_PLATFORM_PERIODS,
	.periods_min		=	LPASS_PLATFORM_PERIODS,
	.periods_max		=	LPASS_PLATFORM_PERIODS,
	.fifo_size		=	0,
};

static int lpass_platform_pcmops_open(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	int ret;

	snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);

	runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;

	ret = snd_pcm_hw_constraint_integer(runtime,
			SNDRV_PCM_HW_PARAM_PERIODS);
	if (ret < 0) {
		dev_err(soc_runtime->dev, "%s() setting constraints failed: %d\n",
				__func__, ret);
		return -EINVAL;
	}

	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);

	return 0;
}

static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
		struct snd_pcm_hw_params *params)
{
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_variant *v = drvdata->variant;
	snd_pcm_format_t format = params_format(params);
	unsigned int channels = params_channels(params);
	unsigned int regval;
	int dir = substream->stream;
	int bitwidth;
	int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;

	bitwidth = snd_pcm_format_width(format);
	if (bitwidth < 0) {
		dev_err(soc_runtime->dev, "%s() invalid bit width given: %d\n",
				__func__, bitwidth);
		return bitwidth;
	}

	regval = LPAIF_DMACTL_BURSTEN_INCR4 |
			LPAIF_DMACTL_AUDINTF(dma_port) |
			LPAIF_DMACTL_FIFOWM_8;

	switch (bitwidth) {
	case 16:
		switch (channels) {
		case 1:
		case 2:
			regval |= LPAIF_DMACTL_WPSCNT_ONE;
			break;
		case 4:
			regval |= LPAIF_DMACTL_WPSCNT_TWO;
			break;
		case 6:
			regval |= LPAIF_DMACTL_WPSCNT_THREE;
			break;
		case 8:
			regval |= LPAIF_DMACTL_WPSCNT_FOUR;
			break;
		default:
			dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
					__func__, bitwidth, channels);
			return -EINVAL;
		}
		break;
	case 24:
	case 32:
		switch (channels) {
		case 1:
			regval |= LPAIF_DMACTL_WPSCNT_ONE;
			break;
		case 2:
			regval |= LPAIF_DMACTL_WPSCNT_TWO;
			break;
		case 4:
			regval |= LPAIF_DMACTL_WPSCNT_FOUR;
			break;
		case 6:
			regval |= LPAIF_DMACTL_WPSCNT_SIX;
			break;
		case 8:
			regval |= LPAIF_DMACTL_WPSCNT_EIGHT;
			break;
		default:
			dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
					__func__, bitwidth, channels);
			return -EINVAL;
		}
		break;
	default:
		dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
				__func__, bitwidth, channels);
		return -EINVAL;
	}

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_DMACTL_REG(v, pcm_data->rdma_ch, dir), regval);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
				__func__, ret);
		return ret;
	}

	return 0;
}

static int lpass_platform_pcmops_hw_free(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_variant *v = drvdata->variant;
	int ret;

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_RDMACTL_REG(v, pcm_data->rdma_ch), 0);
	if (ret)
		dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
				__func__, ret);

	return ret;
}

static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_variant *v = drvdata->variant;
	int ret, ch = pcm_data->rdma_ch;
	int dir = substream->stream;

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_RDMABASE_REG(v, ch),
			runtime->dma_addr);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmabase reg: %d\n",
				__func__, ret);
		return ret;
	}

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_DMABUFF_REG(v, ch, dir),
			(snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmabuff reg: %d\n",
				__func__, ret);
		return ret;
	}

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_DMAPER_REG(v, ch, dir),
			(snd_pcm_lib_period_bytes(substream) >> 2) - 1);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmaper reg: %d\n",
				__func__, ret);
		return ret;
	}

	ret = regmap_update_bits(drvdata->lpaif_map,
			LPAIF_DMACTL_REG(v, ch, dir),
			LPAIF_DMACTL_ENABLE_MASK, LPAIF_DMACTL_ENABLE_ON);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
				__func__, ret);
		return ret;
	}

	return 0;
}

static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
		int cmd)
{
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_variant *v = drvdata->variant;
	int ret, ch = pcm_data->rdma_ch;
	int dir = substream->stream;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		/* clear status before enabling interrupts */
		ret = regmap_write(drvdata->lpaif_map,
				LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_ALL(ch));
		if (ret) {
			dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
					__func__, ret);
			return ret;
		}

		ret = regmap_update_bits(drvdata->lpaif_map,
				LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_ALL(ch),
				LPAIF_IRQ_ALL(ch));
		if (ret) {
			dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
					__func__, ret);
			return ret;
		}

		ret = regmap_update_bits(drvdata->lpaif_map,
				LPAIF_DMACTL_REG(v, ch, dir),
				LPAIF_DMACTL_ENABLE_MASK,
				LPAIF_DMACTL_ENABLE_ON);
		if (ret) {
			dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
					__func__, ret);
			return ret;
		}
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		ret = regmap_update_bits(drvdata->lpaif_map,
				LPAIF_DMACTL_REG(v, ch, dir),
				LPAIF_DMACTL_ENABLE_MASK,
				LPAIF_DMACTL_ENABLE_OFF);
		if (ret) {
			dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
					__func__, ret);
			return ret;
		}

		ret = regmap_update_bits(drvdata->lpaif_map,
				LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_ALL(ch), 0);
		if (ret) {
			dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
					__func__, ret);
			return ret;
		}
		break;
	}

	return 0;
}

static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
		struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
	struct lpass_data *drvdata =
			snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_variant *v = drvdata->variant;
	unsigned int base_addr, curr_addr;
	int ret, ch = pcm_data->rdma_ch;
	int dir = substream->stream;

	ret = regmap_read(drvdata->lpaif_map,
			LPAIF_DMABASE_REG(v, ch, dir), &base_addr);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error reading from rdmabase reg: %d\n",
				__func__, ret);
		return ret;
	}

	ret = regmap_read(drvdata->lpaif_map,
			LPAIF_DMACURR_REG(v, ch, dir), &curr_addr);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error reading from rdmacurr reg: %d\n",
				__func__, ret);
		return ret;
	}

	return bytes_to_frames(substream->runtime, curr_addr - base_addr);
}

static int lpass_platform_pcmops_mmap(struct snd_pcm_substream *substream,
		struct vm_area_struct *vma)
{
	struct snd_pcm_runtime *runtime = substream->runtime;

	return dma_mmap_coherent(substream->pcm->card->dev, vma,
			runtime->dma_area, runtime->dma_addr,
			runtime->dma_bytes);
}

static struct snd_pcm_ops lpass_platform_pcm_ops = {
	.open		= lpass_platform_pcmops_open,
	.ioctl		= snd_pcm_lib_ioctl,
	.hw_params	= lpass_platform_pcmops_hw_params,
	.hw_free	= lpass_platform_pcmops_hw_free,
	.prepare	= lpass_platform_pcmops_prepare,
	.trigger	= lpass_platform_pcmops_trigger,
	.pointer	= lpass_platform_pcmops_pointer,
	.mmap		= lpass_platform_pcmops_mmap,
};

static irqreturn_t lpass_dma_interrupt_handler(
			struct snd_pcm_substream *substream,
			struct lpass_data *drvdata,
			int chan, u32 interrupts)
{
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_variant *v = drvdata->variant;
	irqreturn_t ret = IRQ_NONE;
	int rv;

	if (interrupts & LPAIF_IRQ_PER(chan)) {
		rv = regmap_write(drvdata->lpaif_map,
				LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_PER(chan));
		if (rv) {
			dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
					__func__, rv);
			return IRQ_NONE;
		}
		snd_pcm_period_elapsed(substream);
		ret = IRQ_HANDLED;
	}

	if (interrupts & LPAIF_IRQ_XRUN(chan)) {
		rv = regmap_write(drvdata->lpaif_map,
				LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_XRUN(chan));
		if (rv) {
			dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
					__func__, rv);
			return IRQ_NONE;
		}
		dev_warn(soc_runtime->dev, "%s() xrun warning\n", __func__);
		snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
		ret = IRQ_HANDLED;
	}

	if (interrupts & LPAIF_IRQ_ERR(chan)) {
		rv = regmap_write(drvdata->lpaif_map,
				LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_ERR(chan));
		if (rv) {
			dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
					__func__, rv);
			return IRQ_NONE;
		}
		dev_err(soc_runtime->dev, "%s() bus access error\n", __func__);
		snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
		ret = IRQ_HANDLED;
	}

	return ret;
}

static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
{
	struct lpass_data *drvdata = data;
	struct lpass_variant *v = drvdata->variant;
	unsigned int irqs;
	int rv, chan;

	rv = regmap_read(drvdata->lpaif_map,
			LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
	if (rv) {
		pr_err("%s() error reading from irqstat reg: %d\n",
				__func__, rv);
		return IRQ_NONE;
	}

	/* Handle per channel interrupts */
	for (chan = 0; chan < LPASS_MAX_DMA_CHANNELS; chan++) {
		if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->substream[chan]) {
			rv = lpass_dma_interrupt_handler(
						drvdata->substream[chan],
						drvdata, chan, irqs);
			if (rv != IRQ_HANDLED)
				return rv;
		}
	}

	return IRQ_HANDLED;
}

static int lpass_platform_pcm_new(struct snd_soc_pcm_runtime *soc_runtime)
{
	struct snd_pcm *pcm = soc_runtime->pcm;
	struct snd_pcm_substream *substream =
		pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
	struct snd_soc_dai *cpu_dai = soc_runtime->cpu_dai;
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_variant *v = drvdata->variant;
	int ret;
	struct lpass_pcm_data *data;
	size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;

	data = devm_kzalloc(soc_runtime->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	if (v->alloc_dma_channel)
		data->rdma_ch = v->alloc_dma_channel(drvdata,
						SNDRV_PCM_STREAM_PLAYBACK);

	if (IS_ERR_VALUE(data->rdma_ch))
		return data->rdma_ch;

	drvdata->substream[data->rdma_ch] = substream;
	data->i2s_port = cpu_dai->driver->id;

	snd_soc_pcm_set_drvdata(soc_runtime, data);

	ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
				soc_runtime->platform->dev,
				size, &substream->dma_buffer);
	if (ret)
		return ret;

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_RDMACTL_REG(v, data->rdma_ch), 0);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
				__func__, ret);
		goto err_buf;
	}

	return 0;

err_buf:
	snd_dma_free_pages(&substream->dma_buffer);
	return ret;
}

static void lpass_platform_pcm_free(struct snd_pcm *pcm)
{
	struct snd_pcm_substream *substream =
		pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_pcm_data *data = snd_soc_pcm_get_drvdata(soc_runtime);
	struct lpass_variant *v = drvdata->variant;

	drvdata->substream[data->rdma_ch] = NULL;

	if (v->free_dma_channel)
		v->free_dma_channel(drvdata, data->rdma_ch);

	snd_dma_free_pages(&substream->dma_buffer);
}

static struct snd_soc_platform_driver lpass_platform_driver = {
	.pcm_new	= lpass_platform_pcm_new,
	.pcm_free	= lpass_platform_pcm_free,
	.ops		= &lpass_platform_pcm_ops,
};

int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
{
	struct lpass_data *drvdata = platform_get_drvdata(pdev);
	struct lpass_variant *v = drvdata->variant;
	int ret;

	drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
	if (drvdata->lpaif_irq < 0) {
		dev_err(&pdev->dev, "%s() error getting irq handle: %d\n",
				__func__, drvdata->lpaif_irq);
		return -ENODEV;
	}

	/* ensure audio hardware is disabled */
	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0);
	if (ret) {
		dev_err(&pdev->dev, "%s() error writing to irqen reg: %d\n",
				__func__, ret);
		return ret;
	}

	ret = devm_request_irq(&pdev->dev, drvdata->lpaif_irq,
			lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
			"lpass-irq-lpaif", drvdata);
	if (ret) {
		dev_err(&pdev->dev, "%s() irq request failed: %d\n",
				__func__, ret);
		return ret;
	}


	return devm_snd_soc_register_platform(&pdev->dev,
			&lpass_platform_driver);
}
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);

MODULE_DESCRIPTION("QTi LPASS Platform Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
c5c8635a KW	1	/*
	2	* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
	14	*/
	15
c5c8635a	16	#include <linux/dma-mapping.h>
c5c8635a KW	17	#include <linux/export.h>
	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
c5c8635a	20	#include <linux/platform_device.h>
c5c8635a KW	21	#include <sound/pcm_params.h>
	22	#include <linux/regmap.h>
	23	#include <sound/soc.h>
9bae4880	24	#include "lpass-lpaif-reg.h"
c5c8635a KW	25	#include "lpass.h"
c5c8635a KW	26
6db1c6ba SK	27	struct lpass_pcm_data {
	28	int rdma_ch;
	29	int i2s_port;
	30	};
	31
c5c8635a KW	32	#define LPASS_PLATFORM_BUFFER_SIZE (16 * 1024)
	33	#define LPASS_PLATFORM_PERIODS 2
	34
	35	static struct snd_pcm_hardware lpass_platform_pcm_hardware = {
	36	.info = SNDRV_PCM_INFO_MMAP \|
	37	SNDRV_PCM_INFO_MMAP_VALID \|
	38	SNDRV_PCM_INFO_INTERLEAVED \|
	39	SNDRV_PCM_INFO_PAUSE \|
	40	SNDRV_PCM_INFO_RESUME,
	41	.formats = SNDRV_PCM_FMTBIT_S16 \|
	42	SNDRV_PCM_FMTBIT_S24 \|
	43	SNDRV_PCM_FMTBIT_S32,
	44	.rates = SNDRV_PCM_RATE_8000_192000,
	45	.rate_min = 8000,
	46	.rate_max = 192000,
	47	.channels_min = 1,
	48	.channels_max = 8,
	49	.buffer_bytes_max = LPASS_PLATFORM_BUFFER_SIZE,
	50	.period_bytes_max = LPASS_PLATFORM_BUFFER_SIZE /
	51	LPASS_PLATFORM_PERIODS,
	52	.period_bytes_min = LPASS_PLATFORM_BUFFER_SIZE /
	53	LPASS_PLATFORM_PERIODS,
	54	.periods_min = LPASS_PLATFORM_PERIODS,
	55	.periods_max = LPASS_PLATFORM_PERIODS,
	56	.fifo_size = 0,
	57	};
	58
	59	static int lpass_platform_pcmops_open(struct snd_pcm_substream *substream)
	60	{
	61	struct snd_pcm_runtime *runtime = substream->runtime;
	62	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	63	int ret;
	64
	65	snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);
	66
	67	runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;
	68
	69	ret = snd_pcm_hw_constraint_integer(runtime,
	70	SNDRV_PCM_HW_PARAM_PERIODS);
	71	if (ret < 0) {
	72	dev_err(soc_runtime->dev, "%s() setting constraints failed: %d\n",
	73	__func__, ret);
	74	return -EINVAL;
	75	}
	76
	77	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
	78
	79	return 0;
	80	}
	81
	82	static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
	83	struct snd_pcm_hw_params *params)
	84	{
	85	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
6db1c6ba	86	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
c5c8635a KW	87	struct lpass_data *drvdata =
c5c8635a KW	88	snd_soc_platform_get_drvdata(soc_runtime->platform);
9bae4880	89	struct lpass_variant *v = drvdata->variant;
c5c8635a KW	90	snd_pcm_format_t format = params_format(params);
	91	unsigned int channels = params_channels(params);
	92	unsigned int regval;
ec9e0ec8	93	int dir = substream->stream;
c5c8635a	94	int bitwidth;
ec5b8287	95	int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;
c5c8635a KW	96
	97	bitwidth = snd_pcm_format_width(format);
	98	if (bitwidth < 0) {
	99	dev_err(soc_runtime->dev, "%s() invalid bit width given: %d\n",
	100	__func__, bitwidth);
	101	return bitwidth;
	102	}
	103
ec9e0ec8 SK	104	regval = LPAIF_DMACTL_BURSTEN_INCR4 \|
	105	LPAIF_DMACTL_AUDINTF(dma_port) \|
	106	LPAIF_DMACTL_FIFOWM_8;
c5c8635a KW	107
	108	switch (bitwidth) {
	109	case 16:
	110	switch (channels) {
	111	case 1:
	112	case 2:
ec9e0ec8	113	regval \|= LPAIF_DMACTL_WPSCNT_ONE;
c5c8635a KW	114	break;
c5c8635a KW	115	case 4:
ec9e0ec8	116	regval \|= LPAIF_DMACTL_WPSCNT_TWO;
c5c8635a KW	117	break;
c5c8635a KW	118	case 6:
ec9e0ec8	119	regval \|= LPAIF_DMACTL_WPSCNT_THREE;
c5c8635a KW	120	break;
c5c8635a KW	121	case 8:
ec9e0ec8	122	regval \|= LPAIF_DMACTL_WPSCNT_FOUR;
c5c8635a KW	123	break;
	124	default:
	125	dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
	126	__func__, bitwidth, channels);
	127	return -EINVAL;
	128	}
	129	break;
	130	case 24:
	131	case 32:
	132	switch (channels) {
	133	case 1:
ec9e0ec8	134	regval \|= LPAIF_DMACTL_WPSCNT_ONE;
c5c8635a KW	135	break;
c5c8635a KW	136	case 2:
ec9e0ec8	137	regval \|= LPAIF_DMACTL_WPSCNT_TWO;
c5c8635a KW	138	break;
c5c8635a KW	139	case 4:
ec9e0ec8	140	regval \|= LPAIF_DMACTL_WPSCNT_FOUR;
c5c8635a KW	141	break;
c5c8635a KW	142	case 6:
ec9e0ec8	143	regval \|= LPAIF_DMACTL_WPSCNT_SIX;
c5c8635a KW	144	break;
c5c8635a KW	145	case 8:
ec9e0ec8	146	regval \|= LPAIF_DMACTL_WPSCNT_EIGHT;
c5c8635a KW	147	break;
	148	default:
	149	dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
	150	__func__, bitwidth, channels);
	151	return -EINVAL;
	152	}
	153	break;
	154	default:
	155	dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
	156	__func__, bitwidth, channels);
	157	return -EINVAL;
	158	}
	159
	160	ret = regmap_write(drvdata->lpaif_map,
ec9e0ec8	161	LPAIF_DMACTL_REG(v, pcm_data->rdma_ch, dir), regval);
c5c8635a KW	162	if (ret) {
	163	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	164	__func__, ret);
	165	return ret;
	166	}
	167
	168	return 0;
	169	}
	170
	171	static int lpass_platform_pcmops_hw_free(struct snd_pcm_substream *substream)
	172	{
	173	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
6db1c6ba	174	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
c5c8635a KW	175	struct lpass_data *drvdata =
c5c8635a KW	176	snd_soc_platform_get_drvdata(soc_runtime->platform);
9bae4880	177	struct lpass_variant *v = drvdata->variant;
c5c8635a KW	178	int ret;
	179
	180	ret = regmap_write(drvdata->lpaif_map,
6db1c6ba	181	LPAIF_RDMACTL_REG(v, pcm_data->rdma_ch), 0);
c5c8635a KW	182	if (ret)
	183	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	184	__func__, ret);
	185
	186	return ret;
	187	}
	188
	189	static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
	190	{
	191	struct snd_pcm_runtime *runtime = substream->runtime;
	192	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
6db1c6ba	193	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
c5c8635a KW	194	struct lpass_data *drvdata =
c5c8635a KW	195	snd_soc_platform_get_drvdata(soc_runtime->platform);
9bae4880	196	struct lpass_variant *v = drvdata->variant;
6db1c6ba	197	int ret, ch = pcm_data->rdma_ch;
ec9e0ec8	198	int dir = substream->stream;
c5c8635a KW	199
c5c8635a KW	200	ret = regmap_write(drvdata->lpaif_map,
6db1c6ba	201	LPAIF_RDMABASE_REG(v, ch),
c5c8635a KW	202	runtime->dma_addr);
	203	if (ret) {
	204	dev_err(soc_runtime->dev, "%s() error writing to rdmabase reg: %d\n",
	205	__func__, ret);
	206	return ret;
	207	}
	208
	209	ret = regmap_write(drvdata->lpaif_map,
ec9e0ec8	210	LPAIF_DMABUFF_REG(v, ch, dir),
c5c8635a KW	211	(snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
	212	if (ret) {
	213	dev_err(soc_runtime->dev, "%s() error writing to rdmabuff reg: %d\n",
	214	__func__, ret);
	215	return ret;
	216	}
	217
	218	ret = regmap_write(drvdata->lpaif_map,
ec9e0ec8	219	LPAIF_DMAPER_REG(v, ch, dir),
c5c8635a KW	220	(snd_pcm_lib_period_bytes(substream) >> 2) - 1);
	221	if (ret) {
	222	dev_err(soc_runtime->dev, "%s() error writing to rdmaper reg: %d\n",
	223	__func__, ret);
	224	return ret;
	225	}
	226
	227	ret = regmap_update_bits(drvdata->lpaif_map,
ec9e0ec8 SK	228	LPAIF_DMACTL_REG(v, ch, dir),
ec9e0ec8 SK	229	LPAIF_DMACTL_ENABLE_MASK, LPAIF_DMACTL_ENABLE_ON);
c5c8635a KW	230	if (ret) {
	231	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	232	__func__, ret);
	233	return ret;
	234	}
	235
	236	return 0;
	237	}
	238
	239	static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
	240	int cmd)
	241	{
	242	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
6db1c6ba	243	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
c5c8635a KW	244	struct lpass_data *drvdata =
c5c8635a KW	245	snd_soc_platform_get_drvdata(soc_runtime->platform);
9bae4880	246	struct lpass_variant *v = drvdata->variant;
6db1c6ba	247	int ret, ch = pcm_data->rdma_ch;
ec9e0ec8	248	int dir = substream->stream;
c5c8635a KW	249
	250	switch (cmd) {
	251	case SNDRV_PCM_TRIGGER_START:
	252	case SNDRV_PCM_TRIGGER_RESUME:
	253	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	254	/* clear status before enabling interrupts */
	255	ret = regmap_write(drvdata->lpaif_map,
9bae4880	256	LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba	257	LPAIF_IRQ_ALL(ch));
c5c8635a KW	258	if (ret) {
	259	dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
	260	__func__, ret);
	261	return ret;
	262	}
	263
	264	ret = regmap_update_bits(drvdata->lpaif_map,
9bae4880	265	LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba SK	266	LPAIF_IRQ_ALL(ch),
6db1c6ba SK	267	LPAIF_IRQ_ALL(ch));
c5c8635a KW	268	if (ret) {
	269	dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
	270	__func__, ret);
	271	return ret;
	272	}
	273
	274	ret = regmap_update_bits(drvdata->lpaif_map,
ec9e0ec8 SK	275	LPAIF_DMACTL_REG(v, ch, dir),
	276	LPAIF_DMACTL_ENABLE_MASK,
	277	LPAIF_DMACTL_ENABLE_ON);
c5c8635a KW	278	if (ret) {
	279	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	280	__func__, ret);
	281	return ret;
	282	}
	283	break;
	284	case SNDRV_PCM_TRIGGER_STOP:
	285	case SNDRV_PCM_TRIGGER_SUSPEND:
	286	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	287	ret = regmap_update_bits(drvdata->lpaif_map,
ec9e0ec8 SK	288	LPAIF_DMACTL_REG(v, ch, dir),
	289	LPAIF_DMACTL_ENABLE_MASK,
	290	LPAIF_DMACTL_ENABLE_OFF);
c5c8635a KW	291	if (ret) {
	292	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	293	__func__, ret);
	294	return ret;
	295	}
	296
	297	ret = regmap_update_bits(drvdata->lpaif_map,
9bae4880	298	LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba	299	LPAIF_IRQ_ALL(ch), 0);
c5c8635a KW	300	if (ret) {
	301	dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
	302	__func__, ret);
	303	return ret;
	304	}
	305	break;
	306	}
	307
	308	return 0;
	309	}
	310
	311	static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
	312	struct snd_pcm_substream *substream)
	313	{
	314	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
6db1c6ba	315	struct lpass_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(soc_runtime);
c5c8635a KW	316	struct lpass_data *drvdata =
c5c8635a KW	317	snd_soc_platform_get_drvdata(soc_runtime->platform);
9bae4880	318	struct lpass_variant *v = drvdata->variant;
c5c8635a	319	unsigned int base_addr, curr_addr;
6db1c6ba	320	int ret, ch = pcm_data->rdma_ch;
ec9e0ec8	321	int dir = substream->stream;
c5c8635a KW	322
c5c8635a KW	323	ret = regmap_read(drvdata->lpaif_map,
ec9e0ec8	324	LPAIF_DMABASE_REG(v, ch, dir), &base_addr);
c5c8635a KW	325	if (ret) {
	326	dev_err(soc_runtime->dev, "%s() error reading from rdmabase reg: %d\n",
	327	__func__, ret);
	328	return ret;
	329	}
	330
	331	ret = regmap_read(drvdata->lpaif_map,
ec9e0ec8	332	LPAIF_DMACURR_REG(v, ch, dir), &curr_addr);
c5c8635a KW	333	if (ret) {
	334	dev_err(soc_runtime->dev, "%s() error reading from rdmacurr reg: %d\n",
	335	__func__, ret);
	336	return ret;
	337	}
	338
	339	return bytes_to_frames(substream->runtime, curr_addr - base_addr);
	340	}
	341
	342	static int lpass_platform_pcmops_mmap(struct snd_pcm_substream *substream,
	343	struct vm_area_struct *vma)
	344	{
	345	struct snd_pcm_runtime *runtime = substream->runtime;
	346
	347	return dma_mmap_coherent(substream->pcm->card->dev, vma,
	348	runtime->dma_area, runtime->dma_addr,
	349	runtime->dma_bytes);
	350	}
	351
	352	static struct snd_pcm_ops lpass_platform_pcm_ops = {
	353	.open = lpass_platform_pcmops_open,
	354	.ioctl = snd_pcm_lib_ioctl,
	355	.hw_params = lpass_platform_pcmops_hw_params,
	356	.hw_free = lpass_platform_pcmops_hw_free,
	357	.prepare = lpass_platform_pcmops_prepare,
	358	.trigger = lpass_platform_pcmops_trigger,
	359	.pointer = lpass_platform_pcmops_pointer,
	360	.mmap = lpass_platform_pcmops_mmap,
	361	};
	362
4f629e4b SK	363	static irqreturn_t lpass_dma_interrupt_handler(
	364	struct snd_pcm_substream *substream,
	365	struct lpass_data *drvdata,
	366	int chan, u32 interrupts)
c5c8635a	367	{
c5c8635a	368	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
9bae4880	369	struct lpass_variant *v = drvdata->variant;
c5c8635a	370	irqreturn_t ret = IRQ_NONE;
4f629e4b	371	int rv;
6db1c6ba SK	372
6db1c6ba SK	373	if (interrupts & LPAIF_IRQ_PER(chan)) {
c5c8635a	374	rv = regmap_write(drvdata->lpaif_map,
9bae4880	375	LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba	376	LPAIF_IRQ_PER(chan));
c5c8635a KW	377	if (rv) {
	378	dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
	379	__func__, rv);
	380	return IRQ_NONE;
	381	}
	382	snd_pcm_period_elapsed(substream);
	383	ret = IRQ_HANDLED;
	384	}
	385
6db1c6ba	386	if (interrupts & LPAIF_IRQ_XRUN(chan)) {
c5c8635a	387	rv = regmap_write(drvdata->lpaif_map,
9bae4880	388	LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba	389	LPAIF_IRQ_XRUN(chan));
c5c8635a KW	390	if (rv) {
	391	dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
	392	__func__, rv);
	393	return IRQ_NONE;
	394	}
	395	dev_warn(soc_runtime->dev, "%s() xrun warning\n", __func__);
	396	snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
	397	ret = IRQ_HANDLED;
	398	}
	399
6db1c6ba	400	if (interrupts & LPAIF_IRQ_ERR(chan)) {
c5c8635a	401	rv = regmap_write(drvdata->lpaif_map,
9bae4880	402	LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba	403	LPAIF_IRQ_ERR(chan));
c5c8635a KW	404	if (rv) {
	405	dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
	406	__func__, rv);
	407	return IRQ_NONE;
	408	}
	409	dev_err(soc_runtime->dev, "%s() bus access error\n", __func__);
	410	snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
	411	ret = IRQ_HANDLED;
	412	}
	413
	414	return ret;
	415	}
	416
4f629e4b SK	417	static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
	418	{
	419	struct lpass_data *drvdata = data;
	420	struct lpass_variant *v = drvdata->variant;
	421	unsigned int irqs;
	422	int rv, chan;
	423
	424	rv = regmap_read(drvdata->lpaif_map,
	425	LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
	426	if (rv) {
	427	pr_err("%s() error reading from irqstat reg: %d\n",
	428	__func__, rv);
	429	return IRQ_NONE;
	430	}
	431
	432	/* Handle per channel interrupts */
	433	for (chan = 0; chan < LPASS_MAX_DMA_CHANNELS; chan++) {
	434	if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->substream[chan]) {
	435	rv = lpass_dma_interrupt_handler(
	436	drvdata->substream[chan],
	437	drvdata, chan, irqs);
	438	if (rv != IRQ_HANDLED)
	439	return rv;
	440	}
	441	}
	442
	443	return IRQ_HANDLED;
	444	}
	445
c5c8635a KW	446	static int lpass_platform_pcm_new(struct snd_soc_pcm_runtime *soc_runtime)
	447	{
	448	struct snd_pcm *pcm = soc_runtime->pcm;
	449	struct snd_pcm_substream *substream =
	450	pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
6db1c6ba	451	struct snd_soc_dai *cpu_dai = soc_runtime->cpu_dai;
c5c8635a KW	452	struct lpass_data *drvdata =
c5c8635a KW	453	snd_soc_platform_get_drvdata(soc_runtime->platform);
9bae4880	454	struct lpass_variant *v = drvdata->variant;
c5c8635a	455	int ret;
6db1c6ba	456	struct lpass_pcm_data *data;
144a9883	457	size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;
6db1c6ba SK	458
	459	data = devm_kzalloc(soc_runtime->dev, sizeof(*data), GFP_KERNEL);
	460	if (!data)
	461	return -ENOMEM;
	462
	463	if (v->alloc_dma_channel)
73c847b6 SK	464	data->rdma_ch = v->alloc_dma_channel(drvdata,
73c847b6 SK	465	SNDRV_PCM_STREAM_PLAYBACK);
6db1c6ba SK	466
	467	if (IS_ERR_VALUE(data->rdma_ch))
	468	return data->rdma_ch;
	469
4f629e4b	470	drvdata->substream[data->rdma_ch] = substream;
6db1c6ba SK	471	data->i2s_port = cpu_dai->driver->id;
	472
	473	snd_soc_pcm_set_drvdata(soc_runtime, data);
c5c8635a	474
144a9883 SK	475	ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
	476	soc_runtime->platform->dev,
	477	size, &substream->dma_buffer);
c5c8635a KW	478	if (ret)
	479	return ret;
	480
c5c8635a	481	ret = regmap_write(drvdata->lpaif_map,
6db1c6ba	482	LPAIF_RDMACTL_REG(v, data->rdma_ch), 0);
c5c8635a KW	483	if (ret) {
	484	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	485	__func__, ret);
4f629e4b	486	goto err_buf;
c5c8635a KW	487	}
	488
	489	return 0;
	490
	491	err_buf:
144a9883	492	snd_dma_free_pages(&substream->dma_buffer);
c5c8635a KW	493	return ret;
	494	}
	495
	496	static void lpass_platform_pcm_free(struct snd_pcm *pcm)
	497	{
	498	struct snd_pcm_substream *substream =
	499	pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
	500	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
6db1c6ba SK	501	struct lpass_data *drvdata =
	502	snd_soc_platform_get_drvdata(soc_runtime->platform);
	503	struct lpass_pcm_data *data = snd_soc_pcm_get_drvdata(soc_runtime);
	504	struct lpass_variant *v = drvdata->variant;
	505
4f629e4b SK	506	drvdata->substream[data->rdma_ch] = NULL;
4f629e4b SK	507
6db1c6ba SK	508	if (v->free_dma_channel)
6db1c6ba SK	509	v->free_dma_channel(drvdata, data->rdma_ch);
c5c8635a	510
144a9883	511	snd_dma_free_pages(&substream->dma_buffer);
c5c8635a KW	512	}
	513
	514	static struct snd_soc_platform_driver lpass_platform_driver = {
	515	.pcm_new = lpass_platform_pcm_new,
	516	.pcm_free = lpass_platform_pcm_free,
	517	.ops = &lpass_platform_pcm_ops,
	518	};
	519
	520	int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
	521	{
	522	struct lpass_data *drvdata = platform_get_drvdata(pdev);
4f629e4b SK	523	struct lpass_variant *v = drvdata->variant;
4f629e4b SK	524	int ret;
c5c8635a KW	525
	526	drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
	527	if (drvdata->lpaif_irq < 0) {
	528	dev_err(&pdev->dev, "%s() error getting irq handle: %d\n",
	529	__func__, drvdata->lpaif_irq);
	530	return -ENODEV;
	531	}
	532
4f629e4b SK	533	/* ensure audio hardware is disabled */
	534	ret = regmap_write(drvdata->lpaif_map,
	535	LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0);
	536	if (ret) {
	537	dev_err(&pdev->dev, "%s() error writing to irqen reg: %d\n",
	538	__func__, ret);
	539	return ret;
	540	}
	541
	542	ret = devm_request_irq(&pdev->dev, drvdata->lpaif_irq,
	543	lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
	544	"lpass-irq-lpaif", drvdata);
	545	if (ret) {
	546	dev_err(&pdev->dev, "%s() irq request failed: %d\n",
	547	__func__, ret);
	548	return ret;
	549	}
	550
	551
c5c8635a KW	552	return devm_snd_soc_register_platform(&pdev->dev,
	553	&lpass_platform_driver);
	554	}
	555	EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);
	556
	557	MODULE_DESCRIPTION("QTi LPASS Platform Driver");
	558	MODULE_LICENSE("GPL v2");