[deliverable/linux.git] / sound / soc / rockchip / rockchip_i2s.c

/* sound/soc/rockchip/rockchip_i2s.c
 *
 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
 *
 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
 * Author: Jianqun <jay.xu@rock-chips.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/of_gpio.h>
#include <linux/clk.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include <sound/dmaengine_pcm.h>

#include "rockchip_i2s.h"

#define DRV_NAME "rockchip-i2s"

struct rk_i2s_dev {
	struct device *dev;

	struct clk *hclk;
	struct clk *mclk;

	struct snd_dmaengine_dai_dma_data capture_dma_data;
	struct snd_dmaengine_dai_dma_data playback_dma_data;

	struct regmap *regmap;

	bool is_master_mode;
};

static int i2s_runtime_suspend(struct device *dev)
{
	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);

	clk_disable_unprepare(i2s->mclk);

	return 0;
}

static int i2s_runtime_resume(struct device *dev)
{
	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(i2s->mclk);
	if (ret) {
		dev_err(i2s->dev, "clock enable failed %d\n", ret);
		return ret;
	}

	return 0;
}

static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
{
	return snd_soc_dai_get_drvdata(dai);
}

static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
{
	unsigned int val = 0;
	int retry = 10;

	if (on) {
		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);

		regmap_update_bits(i2s->regmap, I2S_XFER,
				   I2S_XFER_TXS_START,
				   I2S_XFER_TXS_START);
	} else {
		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);

		regmap_update_bits(i2s->regmap, I2S_XFER,
				   I2S_XFER_TXS_START,
				   I2S_XFER_TXS_STOP);

		regmap_update_bits(i2s->regmap, I2S_CLR,
				   I2S_CLR_TXC,
				   I2S_CLR_TXC);

		regmap_read(i2s->regmap, I2S_CLR, &val);

		/* Should wait for clear operation to finish */
		while (val & I2S_CLR_TXC) {
			regmap_read(i2s->regmap, I2S_CLR, &val);
			retry--;
			if (!retry) {
				dev_warn(i2s->dev, "fail to clear\n");
				break;
			}
		}
	}
}

static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
{
	unsigned int val = 0;
	int retry = 10;

	if (on) {
		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);

		regmap_update_bits(i2s->regmap, I2S_XFER,
				   I2S_XFER_RXS_START,
				   I2S_XFER_RXS_START);
	} else {
		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);

		regmap_update_bits(i2s->regmap, I2S_XFER,
				   I2S_XFER_RXS_START,
				   I2S_XFER_RXS_STOP);

		regmap_update_bits(i2s->regmap, I2S_CLR,
				   I2S_CLR_RXC,
				   I2S_CLR_RXC);

		regmap_read(i2s->regmap, I2S_CLR, &val);

		/* Should wait for clear operation to finish */
		while (val & I2S_CLR_RXC) {
			regmap_read(i2s->regmap, I2S_CLR, &val);
			retry--;
			if (!retry) {
				dev_warn(i2s->dev, "fail to clear\n");
				break;
			}
		}
	}
}

static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
				unsigned int fmt)
{
	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	unsigned int mask = 0, val = 0;

	mask = I2S_CKR_MSS_MASK;
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* Set source clock in Master mode */
		val = I2S_CKR_MSS_MASTER;
		i2s->is_master_mode = true;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		val = I2S_CKR_MSS_SLAVE;
		i2s->is_master_mode = false;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);

	mask = I2S_TXCR_IBM_MASK;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		val = I2S_TXCR_IBM_RSJM;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		val = I2S_TXCR_IBM_LSJM;
		break;
	case SND_SOC_DAIFMT_I2S:
		val = I2S_TXCR_IBM_NORMAL;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);

	mask = I2S_RXCR_IBM_MASK;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		val = I2S_RXCR_IBM_RSJM;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		val = I2S_RXCR_IBM_LSJM;
		break;
	case SND_SOC_DAIFMT_I2S:
		val = I2S_RXCR_IBM_NORMAL;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);

	return 0;
}

static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
				  struct snd_pcm_hw_params *params,
				  struct snd_soc_dai *dai)
{
	struct rk_i2s_dev *i2s = to_info(dai);
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	unsigned int val = 0;
	unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;

	if (i2s->is_master_mode) {
		mclk_rate = clk_get_rate(i2s->mclk);
		bclk_rate = 2 * 32 * params_rate(params);
		if (bclk_rate && mclk_rate % bclk_rate)
			return -EINVAL;

		div_bclk = mclk_rate / bclk_rate;
		div_lrck = bclk_rate / params_rate(params);
		regmap_update_bits(i2s->regmap, I2S_CKR,
				   I2S_CKR_MDIV_MASK,
				   I2S_CKR_MDIV(div_bclk));

		regmap_update_bits(i2s->regmap, I2S_CKR,
				   I2S_CKR_TSD_MASK |
				   I2S_CKR_RSD_MASK,
				   I2S_CKR_TSD(div_lrck) |
				   I2S_CKR_RSD(div_lrck));
	}

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		val |= I2S_TXCR_VDW(8);
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		val |= I2S_TXCR_VDW(16);
		break;
	case SNDRV_PCM_FORMAT_S20_3LE:
		val |= I2S_TXCR_VDW(20);
		break;
	case SNDRV_PCM_FORMAT_S24_LE:
		val |= I2S_TXCR_VDW(24);
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		val |= I2S_TXCR_VDW(32);
		break;
	default:
		return -EINVAL;
	}

	switch (params_channels(params)) {
	case 8:
		val |= I2S_CHN_8;
		break;
	case 6:
		val |= I2S_CHN_6;
		break;
	case 4:
		val |= I2S_CHN_4;
		break;
	case 2:
		val |= I2S_CHN_2;
		break;
	default:
		dev_err(i2s->dev, "invalid channel: %d\n",
			params_channels(params));
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
		regmap_update_bits(i2s->regmap, I2S_RXCR,
				   I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
				   val);
	else
		regmap_update_bits(i2s->regmap, I2S_TXCR,
				   I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
				   val);

	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
			   I2S_DMACR_TDL(16));
	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
			   I2S_DMACR_RDL(16));

	val = I2S_CKR_TRCM_TXRX;
	if (dai->driver->symmetric_rates || rtd->dai_link->symmetric_rates)
		val = I2S_CKR_TRCM_TXSHARE;

	regmap_update_bits(i2s->regmap, I2S_CKR,
			   I2S_CKR_TRCM_MASK,
			   val);
	return 0;
}

static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
				int cmd, struct snd_soc_dai *dai)
{
	struct rk_i2s_dev *i2s = to_info(dai);
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			rockchip_snd_rxctrl(i2s, 1);
		else
			rockchip_snd_txctrl(i2s, 1);
		break;
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			rockchip_snd_rxctrl(i2s, 0);
		else
			rockchip_snd_txctrl(i2s, 0);
		break;
	default:
		ret = -EINVAL;
		break;
	}

	return ret;
}

static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
				   unsigned int freq, int dir)
{
	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	int ret;

	ret = clk_set_rate(i2s->mclk, freq);
	if (ret)
		dev_err(i2s->dev, "Fail to set mclk %d\n", ret);

	return ret;
}

static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
{
	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);

	dai->capture_dma_data = &i2s->capture_dma_data;
	dai->playback_dma_data = &i2s->playback_dma_data;

	return 0;
}

static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
	.hw_params = rockchip_i2s_hw_params,
	.set_sysclk = rockchip_i2s_set_sysclk,
	.set_fmt = rockchip_i2s_set_fmt,
	.trigger = rockchip_i2s_trigger,
};

static struct snd_soc_dai_driver rockchip_i2s_dai = {
	.probe = rockchip_i2s_dai_probe,
	.playback = {
		.stream_name = "Playback",
		.channels_min = 2,
		.channels_max = 8,
		.rates = SNDRV_PCM_RATE_8000_192000,
		.formats = (SNDRV_PCM_FMTBIT_S8 |
			    SNDRV_PCM_FMTBIT_S16_LE |
			    SNDRV_PCM_FMTBIT_S20_3LE |
			    SNDRV_PCM_FMTBIT_S24_LE |
			    SNDRV_PCM_FMTBIT_S32_LE),
	},
	.capture = {
		.stream_name = "Capture",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_192000,
		.formats = (SNDRV_PCM_FMTBIT_S8 |
			    SNDRV_PCM_FMTBIT_S16_LE |
			    SNDRV_PCM_FMTBIT_S20_3LE |
			    SNDRV_PCM_FMTBIT_S24_LE |
			    SNDRV_PCM_FMTBIT_S32_LE),
	},
	.ops = &rockchip_i2s_dai_ops,
	.symmetric_rates = 1,
};

static const struct snd_soc_component_driver rockchip_i2s_component = {
	.name = DRV_NAME,
};

static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_TXCR:
	case I2S_RXCR:
	case I2S_CKR:
	case I2S_DMACR:
	case I2S_INTCR:
	case I2S_XFER:
	case I2S_CLR:
	case I2S_TXDR:
		return true;
	default:
		return false;
	}
}

static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_TXCR:
	case I2S_RXCR:
	case I2S_CKR:
	case I2S_DMACR:
	case I2S_INTCR:
	case I2S_XFER:
	case I2S_CLR:
	case I2S_RXDR:
	case I2S_FIFOLR:
	case I2S_INTSR:
		return true;
	default:
		return false;
	}
}

static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_INTSR:
	case I2S_CLR:
		return true;
	default:
		return false;
	}
}

static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	default:
		return false;
	}
}

static const struct reg_default rockchip_i2s_reg_defaults[] = {
	{0x00, 0x0000000f},
	{0x04, 0x0000000f},
	{0x08, 0x00071f1f},
	{0x10, 0x001f0000},
	{0x14, 0x01f00000},
};

static const struct regmap_config rockchip_i2s_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = I2S_RXDR,
	.reg_defaults = rockchip_i2s_reg_defaults,
	.num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
	.writeable_reg = rockchip_i2s_wr_reg,
	.readable_reg = rockchip_i2s_rd_reg,
	.volatile_reg = rockchip_i2s_volatile_reg,
	.precious_reg = rockchip_i2s_precious_reg,
	.cache_type = REGCACHE_FLAT,
};

static int rockchip_i2s_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct rk_i2s_dev *i2s;
	struct snd_soc_dai_driver *soc_dai;
	struct resource *res;
	void __iomem *regs;
	int ret;
	int val;

	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
	if (!i2s) {
		dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
		return -ENOMEM;
	}

	/* try to prepare related clocks */
	i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
	if (IS_ERR(i2s->hclk)) {
		dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
		return PTR_ERR(i2s->hclk);
	}
	ret = clk_prepare_enable(i2s->hclk);
	if (ret) {
		dev_err(i2s->dev, "hclock enable failed %d\n", ret);
		return ret;
	}

	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
	if (IS_ERR(i2s->mclk)) {
		dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
		return PTR_ERR(i2s->mclk);
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
					    &rockchip_i2s_regmap_config);
	if (IS_ERR(i2s->regmap)) {
		dev_err(&pdev->dev,
			"Failed to initialise managed register map\n");
		return PTR_ERR(i2s->regmap);
	}

	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	i2s->playback_dma_data.maxburst = 4;

	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	i2s->capture_dma_data.maxburst = 4;

	i2s->dev = &pdev->dev;
	dev_set_drvdata(&pdev->dev, i2s);

	pm_runtime_enable(&pdev->dev);
	if (!pm_runtime_enabled(&pdev->dev)) {
		ret = i2s_runtime_resume(&pdev->dev);
		if (ret)
			goto err_pm_disable;
	}

	soc_dai = devm_kzalloc(&pdev->dev,
			       sizeof(*soc_dai), GFP_KERNEL);
	if (!soc_dai)
		return -ENOMEM;

	memcpy(soc_dai, &rockchip_i2s_dai, sizeof(*soc_dai));
	if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
		if (val >= 2 && val <= 8)
			soc_dai->playback.channels_max = val;
	}

	if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
		if (val >= 2 && val <= 8)
			soc_dai->capture.channels_max = val;
	}

	ret = devm_snd_soc_register_component(&pdev->dev,
					      &rockchip_i2s_component,
					      soc_dai, 1);

	if (ret) {
		dev_err(&pdev->dev, "Could not register DAI\n");
		goto err_suspend;
	}

	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
	if (ret) {
		dev_err(&pdev->dev, "Could not register PCM\n");
		return ret;
	}

	return 0;

err_suspend:
	if (!pm_runtime_status_suspended(&pdev->dev))
		i2s_runtime_suspend(&pdev->dev);
err_pm_disable:
	pm_runtime_disable(&pdev->dev);

	return ret;
}

static int rockchip_i2s_remove(struct platform_device *pdev)
{
	struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		i2s_runtime_suspend(&pdev->dev);

	clk_disable_unprepare(i2s->mclk);
	clk_disable_unprepare(i2s->hclk);

	return 0;
}

static const struct of_device_id rockchip_i2s_match[] = {
	{ .compatible = "rockchip,rk3066-i2s", },
	{ .compatible = "rockchip,rk3188-i2s", },
	{ .compatible = "rockchip,rk3288-i2s", },
	{ .compatible = "rockchip,rk3399-i2s", },
	{},
};

static const struct dev_pm_ops rockchip_i2s_pm_ops = {
	SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
			   NULL)
};

static struct platform_driver rockchip_i2s_driver = {
	.probe = rockchip_i2s_probe,
	.remove = rockchip_i2s_remove,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = of_match_ptr(rockchip_i2s_match),
		.pm = &rockchip_i2s_pm_ops,
	},
};
module_platform_driver(rockchip_i2s_driver);

MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
Commit	Line	Data
4495c89f JX	1	/* sound/soc/rockchip/rockchip_i2s.c
	2	*
	3	* ALSA SoC Audio Layer - Rockchip I2S Controller driver
	4	*
	5	* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
	6	* Author: Jianqun <jay.xu@rock-chips.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
1b21572f	13	#include <linux/module.h>
4495c89f JX	14	#include <linux/delay.h>
	15	#include <linux/of_gpio.h>
	16	#include <linux/clk.h>
	17	#include <linux/pm_runtime.h>
	18	#include <linux/regmap.h>
	19	#include <sound/pcm_params.h>
	20	#include <sound/dmaengine_pcm.h>
	21
	22	#include "rockchip_i2s.h"
	23
	24	#define DRV_NAME "rockchip-i2s"
	25
	26	struct rk_i2s_dev {
	27	struct device *dev;
	28
	29	struct clk *hclk;
	30	struct clk *mclk;
	31
	32	struct snd_dmaengine_dai_dma_data capture_dma_data;
	33	struct snd_dmaengine_dai_dma_data playback_dma_data;
	34
	35	struct regmap *regmap;
	36
2458c377	37	bool is_master_mode;
4495c89f JX	38	};
	39
	40	static int i2s_runtime_suspend(struct device *dev)
	41	{
	42	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
	43
	44	clk_disable_unprepare(i2s->mclk);
	45
	46	return 0;
	47	}
	48
	49	static int i2s_runtime_resume(struct device *dev)
	50	{
	51	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
	52	int ret;
	53
	54	ret = clk_prepare_enable(i2s->mclk);
	55	if (ret) {
	56	dev_err(i2s->dev, "clock enable failed %d\n", ret);
	57	return ret;
	58	}
	59
	60	return 0;
	61	}
	62
	63	static inline struct rk_i2s_dev to_info(struct snd_soc_dai dai)
	64	{
	65	return snd_soc_dai_get_drvdata(dai);
	66	}
	67
	68	static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
	69	{
	70	unsigned int val = 0;
	71	int retry = 10;
	72
	73	if (on) {
	74	regmap_update_bits(i2s->regmap, I2S_DMACR,
	75	I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
	76
	77	regmap_update_bits(i2s->regmap, I2S_XFER,
eba65d17 JK	78	I2S_XFER_TXS_START,
eba65d17 JK	79	I2S_XFER_TXS_START);
4495c89f	80	} else {
4495c89f	81	regmap_update_bits(i2s->regmap, I2S_DMACR,
4c5258ac	82	I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
4495c89f	83
eba65d17 JK	84	regmap_update_bits(i2s->regmap, I2S_XFER,
	85	I2S_XFER_TXS_START,
	86	I2S_XFER_TXS_STOP);
4495c89f	87
eba65d17 JK	88	regmap_update_bits(i2s->regmap, I2S_CLR,
	89	I2S_CLR_TXC,
	90	I2S_CLR_TXC);
4495c89f	91
eba65d17	92	regmap_read(i2s->regmap, I2S_CLR, &val);
4495c89f	93
eba65d17 JK	94	/* Should wait for clear operation to finish */
	95	while (val & I2S_CLR_TXC) {
	96	regmap_read(i2s->regmap, I2S_CLR, &val);
	97	retry--;
	98	if (!retry) {
	99	dev_warn(i2s->dev, "fail to clear\n");
	100	break;
4495c89f JX	101	}
	102	}
	103	}
	104	}
	105
	106	static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
	107	{
	108	unsigned int val = 0;
	109	int retry = 10;
	110
	111	if (on) {
	112	regmap_update_bits(i2s->regmap, I2S_DMACR,
	113	I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
	114
	115	regmap_update_bits(i2s->regmap, I2S_XFER,
eba65d17 JK	116	I2S_XFER_RXS_START,
eba65d17 JK	117	I2S_XFER_RXS_START);
4495c89f	118	} else {
4495c89f JX	119	regmap_update_bits(i2s->regmap, I2S_DMACR,
	120	I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
	121
eba65d17 JK	122	regmap_update_bits(i2s->regmap, I2S_XFER,
	123	I2S_XFER_RXS_START,
	124	I2S_XFER_RXS_STOP);
4495c89f	125
eba65d17 JK	126	regmap_update_bits(i2s->regmap, I2S_CLR,
	127	I2S_CLR_RXC,
	128	I2S_CLR_RXC);
4495c89f	129
eba65d17	130	regmap_read(i2s->regmap, I2S_CLR, &val);
4495c89f	131
eba65d17 JK	132	/* Should wait for clear operation to finish */
	133	while (val & I2S_CLR_RXC) {
	134	regmap_read(i2s->regmap, I2S_CLR, &val);
	135	retry--;
	136	if (!retry) {
	137	dev_warn(i2s->dev, "fail to clear\n");
	138	break;
4495c89f JX	139	}
	140	}
	141	}
	142	}
	143
	144	static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
	145	unsigned int fmt)
	146	{
	147	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	148	unsigned int mask = 0, val = 0;
	149
07833d88	150	mask = I2S_CKR_MSS_MASK;
4495c89f JX	151	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4495c89f JX	152	case SND_SOC_DAIFMT_CBS_CFS:
07833d88 J	153	/* Set source clock in Master mode */
07833d88 J	154	val = I2S_CKR_MSS_MASTER;
2458c377	155	i2s->is_master_mode = true;
4495c89f JX	156	break;
4495c89f JX	157	case SND_SOC_DAIFMT_CBM_CFM:
07833d88	158	val = I2S_CKR_MSS_SLAVE;
2458c377	159	i2s->is_master_mode = false;
4495c89f JX	160	break;
	161	default:
	162	return -EINVAL;
	163	}
	164
	165	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
	166
	167	mask = I2S_TXCR_IBM_MASK;
	168	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	169	case SND_SOC_DAIFMT_RIGHT_J:
	170	val = I2S_TXCR_IBM_RSJM;
	171	break;
	172	case SND_SOC_DAIFMT_LEFT_J:
	173	val = I2S_TXCR_IBM_LSJM;
	174	break;
	175	case SND_SOC_DAIFMT_I2S:
	176	val = I2S_TXCR_IBM_NORMAL;
	177	break;
	178	default:
	179	return -EINVAL;
	180	}
	181
	182	regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
	183
	184	mask = I2S_RXCR_IBM_MASK;
	185	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	186	case SND_SOC_DAIFMT_RIGHT_J:
	187	val = I2S_RXCR_IBM_RSJM;
	188	break;
	189	case SND_SOC_DAIFMT_LEFT_J:
	190	val = I2S_RXCR_IBM_LSJM;
	191	break;
	192	case SND_SOC_DAIFMT_I2S:
	193	val = I2S_RXCR_IBM_NORMAL;
	194	break;
	195	default:
	196	return -EINVAL;
	197	}
	198
	199	regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
	200
	201	return 0;
	202	}
	203
	204	static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
	205	struct snd_pcm_hw_params *params,
	206	struct snd_soc_dai *dai)
	207	{
	208	struct rk_i2s_dev *i2s = to_info(dai);
b3f2dcdd	209	struct snd_soc_pcm_runtime *rtd = substream->private_data;
4495c89f	210	unsigned int val = 0;
2458c377 CW	211	unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
	212
	213	if (i2s->is_master_mode) {
	214	mclk_rate = clk_get_rate(i2s->mclk);
	215	bclk_rate = 2 * 32 * params_rate(params);
	216	if (bclk_rate && mclk_rate % bclk_rate)
	217	return -EINVAL;
	218
	219	div_bclk = mclk_rate / bclk_rate;
	220	div_lrck = bclk_rate / params_rate(params);
	221	regmap_update_bits(i2s->regmap, I2S_CKR,
	222	I2S_CKR_MDIV_MASK,
	223	I2S_CKR_MDIV(div_bclk));
	224
	225	regmap_update_bits(i2s->regmap, I2S_CKR,
	226	I2S_CKR_TSD_MASK \|
	227	I2S_CKR_RSD_MASK,
	228	I2S_CKR_TSD(div_lrck) \|
	229	I2S_CKR_RSD(div_lrck));
	230	}
4495c89f JX	231
	232	switch (params_format(params)) {
	233	case SNDRV_PCM_FORMAT_S8:
	234	val \|= I2S_TXCR_VDW(8);
	235	break;
	236	case SNDRV_PCM_FORMAT_S16_LE:
	237	val \|= I2S_TXCR_VDW(16);
	238	break;
	239	case SNDRV_PCM_FORMAT_S20_3LE:
	240	val \|= I2S_TXCR_VDW(20);
	241	break;
	242	case SNDRV_PCM_FORMAT_S24_LE:
	243	val \|= I2S_TXCR_VDW(24);
	244	break;
4ab936d1 MT	245	case SNDRV_PCM_FORMAT_S32_LE:
	246	val \|= I2S_TXCR_VDW(32);
	247	break;
4495c89f JX	248	default:
	249	return -EINVAL;
	250	}
	251
4c9c018b SZ	252	switch (params_channels(params)) {
	253	case 8:
	254	val \|= I2S_CHN_8;
	255	break;
	256	case 6:
	257	val \|= I2S_CHN_6;
	258	break;
	259	case 4:
	260	val \|= I2S_CHN_4;
	261	break;
	262	case 2:
	263	val \|= I2S_CHN_2;
	264	break;
	265	default:
	266	dev_err(i2s->dev, "invalid channel: %d\n",
	267	params_channels(params));
	268	return -EINVAL;
	269	}
	270
	271	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	272	regmap_update_bits(i2s->regmap, I2S_RXCR,
	273	I2S_RXCR_VDW_MASK \| I2S_RXCR_CSR_MASK,
	274	val);
	275	else
	276	regmap_update_bits(i2s->regmap, I2S_TXCR,
	277	I2S_TXCR_VDW_MASK \| I2S_TXCR_CSR_MASK,
	278	val);
	279
bba14312 JX	280	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
	281	I2S_DMACR_TDL(16));
	282	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
	283	I2S_DMACR_RDL(16));
4495c89f	284
b3f2dcdd SZ	285	val = I2S_CKR_TRCM_TXRX;
	286	if (dai->driver->symmetric_rates \|\| rtd->dai_link->symmetric_rates)
	287	val = I2S_CKR_TRCM_TXSHARE;
	288
	289	regmap_update_bits(i2s->regmap, I2S_CKR,
	290	I2S_CKR_TRCM_MASK,
	291	val);
4495c89f JX	292	return 0;
	293	}
	294
	295	static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
	296	int cmd, struct snd_soc_dai *dai)
	297	{
	298	struct rk_i2s_dev *i2s = to_info(dai);
	299	int ret = 0;
	300
	301	switch (cmd) {
	302	case SNDRV_PCM_TRIGGER_START:
	303	case SNDRV_PCM_TRIGGER_RESUME:
	304	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	305	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	306	rockchip_snd_rxctrl(i2s, 1);
	307	else
	308	rockchip_snd_txctrl(i2s, 1);
	309	break;
	310	case SNDRV_PCM_TRIGGER_SUSPEND:
	311	case SNDRV_PCM_TRIGGER_STOP:
	312	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	313	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	314	rockchip_snd_rxctrl(i2s, 0);
	315	else
	316	rockchip_snd_txctrl(i2s, 0);
	317	break;
	318	default:
	319	ret = -EINVAL;
	320	break;
	321	}
	322
	323	return ret;
	324	}
	325
	326	static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
	327	unsigned int freq, int dir)
	328	{
	329	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	330	int ret;
	331
	332	ret = clk_set_rate(i2s->mclk, freq);
	333	if (ret)
	334	dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
	335
	336	return ret;
	337	}
	338
3b40a802 J	339	static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
	340	{
	341	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
	342
	343	dai->capture_dma_data = &i2s->capture_dma_data;
	344	dai->playback_dma_data = &i2s->playback_dma_data;
	345
	346	return 0;
	347	}
	348
4495c89f JX	349	static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
	350	.hw_params = rockchip_i2s_hw_params,
	351	.set_sysclk = rockchip_i2s_set_sysclk,
	352	.set_fmt = rockchip_i2s_set_fmt,
	353	.trigger = rockchip_i2s_trigger,
	354	};
	355
	356	static struct snd_soc_dai_driver rockchip_i2s_dai = {
3b40a802	357	.probe = rockchip_i2s_dai_probe,
4495c89f	358	.playback = {
3b40a802	359	.stream_name = "Playback",
4495c89f JX	360	.channels_min = 2,
	361	.channels_max = 8,
	362	.rates = SNDRV_PCM_RATE_8000_192000,
	363	.formats = (SNDRV_PCM_FMTBIT_S8 \|
	364	SNDRV_PCM_FMTBIT_S16_LE \|
	365	SNDRV_PCM_FMTBIT_S20_3LE \|
4ab936d1 MT	366	SNDRV_PCM_FMTBIT_S24_LE \|
4ab936d1 MT	367	SNDRV_PCM_FMTBIT_S32_LE),
4495c89f JX	368	},
4495c89f JX	369	.capture = {
3b40a802	370	.stream_name = "Capture",
4495c89f JX	371	.channels_min = 2,
	372	.channels_max = 2,
	373	.rates = SNDRV_PCM_RATE_8000_192000,
	374	.formats = (SNDRV_PCM_FMTBIT_S8 \|
	375	SNDRV_PCM_FMTBIT_S16_LE \|
	376	SNDRV_PCM_FMTBIT_S20_3LE \|
4ab936d1 MT	377	SNDRV_PCM_FMTBIT_S24_LE \|
4ab936d1 MT	378	SNDRV_PCM_FMTBIT_S32_LE),
4495c89f JX	379	},
4495c89f JX	380	.ops = &rockchip_i2s_dai_ops,
a12d159d	381	.symmetric_rates = 1,
4495c89f JX	382	};
	383
	384	static const struct snd_soc_component_driver rockchip_i2s_component = {
	385	.name = DRV_NAME,
	386	};
	387
	388	static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
	389	{
	390	switch (reg) {
	391	case I2S_TXCR:
	392	case I2S_RXCR:
	393	case I2S_CKR:
	394	case I2S_DMACR:
	395	case I2S_INTCR:
	396	case I2S_XFER:
	397	case I2S_CLR:
	398	case I2S_TXDR:
	399	return true;
	400	default:
	401	return false;
	402	}
	403	}
	404
	405	static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
	406	{
	407	switch (reg) {
	408	case I2S_TXCR:
	409	case I2S_RXCR:
	410	case I2S_CKR:
	411	case I2S_DMACR:
	412	case I2S_INTCR:
	413	case I2S_XFER:
	414	case I2S_CLR:
	415	case I2S_RXDR:
2f1e93f8 J	416	case I2S_FIFOLR:
2f1e93f8 J	417	case I2S_INTSR:
4495c89f JX	418	return true;
	419	default:
	420	return false;
	421	}
	422	}
	423
	424	static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
	425	{
	426	switch (reg) {
4495c89f	427	case I2S_INTSR:
2f1e93f8	428	case I2S_CLR:
4495c89f JX	429	return true;
	430	default:
	431	return false;
	432	}
	433	}
	434
	435	static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
	436	{
	437	switch (reg) {
4495c89f JX	438	default:
	439	return false;
	440	}
	441	}
	442
ea2e5b96 SZ	443	static const struct reg_default rockchip_i2s_reg_defaults[] = {
	444	{0x00, 0x0000000f},
	445	{0x04, 0x0000000f},
	446	{0x08, 0x00071f1f},
	447	{0x10, 0x001f0000},
	448	{0x14, 0x01f00000},
	449	};
	450
4495c89f JX	451	static const struct regmap_config rockchip_i2s_regmap_config = {
	452	.reg_bits = 32,
	453	.reg_stride = 4,
	454	.val_bits = 32,
	455	.max_register = I2S_RXDR,
ea2e5b96 SZ	456	.reg_defaults = rockchip_i2s_reg_defaults,
ea2e5b96 SZ	457	.num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
4495c89f JX	458	.writeable_reg = rockchip_i2s_wr_reg,
	459	.readable_reg = rockchip_i2s_rd_reg,
	460	.volatile_reg = rockchip_i2s_volatile_reg,
	461	.precious_reg = rockchip_i2s_precious_reg,
	462	.cache_type = REGCACHE_FLAT,
	463	};
	464
	465	static int rockchip_i2s_probe(struct platform_device *pdev)
	466	{
4c9c018b	467	struct device_node *node = pdev->dev.of_node;
4495c89f	468	struct rk_i2s_dev *i2s;
c4f9374d	469	struct snd_soc_dai_driver *soc_dai;
4495c89f JX	470	struct resource *res;
	471	void __iomem *regs;
	472	int ret;
4c9c018b	473	int val;
4495c89f JX	474
	475	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
	476	if (!i2s) {
	477	dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
	478	return -ENOMEM;
	479	}
	480
	481	/* try to prepare related clocks */
	482	i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
	483	if (IS_ERR(i2s->hclk)) {
	484	dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
	485	return PTR_ERR(i2s->hclk);
	486	}
01605ad1 J	487	ret = clk_prepare_enable(i2s->hclk);
	488	if (ret) {
	489	dev_err(i2s->dev, "hclock enable failed %d\n", ret);
	490	return ret;
	491	}
4495c89f JX	492
	493	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
	494	if (IS_ERR(i2s->mclk)) {
	495	dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
	496	return PTR_ERR(i2s->mclk);
	497	}
	498
	499	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	500	regs = devm_ioremap_resource(&pdev->dev, res);
55b21944	501	if (IS_ERR(regs))
4495c89f	502	return PTR_ERR(regs);
4495c89f JX	503
	504	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
	505	&rockchip_i2s_regmap_config);
	506	if (IS_ERR(i2s->regmap)) {
	507	dev_err(&pdev->dev,
	508	"Failed to initialise managed register map\n");
	509	return PTR_ERR(i2s->regmap);
	510	}
	511
	512	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
	513	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
27fd36ab	514	i2s->playback_dma_data.maxburst = 4;
4495c89f JX	515
	516	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
	517	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
27fd36ab	518	i2s->capture_dma_data.maxburst = 4;
4495c89f JX	519
	520	i2s->dev = &pdev->dev;
	521	dev_set_drvdata(&pdev->dev, i2s);
	522
	523	pm_runtime_enable(&pdev->dev);
	524	if (!pm_runtime_enabled(&pdev->dev)) {
	525	ret = i2s_runtime_resume(&pdev->dev);
	526	if (ret)
	527	goto err_pm_disable;
	528	}
	529
c4f9374d SZ	530	soc_dai = devm_kzalloc(&pdev->dev,
	531	sizeof(*soc_dai), GFP_KERNEL);
	532	if (!soc_dai)
	533	return -ENOMEM;
	534
	535	memcpy(soc_dai, &rockchip_i2s_dai, sizeof(*soc_dai));
	536	if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
	537	if (val >= 2 && val <= 8)
	538	soc_dai->playback.channels_max = val;
	539	}
	540
4c9c018b SZ	541	if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
4c9c018b SZ	542	if (val >= 2 && val <= 8)
c4f9374d	543	soc_dai->capture.channels_max = val;
4c9c018b SZ	544	}
4c9c018b SZ	545
4495c89f JX	546	ret = devm_snd_soc_register_component(&pdev->dev,
4495c89f JX	547	&rockchip_i2s_component,
c4f9374d SZ	548	soc_dai, 1);
c4f9374d SZ	549
4495c89f JX	550	if (ret) {
	551	dev_err(&pdev->dev, "Could not register DAI\n");
	552	goto err_suspend;
	553	}
	554
ebb75c0b	555	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
4495c89f JX	556	if (ret) {
4495c89f JX	557	dev_err(&pdev->dev, "Could not register PCM\n");
ebb75c0b	558	return ret;
4495c89f JX	559	}
	560
	561	return 0;
	562
4495c89f JX	563	err_suspend:
	564	if (!pm_runtime_status_suspended(&pdev->dev))
	565	i2s_runtime_suspend(&pdev->dev);
	566	err_pm_disable:
	567	pm_runtime_disable(&pdev->dev);
	568
	569	return ret;
	570	}
	571
	572	static int rockchip_i2s_remove(struct platform_device *pdev)
	573	{
	574	struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
	575
	576	pm_runtime_disable(&pdev->dev);
	577	if (!pm_runtime_status_suspended(&pdev->dev))
	578	i2s_runtime_suspend(&pdev->dev);
	579
	580	clk_disable_unprepare(i2s->mclk);
	581	clk_disable_unprepare(i2s->hclk);
4495c89f JX	582
	583	return 0;
	584	}
	585
	586	static const struct of_device_id rockchip_i2s_match[] = {
	587	{ .compatible = "rockchip,rk3066-i2s", },
255edcdf JX	588	{ .compatible = "rockchip,rk3188-i2s", },
	589	{ .compatible = "rockchip,rk3288-i2s", },
	590	{ .compatible = "rockchip,rk3399-i2s", },
4495c89f JX	591	{},
	592	};
	593
	594	static const struct dev_pm_ops rockchip_i2s_pm_ops = {
	595	SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
	596	NULL)
	597	};
	598
	599	static struct platform_driver rockchip_i2s_driver = {
	600	.probe = rockchip_i2s_probe,
	601	.remove = rockchip_i2s_remove,
	602	.driver = {
	603	.name = DRV_NAME,
4495c89f JX	604	.of_match_table = of_match_ptr(rockchip_i2s_match),
	605	.pm = &rockchip_i2s_pm_ops,
	606	},
	607	};
	608	module_platform_driver(rockchip_i2s_driver);
	609
	610	MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
	611	MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
	612	MODULE_LICENSE("GPL v2");
	613	MODULE_ALIAS("platform:" DRV_NAME);
	614	MODULE_DEVICE_TABLE(of, rockchip_i2s_match);