[deliverable/linux.git] / sound / soc / rockchip / rockchip_i2s.c

/* sound/soc/rockchip/rockchip_i2s.c
 *
 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
 *
 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
 * Author: Jianqun <jay.xu@rock-chips.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/of_gpio.h>
#include <linux/clk.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include <sound/dmaengine_pcm.h>

#include "rockchip_i2s.h"

#define DRV_NAME "rockchip-i2s"

struct rk_i2s_dev {
	struct device *dev;

	struct clk *hclk;
	struct clk *mclk;

	struct snd_dmaengine_dai_dma_data capture_dma_data;
	struct snd_dmaengine_dai_dma_data playback_dma_data;

	struct regmap *regmap;

/*
 * Used to indicate the tx/rx status.
 * I2S controller hopes to start the tx and rx together,
 * also to stop them when they are both try to stop.
*/
	bool tx_start;
	bool rx_start;
	bool is_master_mode;
};

static int i2s_runtime_suspend(struct device *dev)
{
	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);

	clk_disable_unprepare(i2s->mclk);

	return 0;
}

static int i2s_runtime_resume(struct device *dev)
{
	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(i2s->mclk);
	if (ret) {
		dev_err(i2s->dev, "clock enable failed %d\n", ret);
		return ret;
	}

	return 0;
}

static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
{
	return snd_soc_dai_get_drvdata(dai);
}

static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
{
	unsigned int val = 0;
	int retry = 10;

	if (on) {
		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);

		regmap_update_bits(i2s->regmap, I2S_XFER,
				   I2S_XFER_TXS_START,
				   I2S_XFER_TXS_START);

		i2s->tx_start = true;
	} else {
		i2s->tx_start = false;

		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);

		regmap_update_bits(i2s->regmap, I2S_XFER,
				   I2S_XFER_TXS_START,
				   I2S_XFER_TXS_STOP);

		regmap_update_bits(i2s->regmap, I2S_CLR,
				   I2S_CLR_TXC,
				   I2S_CLR_TXC);

		regmap_read(i2s->regmap, I2S_CLR, &val);

		/* Should wait for clear operation to finish */
		while (val & I2S_CLR_TXC) {
			regmap_read(i2s->regmap, I2S_CLR, &val);
			retry--;
			if (!retry) {
				dev_warn(i2s->dev, "fail to clear\n");
				break;
			}
		}
	}
}

static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
{
	unsigned int val = 0;
	int retry = 10;

	if (on) {
		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);

		regmap_update_bits(i2s->regmap, I2S_XFER,
				   I2S_XFER_RXS_START,
				   I2S_XFER_RXS_START);

		i2s->rx_start = true;
	} else {
		i2s->rx_start = false;

		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);

		regmap_update_bits(i2s->regmap, I2S_XFER,
				   I2S_XFER_RXS_START,
				   I2S_XFER_RXS_STOP);

		regmap_update_bits(i2s->regmap, I2S_CLR,
				   I2S_CLR_RXC,
				   I2S_CLR_RXC);

		regmap_read(i2s->regmap, I2S_CLR, &val);

		/* Should wait for clear operation to finish */
		while (val & I2S_CLR_RXC) {
			regmap_read(i2s->regmap, I2S_CLR, &val);
			retry--;
			if (!retry) {
				dev_warn(i2s->dev, "fail to clear\n");
				break;
			}
		}
	}
}

static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
				unsigned int fmt)
{
	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	unsigned int mask = 0, val = 0;

	mask = I2S_CKR_MSS_MASK;
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* Set source clock in Master mode */
		val = I2S_CKR_MSS_MASTER;
		i2s->is_master_mode = true;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		val = I2S_CKR_MSS_SLAVE;
		i2s->is_master_mode = false;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);

	mask = I2S_TXCR_IBM_MASK;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		val = I2S_TXCR_IBM_RSJM;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		val = I2S_TXCR_IBM_LSJM;
		break;
	case SND_SOC_DAIFMT_I2S:
		val = I2S_TXCR_IBM_NORMAL;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);

	mask = I2S_RXCR_IBM_MASK;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		val = I2S_RXCR_IBM_RSJM;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		val = I2S_RXCR_IBM_LSJM;
		break;
	case SND_SOC_DAIFMT_I2S:
		val = I2S_RXCR_IBM_NORMAL;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);

	return 0;
}

static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
				  struct snd_pcm_hw_params *params,
				  struct snd_soc_dai *dai)
{
	struct rk_i2s_dev *i2s = to_info(dai);
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	unsigned int val = 0;
	unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;

	if (i2s->is_master_mode) {
		mclk_rate = clk_get_rate(i2s->mclk);
		bclk_rate = 2 * 32 * params_rate(params);
		if (bclk_rate && mclk_rate % bclk_rate)
			return -EINVAL;

		div_bclk = mclk_rate / bclk_rate;
		div_lrck = bclk_rate / params_rate(params);
		regmap_update_bits(i2s->regmap, I2S_CKR,
				   I2S_CKR_MDIV_MASK,
				   I2S_CKR_MDIV(div_bclk));

		regmap_update_bits(i2s->regmap, I2S_CKR,
				   I2S_CKR_TSD_MASK |
				   I2S_CKR_RSD_MASK,
				   I2S_CKR_TSD(div_lrck) |
				   I2S_CKR_RSD(div_lrck));
	}

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		val |= I2S_TXCR_VDW(8);
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		val |= I2S_TXCR_VDW(16);
		break;
	case SNDRV_PCM_FORMAT_S20_3LE:
		val |= I2S_TXCR_VDW(20);
		break;
	case SNDRV_PCM_FORMAT_S24_LE:
		val |= I2S_TXCR_VDW(24);
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		val |= I2S_TXCR_VDW(32);
		break;
	default:
		return -EINVAL;
	}

	switch (params_channels(params)) {
	case 8:
		val |= I2S_CHN_8;
		break;
	case 6:
		val |= I2S_CHN_6;
		break;
	case 4:
		val |= I2S_CHN_4;
		break;
	case 2:
		val |= I2S_CHN_2;
		break;
	default:
		dev_err(i2s->dev, "invalid channel: %d\n",
			params_channels(params));
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
		regmap_update_bits(i2s->regmap, I2S_RXCR,
				   I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
				   val);
	else
		regmap_update_bits(i2s->regmap, I2S_TXCR,
				   I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
				   val);

	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
			   I2S_DMACR_TDL(16));
	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
			   I2S_DMACR_RDL(16));

	val = I2S_CKR_TRCM_TXRX;
	if (dai->driver->symmetric_rates || rtd->dai_link->symmetric_rates)
		val = I2S_CKR_TRCM_TXSHARE;

	regmap_update_bits(i2s->regmap, I2S_CKR,
			   I2S_CKR_TRCM_MASK,
			   val);
	return 0;
}

static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
				int cmd, struct snd_soc_dai *dai)
{
	struct rk_i2s_dev *i2s = to_info(dai);
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			rockchip_snd_rxctrl(i2s, 1);
		else
			rockchip_snd_txctrl(i2s, 1);
		break;
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			rockchip_snd_rxctrl(i2s, 0);
		else
			rockchip_snd_txctrl(i2s, 0);
		break;
	default:
		ret = -EINVAL;
		break;
	}

	return ret;
}

static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
				   unsigned int freq, int dir)
{
	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	int ret;

	ret = clk_set_rate(i2s->mclk, freq);
	if (ret)
		dev_err(i2s->dev, "Fail to set mclk %d\n", ret);

	return ret;
}

static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
{
	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);

	dai->capture_dma_data = &i2s->capture_dma_data;
	dai->playback_dma_data = &i2s->playback_dma_data;

	return 0;
}

static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
	.hw_params = rockchip_i2s_hw_params,
	.set_sysclk = rockchip_i2s_set_sysclk,
	.set_fmt = rockchip_i2s_set_fmt,
	.trigger = rockchip_i2s_trigger,
};

static struct snd_soc_dai_driver rockchip_i2s_dai = {
	.probe = rockchip_i2s_dai_probe,
	.playback = {
		.stream_name = "Playback",
		.channels_min = 2,
		.channels_max = 8,
		.rates = SNDRV_PCM_RATE_8000_192000,
		.formats = (SNDRV_PCM_FMTBIT_S8 |
			    SNDRV_PCM_FMTBIT_S16_LE |
			    SNDRV_PCM_FMTBIT_S20_3LE |
			    SNDRV_PCM_FMTBIT_S24_LE |
			    SNDRV_PCM_FMTBIT_S32_LE),
	},
	.capture = {
		.stream_name = "Capture",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_192000,
		.formats = (SNDRV_PCM_FMTBIT_S8 |
			    SNDRV_PCM_FMTBIT_S16_LE |
			    SNDRV_PCM_FMTBIT_S20_3LE |
			    SNDRV_PCM_FMTBIT_S24_LE |
			    SNDRV_PCM_FMTBIT_S32_LE),
	},
	.ops = &rockchip_i2s_dai_ops,
	.symmetric_rates = 1,
};

static const struct snd_soc_component_driver rockchip_i2s_component = {
	.name = DRV_NAME,
};

static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_TXCR:
	case I2S_RXCR:
	case I2S_CKR:
	case I2S_DMACR:
	case I2S_INTCR:
	case I2S_XFER:
	case I2S_CLR:
	case I2S_TXDR:
		return true;
	default:
		return false;
	}
}

static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_TXCR:
	case I2S_RXCR:
	case I2S_CKR:
	case I2S_DMACR:
	case I2S_INTCR:
	case I2S_XFER:
	case I2S_CLR:
	case I2S_RXDR:
	case I2S_FIFOLR:
	case I2S_INTSR:
		return true;
	default:
		return false;
	}
}

static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_INTSR:
	case I2S_CLR:
		return true;
	default:
		return false;
	}
}

static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	default:
		return false;
	}
}

static const struct reg_default rockchip_i2s_reg_defaults[] = {
	{0x00, 0x0000000f},
	{0x04, 0x0000000f},
	{0x08, 0x00071f1f},
	{0x10, 0x001f0000},
	{0x14, 0x01f00000},
};

static const struct regmap_config rockchip_i2s_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = I2S_RXDR,
	.reg_defaults = rockchip_i2s_reg_defaults,
	.num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
	.writeable_reg = rockchip_i2s_wr_reg,
	.readable_reg = rockchip_i2s_rd_reg,
	.volatile_reg = rockchip_i2s_volatile_reg,
	.precious_reg = rockchip_i2s_precious_reg,
	.cache_type = REGCACHE_FLAT,
};

static int rockchip_i2s_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct rk_i2s_dev *i2s;
	struct snd_soc_dai_driver *soc_dai;
	struct resource *res;
	void __iomem *regs;
	int ret;
	int val;

	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
	if (!i2s) {
		dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
		return -ENOMEM;
	}

	/* try to prepare related clocks */
	i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
	if (IS_ERR(i2s->hclk)) {
		dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
		return PTR_ERR(i2s->hclk);
	}
	ret = clk_prepare_enable(i2s->hclk);
	if (ret) {
		dev_err(i2s->dev, "hclock enable failed %d\n", ret);
		return ret;
	}

	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
	if (IS_ERR(i2s->mclk)) {
		dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
		return PTR_ERR(i2s->mclk);
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
					    &rockchip_i2s_regmap_config);
	if (IS_ERR(i2s->regmap)) {
		dev_err(&pdev->dev,
			"Failed to initialise managed register map\n");
		return PTR_ERR(i2s->regmap);
	}

	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	i2s->playback_dma_data.maxburst = 4;

	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	i2s->capture_dma_data.maxburst = 4;

	i2s->dev = &pdev->dev;
	dev_set_drvdata(&pdev->dev, i2s);

	pm_runtime_enable(&pdev->dev);
	if (!pm_runtime_enabled(&pdev->dev)) {
		ret = i2s_runtime_resume(&pdev->dev);
		if (ret)
			goto err_pm_disable;
	}

	soc_dai = devm_kzalloc(&pdev->dev,
			       sizeof(*soc_dai), GFP_KERNEL);
	if (!soc_dai)
		return -ENOMEM;

	memcpy(soc_dai, &rockchip_i2s_dai, sizeof(*soc_dai));
	if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
		if (val >= 2 && val <= 8)
			soc_dai->playback.channels_max = val;
	}

	if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
		if (val >= 2 && val <= 8)
			soc_dai->capture.channels_max = val;
	}

	ret = devm_snd_soc_register_component(&pdev->dev,
					      &rockchip_i2s_component,
					      soc_dai, 1);

	if (ret) {
		dev_err(&pdev->dev, "Could not register DAI\n");
		goto err_suspend;
	}

	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
	if (ret) {
		dev_err(&pdev->dev, "Could not register PCM\n");
		return ret;
	}

	return 0;

err_suspend:
	if (!pm_runtime_status_suspended(&pdev->dev))
		i2s_runtime_suspend(&pdev->dev);
err_pm_disable:
	pm_runtime_disable(&pdev->dev);

	return ret;
}

static int rockchip_i2s_remove(struct platform_device *pdev)
{
	struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		i2s_runtime_suspend(&pdev->dev);

	clk_disable_unprepare(i2s->mclk);
	clk_disable_unprepare(i2s->hclk);

	return 0;
}

static const struct of_device_id rockchip_i2s_match[] = {
	{ .compatible = "rockchip,rk3066-i2s", },
	{ .compatible = "rockchip,rk3188-i2s", },
	{ .compatible = "rockchip,rk3288-i2s", },
	{ .compatible = "rockchip,rk3399-i2s", },
	{},
};

static const struct dev_pm_ops rockchip_i2s_pm_ops = {
	SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
			   NULL)
};

static struct platform_driver rockchip_i2s_driver = {
	.probe = rockchip_i2s_probe,
	.remove = rockchip_i2s_remove,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = of_match_ptr(rockchip_i2s_match),
		.pm = &rockchip_i2s_pm_ops,
	},
};
module_platform_driver(rockchip_i2s_driver);

MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
Commit	Line	Data
4495c89f JX	1	/* sound/soc/rockchip/rockchip_i2s.c
	2	*
	3	* ALSA SoC Audio Layer - Rockchip I2S Controller driver
	4	*
	5	* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
	6	* Author: Jianqun <jay.xu@rock-chips.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
1b21572f	13	#include <linux/module.h>
4495c89f JX	14	#include <linux/delay.h>
	15	#include <linux/of_gpio.h>
	16	#include <linux/clk.h>
	17	#include <linux/pm_runtime.h>
	18	#include <linux/regmap.h>
	19	#include <sound/pcm_params.h>
	20	#include <sound/dmaengine_pcm.h>
	21
	22	#include "rockchip_i2s.h"
	23
	24	#define DRV_NAME "rockchip-i2s"
	25
	26	struct rk_i2s_dev {
	27	struct device *dev;
	28
	29	struct clk *hclk;
	30	struct clk *mclk;
	31
	32	struct snd_dmaengine_dai_dma_data capture_dma_data;
	33	struct snd_dmaengine_dai_dma_data playback_dma_data;
	34
	35	struct regmap *regmap;
	36
a6e806c4 JK	37	/*
	38	* Used to indicate the tx/rx status.
	39	* I2S controller hopes to start the tx and rx together,
	40	* also to stop them when they are both try to stop.
	41	*/
	42	bool tx_start;
	43	bool rx_start;
2458c377	44	bool is_master_mode;
4495c89f JX	45	};
	46
	47	static int i2s_runtime_suspend(struct device *dev)
	48	{
	49	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
	50
	51	clk_disable_unprepare(i2s->mclk);
	52
	53	return 0;
	54	}
	55
	56	static int i2s_runtime_resume(struct device *dev)
	57	{
	58	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
	59	int ret;
	60
	61	ret = clk_prepare_enable(i2s->mclk);
	62	if (ret) {
	63	dev_err(i2s->dev, "clock enable failed %d\n", ret);
	64	return ret;
	65	}
	66
	67	return 0;
	68	}
	69
	70	static inline struct rk_i2s_dev to_info(struct snd_soc_dai dai)
	71	{
	72	return snd_soc_dai_get_drvdata(dai);
	73	}
	74
	75	static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
	76	{
	77	unsigned int val = 0;
	78	int retry = 10;
	79
	80	if (on) {
	81	regmap_update_bits(i2s->regmap, I2S_DMACR,
	82	I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
	83
	84	regmap_update_bits(i2s->regmap, I2S_XFER,
eba65d17 JK	85	I2S_XFER_TXS_START,
eba65d17 JK	86	I2S_XFER_TXS_START);
a6e806c4 JK	87
a6e806c4 JK	88	i2s->tx_start = true;
4495c89f	89	} else {
a6e806c4 JK	90	i2s->tx_start = false;
a6e806c4 JK	91
4495c89f	92	regmap_update_bits(i2s->regmap, I2S_DMACR,
4c5258ac	93	I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
4495c89f	94
eba65d17 JK	95	regmap_update_bits(i2s->regmap, I2S_XFER,
	96	I2S_XFER_TXS_START,
	97	I2S_XFER_TXS_STOP);
4495c89f	98
eba65d17 JK	99	regmap_update_bits(i2s->regmap, I2S_CLR,
	100	I2S_CLR_TXC,
	101	I2S_CLR_TXC);
4495c89f	102
eba65d17	103	regmap_read(i2s->regmap, I2S_CLR, &val);
4495c89f	104
eba65d17 JK	105	/* Should wait for clear operation to finish */
	106	while (val & I2S_CLR_TXC) {
	107	regmap_read(i2s->regmap, I2S_CLR, &val);
	108	retry--;
	109	if (!retry) {
	110	dev_warn(i2s->dev, "fail to clear\n");
	111	break;
4495c89f JX	112	}
	113	}
	114	}
	115	}
	116
	117	static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
	118	{
	119	unsigned int val = 0;
	120	int retry = 10;
	121
	122	if (on) {
	123	regmap_update_bits(i2s->regmap, I2S_DMACR,
	124	I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
	125
	126	regmap_update_bits(i2s->regmap, I2S_XFER,
eba65d17 JK	127	I2S_XFER_RXS_START,
eba65d17 JK	128	I2S_XFER_RXS_START);
a6e806c4 JK	129
a6e806c4 JK	130	i2s->rx_start = true;
4495c89f	131	} else {
a6e806c4 JK	132	i2s->rx_start = false;
a6e806c4 JK	133
4495c89f JX	134	regmap_update_bits(i2s->regmap, I2S_DMACR,
	135	I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
	136
eba65d17 JK	137	regmap_update_bits(i2s->regmap, I2S_XFER,
	138	I2S_XFER_RXS_START,
	139	I2S_XFER_RXS_STOP);
4495c89f	140
eba65d17 JK	141	regmap_update_bits(i2s->regmap, I2S_CLR,
	142	I2S_CLR_RXC,
	143	I2S_CLR_RXC);
4495c89f	144
eba65d17	145	regmap_read(i2s->regmap, I2S_CLR, &val);
4495c89f	146
eba65d17 JK	147	/* Should wait for clear operation to finish */
	148	while (val & I2S_CLR_RXC) {
	149	regmap_read(i2s->regmap, I2S_CLR, &val);
	150	retry--;
	151	if (!retry) {
	152	dev_warn(i2s->dev, "fail to clear\n");
	153	break;
4495c89f JX	154	}
	155	}
	156	}
	157	}
	158
	159	static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
	160	unsigned int fmt)
	161	{
	162	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	163	unsigned int mask = 0, val = 0;
	164
07833d88	165	mask = I2S_CKR_MSS_MASK;
4495c89f JX	166	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4495c89f JX	167	case SND_SOC_DAIFMT_CBS_CFS:
07833d88 J	168	/* Set source clock in Master mode */
07833d88 J	169	val = I2S_CKR_MSS_MASTER;
2458c377	170	i2s->is_master_mode = true;
4495c89f JX	171	break;
4495c89f JX	172	case SND_SOC_DAIFMT_CBM_CFM:
07833d88	173	val = I2S_CKR_MSS_SLAVE;
2458c377	174	i2s->is_master_mode = false;
4495c89f JX	175	break;
	176	default:
	177	return -EINVAL;
	178	}
	179
	180	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
	181
	182	mask = I2S_TXCR_IBM_MASK;
	183	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	184	case SND_SOC_DAIFMT_RIGHT_J:
	185	val = I2S_TXCR_IBM_RSJM;
	186	break;
	187	case SND_SOC_DAIFMT_LEFT_J:
	188	val = I2S_TXCR_IBM_LSJM;
	189	break;
	190	case SND_SOC_DAIFMT_I2S:
	191	val = I2S_TXCR_IBM_NORMAL;
	192	break;
	193	default:
	194	return -EINVAL;
	195	}
	196
	197	regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
	198
	199	mask = I2S_RXCR_IBM_MASK;
	200	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	201	case SND_SOC_DAIFMT_RIGHT_J:
	202	val = I2S_RXCR_IBM_RSJM;
	203	break;
	204	case SND_SOC_DAIFMT_LEFT_J:
	205	val = I2S_RXCR_IBM_LSJM;
	206	break;
	207	case SND_SOC_DAIFMT_I2S:
	208	val = I2S_RXCR_IBM_NORMAL;
	209	break;
	210	default:
	211	return -EINVAL;
	212	}
	213
	214	regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
	215
	216	return 0;
	217	}
	218
	219	static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
	220	struct snd_pcm_hw_params *params,
	221	struct snd_soc_dai *dai)
	222	{
	223	struct rk_i2s_dev *i2s = to_info(dai);
b3f2dcdd	224	struct snd_soc_pcm_runtime *rtd = substream->private_data;
4495c89f	225	unsigned int val = 0;
2458c377 CW	226	unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
	227
	228	if (i2s->is_master_mode) {
	229	mclk_rate = clk_get_rate(i2s->mclk);
	230	bclk_rate = 2 * 32 * params_rate(params);
	231	if (bclk_rate && mclk_rate % bclk_rate)
	232	return -EINVAL;
	233
	234	div_bclk = mclk_rate / bclk_rate;
	235	div_lrck = bclk_rate / params_rate(params);
	236	regmap_update_bits(i2s->regmap, I2S_CKR,
	237	I2S_CKR_MDIV_MASK,
	238	I2S_CKR_MDIV(div_bclk));
	239
	240	regmap_update_bits(i2s->regmap, I2S_CKR,
	241	I2S_CKR_TSD_MASK \|
	242	I2S_CKR_RSD_MASK,
	243	I2S_CKR_TSD(div_lrck) \|
	244	I2S_CKR_RSD(div_lrck));
	245	}
4495c89f JX	246
	247	switch (params_format(params)) {
	248	case SNDRV_PCM_FORMAT_S8:
	249	val \|= I2S_TXCR_VDW(8);
	250	break;
	251	case SNDRV_PCM_FORMAT_S16_LE:
	252	val \|= I2S_TXCR_VDW(16);
	253	break;
	254	case SNDRV_PCM_FORMAT_S20_3LE:
	255	val \|= I2S_TXCR_VDW(20);
	256	break;
	257	case SNDRV_PCM_FORMAT_S24_LE:
	258	val \|= I2S_TXCR_VDW(24);
	259	break;
4ab936d1 MT	260	case SNDRV_PCM_FORMAT_S32_LE:
	261	val \|= I2S_TXCR_VDW(32);
	262	break;
4495c89f JX	263	default:
	264	return -EINVAL;
	265	}
	266
4c9c018b SZ	267	switch (params_channels(params)) {
	268	case 8:
	269	val \|= I2S_CHN_8;
	270	break;
	271	case 6:
	272	val \|= I2S_CHN_6;
	273	break;
	274	case 4:
	275	val \|= I2S_CHN_4;
	276	break;
	277	case 2:
	278	val \|= I2S_CHN_2;
	279	break;
	280	default:
	281	dev_err(i2s->dev, "invalid channel: %d\n",
	282	params_channels(params));
	283	return -EINVAL;
	284	}
	285
	286	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	287	regmap_update_bits(i2s->regmap, I2S_RXCR,
	288	I2S_RXCR_VDW_MASK \| I2S_RXCR_CSR_MASK,
	289	val);
	290	else
	291	regmap_update_bits(i2s->regmap, I2S_TXCR,
	292	I2S_TXCR_VDW_MASK \| I2S_TXCR_CSR_MASK,
	293	val);
	294
bba14312 JX	295	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
	296	I2S_DMACR_TDL(16));
	297	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
	298	I2S_DMACR_RDL(16));
4495c89f	299
b3f2dcdd SZ	300	val = I2S_CKR_TRCM_TXRX;
	301	if (dai->driver->symmetric_rates \|\| rtd->dai_link->symmetric_rates)
	302	val = I2S_CKR_TRCM_TXSHARE;
	303
	304	regmap_update_bits(i2s->regmap, I2S_CKR,
	305	I2S_CKR_TRCM_MASK,
	306	val);
4495c89f JX	307	return 0;
	308	}
	309
	310	static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
	311	int cmd, struct snd_soc_dai *dai)
	312	{
	313	struct rk_i2s_dev *i2s = to_info(dai);
	314	int ret = 0;
	315
	316	switch (cmd) {
	317	case SNDRV_PCM_TRIGGER_START:
	318	case SNDRV_PCM_TRIGGER_RESUME:
	319	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	320	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	321	rockchip_snd_rxctrl(i2s, 1);
	322	else
	323	rockchip_snd_txctrl(i2s, 1);
	324	break;
	325	case SNDRV_PCM_TRIGGER_SUSPEND:
	326	case SNDRV_PCM_TRIGGER_STOP:
	327	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	328	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	329	rockchip_snd_rxctrl(i2s, 0);
	330	else
	331	rockchip_snd_txctrl(i2s, 0);
	332	break;
	333	default:
	334	ret = -EINVAL;
	335	break;
	336	}
	337
	338	return ret;
	339	}
	340
	341	static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
	342	unsigned int freq, int dir)
	343	{
	344	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	345	int ret;
	346
	347	ret = clk_set_rate(i2s->mclk, freq);
	348	if (ret)
	349	dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
	350
	351	return ret;
	352	}
	353
3b40a802 J	354	static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
	355	{
	356	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
	357
	358	dai->capture_dma_data = &i2s->capture_dma_data;
	359	dai->playback_dma_data = &i2s->playback_dma_data;
	360
	361	return 0;
	362	}
	363
4495c89f JX	364	static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
	365	.hw_params = rockchip_i2s_hw_params,
	366	.set_sysclk = rockchip_i2s_set_sysclk,
	367	.set_fmt = rockchip_i2s_set_fmt,
	368	.trigger = rockchip_i2s_trigger,
	369	};
	370
	371	static struct snd_soc_dai_driver rockchip_i2s_dai = {
3b40a802	372	.probe = rockchip_i2s_dai_probe,
4495c89f	373	.playback = {
3b40a802	374	.stream_name = "Playback",
4495c89f JX	375	.channels_min = 2,
	376	.channels_max = 8,
	377	.rates = SNDRV_PCM_RATE_8000_192000,
	378	.formats = (SNDRV_PCM_FMTBIT_S8 \|
	379	SNDRV_PCM_FMTBIT_S16_LE \|
	380	SNDRV_PCM_FMTBIT_S20_3LE \|
4ab936d1 MT	381	SNDRV_PCM_FMTBIT_S24_LE \|
4ab936d1 MT	382	SNDRV_PCM_FMTBIT_S32_LE),
4495c89f JX	383	},
4495c89f JX	384	.capture = {
3b40a802	385	.stream_name = "Capture",
4495c89f JX	386	.channels_min = 2,
	387	.channels_max = 2,
	388	.rates = SNDRV_PCM_RATE_8000_192000,
	389	.formats = (SNDRV_PCM_FMTBIT_S8 \|
	390	SNDRV_PCM_FMTBIT_S16_LE \|
	391	SNDRV_PCM_FMTBIT_S20_3LE \|
4ab936d1 MT	392	SNDRV_PCM_FMTBIT_S24_LE \|
4ab936d1 MT	393	SNDRV_PCM_FMTBIT_S32_LE),
4495c89f JX	394	},
4495c89f JX	395	.ops = &rockchip_i2s_dai_ops,
a12d159d	396	.symmetric_rates = 1,
4495c89f JX	397	};
	398
	399	static const struct snd_soc_component_driver rockchip_i2s_component = {
	400	.name = DRV_NAME,
	401	};
	402
	403	static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
	404	{
	405	switch (reg) {
	406	case I2S_TXCR:
	407	case I2S_RXCR:
	408	case I2S_CKR:
	409	case I2S_DMACR:
	410	case I2S_INTCR:
	411	case I2S_XFER:
	412	case I2S_CLR:
	413	case I2S_TXDR:
	414	return true;
	415	default:
	416	return false;
	417	}
	418	}
	419
	420	static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
	421	{
	422	switch (reg) {
	423	case I2S_TXCR:
	424	case I2S_RXCR:
	425	case I2S_CKR:
	426	case I2S_DMACR:
	427	case I2S_INTCR:
	428	case I2S_XFER:
	429	case I2S_CLR:
	430	case I2S_RXDR:
2f1e93f8 J	431	case I2S_FIFOLR:
2f1e93f8 J	432	case I2S_INTSR:
4495c89f JX	433	return true;
	434	default:
	435	return false;
	436	}
	437	}
	438
	439	static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
	440	{
	441	switch (reg) {
4495c89f	442	case I2S_INTSR:
2f1e93f8	443	case I2S_CLR:
4495c89f JX	444	return true;
	445	default:
	446	return false;
	447	}
	448	}
	449
	450	static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
	451	{
	452	switch (reg) {
4495c89f JX	453	default:
	454	return false;
	455	}
	456	}
	457
ea2e5b96 SZ	458	static const struct reg_default rockchip_i2s_reg_defaults[] = {
	459	{0x00, 0x0000000f},
	460	{0x04, 0x0000000f},
	461	{0x08, 0x00071f1f},
	462	{0x10, 0x001f0000},
	463	{0x14, 0x01f00000},
	464	};
	465
4495c89f JX	466	static const struct regmap_config rockchip_i2s_regmap_config = {
	467	.reg_bits = 32,
	468	.reg_stride = 4,
	469	.val_bits = 32,
	470	.max_register = I2S_RXDR,
ea2e5b96 SZ	471	.reg_defaults = rockchip_i2s_reg_defaults,
ea2e5b96 SZ	472	.num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
4495c89f JX	473	.writeable_reg = rockchip_i2s_wr_reg,
	474	.readable_reg = rockchip_i2s_rd_reg,
	475	.volatile_reg = rockchip_i2s_volatile_reg,
	476	.precious_reg = rockchip_i2s_precious_reg,
	477	.cache_type = REGCACHE_FLAT,
	478	};
	479
	480	static int rockchip_i2s_probe(struct platform_device *pdev)
	481	{
4c9c018b	482	struct device_node *node = pdev->dev.of_node;
4495c89f	483	struct rk_i2s_dev *i2s;
c4f9374d	484	struct snd_soc_dai_driver *soc_dai;
4495c89f JX	485	struct resource *res;
	486	void __iomem *regs;
	487	int ret;
4c9c018b	488	int val;
4495c89f JX	489
	490	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
	491	if (!i2s) {
	492	dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
	493	return -ENOMEM;
	494	}
	495
	496	/* try to prepare related clocks */
	497	i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
	498	if (IS_ERR(i2s->hclk)) {
	499	dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
	500	return PTR_ERR(i2s->hclk);
	501	}
01605ad1 J	502	ret = clk_prepare_enable(i2s->hclk);
	503	if (ret) {
	504	dev_err(i2s->dev, "hclock enable failed %d\n", ret);
	505	return ret;
	506	}
4495c89f JX	507
	508	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
	509	if (IS_ERR(i2s->mclk)) {
	510	dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
	511	return PTR_ERR(i2s->mclk);
	512	}
	513
	514	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	515	regs = devm_ioremap_resource(&pdev->dev, res);
55b21944	516	if (IS_ERR(regs))
4495c89f	517	return PTR_ERR(regs);
4495c89f JX	518
	519	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
	520	&rockchip_i2s_regmap_config);
	521	if (IS_ERR(i2s->regmap)) {
	522	dev_err(&pdev->dev,
	523	"Failed to initialise managed register map\n");
	524	return PTR_ERR(i2s->regmap);
	525	}
	526
	527	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
	528	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
27fd36ab	529	i2s->playback_dma_data.maxburst = 4;
4495c89f JX	530
	531	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
	532	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
27fd36ab	533	i2s->capture_dma_data.maxburst = 4;
4495c89f JX	534
	535	i2s->dev = &pdev->dev;
	536	dev_set_drvdata(&pdev->dev, i2s);
	537
	538	pm_runtime_enable(&pdev->dev);
	539	if (!pm_runtime_enabled(&pdev->dev)) {
	540	ret = i2s_runtime_resume(&pdev->dev);
	541	if (ret)
	542	goto err_pm_disable;
	543	}
	544
c4f9374d SZ	545	soc_dai = devm_kzalloc(&pdev->dev,
	546	sizeof(*soc_dai), GFP_KERNEL);
	547	if (!soc_dai)
	548	return -ENOMEM;
	549
	550	memcpy(soc_dai, &rockchip_i2s_dai, sizeof(*soc_dai));
	551	if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
	552	if (val >= 2 && val <= 8)
	553	soc_dai->playback.channels_max = val;
	554	}
	555
4c9c018b SZ	556	if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
4c9c018b SZ	557	if (val >= 2 && val <= 8)
c4f9374d	558	soc_dai->capture.channels_max = val;
4c9c018b SZ	559	}
4c9c018b SZ	560
4495c89f JX	561	ret = devm_snd_soc_register_component(&pdev->dev,
4495c89f JX	562	&rockchip_i2s_component,
c4f9374d SZ	563	soc_dai, 1);
c4f9374d SZ	564
4495c89f JX	565	if (ret) {
	566	dev_err(&pdev->dev, "Could not register DAI\n");
	567	goto err_suspend;
	568	}
	569
ebb75c0b	570	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
4495c89f JX	571	if (ret) {
4495c89f JX	572	dev_err(&pdev->dev, "Could not register PCM\n");
ebb75c0b	573	return ret;
4495c89f JX	574	}
	575
	576	return 0;
	577
4495c89f JX	578	err_suspend:
	579	if (!pm_runtime_status_suspended(&pdev->dev))
	580	i2s_runtime_suspend(&pdev->dev);
	581	err_pm_disable:
	582	pm_runtime_disable(&pdev->dev);
	583
	584	return ret;
	585	}
	586
	587	static int rockchip_i2s_remove(struct platform_device *pdev)
	588	{
	589	struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
	590
	591	pm_runtime_disable(&pdev->dev);
	592	if (!pm_runtime_status_suspended(&pdev->dev))
	593	i2s_runtime_suspend(&pdev->dev);
	594
	595	clk_disable_unprepare(i2s->mclk);
	596	clk_disable_unprepare(i2s->hclk);
4495c89f JX	597
	598	return 0;
	599	}
	600
	601	static const struct of_device_id rockchip_i2s_match[] = {
	602	{ .compatible = "rockchip,rk3066-i2s", },
255edcdf JX	603	{ .compatible = "rockchip,rk3188-i2s", },
	604	{ .compatible = "rockchip,rk3288-i2s", },
	605	{ .compatible = "rockchip,rk3399-i2s", },
4495c89f JX	606	{},
	607	};
	608
	609	static const struct dev_pm_ops rockchip_i2s_pm_ops = {
	610	SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
	611	NULL)
	612	};
	613
	614	static struct platform_driver rockchip_i2s_driver = {
	615	.probe = rockchip_i2s_probe,
	616	.remove = rockchip_i2s_remove,
	617	.driver = {
	618	.name = DRV_NAME,
4495c89f JX	619	.of_match_table = of_match_ptr(rockchip_i2s_match),
	620	.pm = &rockchip_i2s_pm_ops,
	621	},
	622	};
	623	module_platform_driver(rockchip_i2s_driver);
	624
	625	MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
	626	MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
	627	MODULE_LICENSE("GPL v2");
	628	MODULE_ALIAS("platform:" DRV_NAME);
	629	MODULE_DEVICE_TABLE(of, rockchip_i2s_match);