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4495c89f JX |
1 | /* |
2 | * sound/soc/rockchip/rockchip_i2s.h | |
3 | * | |
4 | * ALSA SoC Audio Layer - Rockchip I2S Controller driver | |
5 | * | |
6 | * Copyright (c) 2014 Rockchip Electronics Co. Ltd. | |
7 | * Author: Jianqun xu <jay.xu@rock-chips.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #ifndef _ROCKCHIP_IIS_H | |
15 | #define _ROCKCHIP_IIS_H | |
16 | ||
17 | /* | |
18 | * TXCR | |
19 | * transmit operation control register | |
20 | */ | |
21 | #define I2S_TXCR_RCNT_SHIFT 17 | |
22 | #define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT) | |
23 | #define I2S_TXCR_CSR_SHIFT 15 | |
24 | #define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT) | |
25 | #define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT) | |
26 | #define I2S_TXCR_HWT BIT(14) | |
27 | #define I2S_TXCR_SJM_SHIFT 12 | |
28 | #define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT) | |
29 | #define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT) | |
30 | #define I2S_TXCR_FBM_SHIFT 11 | |
31 | #define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT) | |
32 | #define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT) | |
33 | #define I2S_TXCR_IBM_SHIFT 9 | |
34 | #define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT) | |
35 | #define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT) | |
36 | #define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT) | |
37 | #define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT) | |
38 | #define I2S_TXCR_PBM_SHIFT 7 | |
39 | #define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT) | |
40 | #define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT) | |
41 | #define I2S_TXCR_TFS_SHIFT 5 | |
42 | #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT) | |
43 | #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT) | |
44 | #define I2S_TXCR_VDW_SHIFT 0 | |
45 | #define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT) | |
46 | #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT) | |
47 | ||
48 | /* | |
49 | * RXCR | |
50 | * receive operation control register | |
51 | */ | |
52 | #define I2S_RXCR_HWT BIT(14) | |
53 | #define I2S_RXCR_SJM_SHIFT 12 | |
54 | #define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT) | |
55 | #define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT) | |
56 | #define I2S_RXCR_FBM_SHIFT 11 | |
57 | #define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT) | |
58 | #define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT) | |
59 | #define I2S_RXCR_IBM_SHIFT 9 | |
60 | #define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT) | |
61 | #define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT) | |
62 | #define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT) | |
63 | #define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT) | |
64 | #define I2S_RXCR_PBM_SHIFT 7 | |
65 | #define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT) | |
66 | #define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT) | |
67 | #define I2S_RXCR_TFS_SHIFT 5 | |
68 | #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT) | |
69 | #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT) | |
70 | #define I2S_RXCR_VDW_SHIFT 0 | |
71 | #define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT) | |
72 | #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT) | |
73 | ||
74 | /* | |
75 | * CKR | |
76 | * clock generation register | |
77 | */ | |
78 | #define I2S_CKR_MSS_SHIFT 27 | |
79 | #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT) | |
80 | #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT) | |
81 | #define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT) | |
82 | #define I2S_CKR_CKP_SHIFT 26 | |
83 | #define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT) | |
84 | #define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT) | |
85 | #define I2S_CKR_RLP_SHIFT 25 | |
86 | #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT) | |
87 | #define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT) | |
88 | #define I2S_CKR_TLP_SHIFT 24 | |
89 | #define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT) | |
90 | #define I2S_CKR_TLP_OPPSITE (1 << I2S_CKR_TLP_SHIFT) | |
91 | #define I2S_CKR_MDIV_SHIFT 16 | |
92 | #define I2S_CKR_MDIV(x) ((x - 1) << I2S_CKR_MDIV_SHIFT) | |
93 | #define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT) | |
94 | #define I2S_CKR_RSD_SHIFT 8 | |
95 | #define I2S_CKR_RSD(x) ((x - 1) << I2S_CKR_RSD_SHIFT) | |
96 | #define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT) | |
97 | #define I2S_CKR_TSD_SHIFT 0 | |
98 | #define I2S_CKR_TSD(x) ((x - 1) << I2S_CKR_TSD_SHIFT) | |
99 | #define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT) | |
100 | ||
101 | /* | |
102 | * FIFOLR | |
103 | * FIFO level register | |
104 | */ | |
105 | #define I2S_FIFOLR_RFL_SHIFT 24 | |
106 | #define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT) | |
107 | #define I2S_FIFOLR_TFL3_SHIFT 18 | |
108 | #define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT) | |
109 | #define I2S_FIFOLR_TFL2_SHIFT 12 | |
110 | #define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT) | |
111 | #define I2S_FIFOLR_TFL1_SHIFT 6 | |
112 | #define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT) | |
113 | #define I2S_FIFOLR_TFL0_SHIFT 0 | |
114 | #define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT) | |
115 | ||
116 | /* | |
117 | * DMACR | |
118 | * DMA control register | |
119 | */ | |
120 | #define I2S_DMACR_RDE_SHIFT 24 | |
121 | #define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT) | |
122 | #define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT) | |
123 | #define I2S_DMACR_RDL_SHIFT 16 | |
124 | #define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT) | |
125 | #define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT) | |
126 | #define I2S_DMACR_TDE_SHIFT 8 | |
127 | #define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT) | |
128 | #define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT) | |
129 | #define I2S_DMACR_TDL_SHIFT 0 | |
4db9c4a9 | 130 | #define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT) |
4495c89f JX |
131 | #define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT) |
132 | ||
133 | /* | |
134 | * INTCR | |
135 | * interrupt control register | |
136 | */ | |
137 | #define I2S_INTCR_RFT_SHIFT 20 | |
138 | #define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT) | |
139 | #define I2S_INTCR_RXOIC BIT(18) | |
140 | #define I2S_INTCR_RXOIE_SHIFT 17 | |
141 | #define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT) | |
142 | #define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT) | |
143 | #define I2S_INTCR_RXFIE_SHIFT 16 | |
144 | #define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT) | |
145 | #define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT) | |
146 | #define I2S_INTCR_TFT_SHIFT 4 | |
147 | #define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT) | |
148 | #define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT) | |
149 | #define I2S_INTCR_TXUIC BIT(2) | |
150 | #define I2S_INTCR_TXUIE_SHIFT 1 | |
151 | #define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT) | |
152 | #define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT) | |
153 | ||
154 | /* | |
155 | * INTSR | |
156 | * interrupt status register | |
157 | */ | |
158 | #define I2S_INTSR_TXEIE_SHIFT 0 | |
159 | #define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTSR_TXEIE_SHIFT) | |
160 | #define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTSR_TXEIE_SHIFT) | |
161 | #define I2S_INTSR_RXOI_SHIFT 17 | |
162 | #define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT) | |
163 | #define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT) | |
164 | #define I2S_INTSR_RXFI_SHIFT 16 | |
165 | #define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT) | |
166 | #define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT) | |
167 | #define I2S_INTSR_TXUI_SHIFT 1 | |
168 | #define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT) | |
169 | #define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT) | |
170 | #define I2S_INTSR_TXEI_SHIFT 0 | |
171 | #define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT) | |
172 | #define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT) | |
173 | ||
174 | /* | |
175 | * XFER | |
176 | * Transfer start register | |
177 | */ | |
178 | #define I2S_XFER_RXS_SHIFT 1 | |
179 | #define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT) | |
180 | #define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT) | |
181 | #define I2S_XFER_TXS_SHIFT 0 | |
182 | #define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT) | |
183 | #define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT) | |
184 | ||
185 | /* | |
186 | * CLR | |
187 | * clear SCLK domain logic register | |
188 | */ | |
189 | #define I2S_CLR_RXC BIT(1) | |
190 | #define I2S_CLR_TXC BIT(0) | |
191 | ||
192 | /* | |
193 | * TXDR | |
194 | * Transimt FIFO data register, write only. | |
195 | */ | |
196 | #define I2S_TXDR_MASK (0xff) | |
197 | ||
198 | /* | |
199 | * RXDR | |
200 | * Receive FIFO data register, write only. | |
201 | */ | |
202 | #define I2S_RXDR_MASK (0xff) | |
203 | ||
204 | /* Clock divider id */ | |
205 | enum { | |
206 | ROCKCHIP_DIV_MCLK = 0, | |
207 | ROCKCHIP_DIV_BCLK, | |
208 | }; | |
209 | ||
210 | /* I2S REGS */ | |
211 | #define I2S_TXCR (0x0000) | |
212 | #define I2S_RXCR (0x0004) | |
213 | #define I2S_CKR (0x0008) | |
214 | #define I2S_FIFOLR (0x000c) | |
215 | #define I2S_DMACR (0x0010) | |
216 | #define I2S_INTCR (0x0014) | |
217 | #define I2S_INTSR (0x0018) | |
218 | #define I2S_XFER (0x001c) | |
219 | #define I2S_CLR (0x0020) | |
220 | #define I2S_TXDR (0x0024) | |
221 | #define I2S_RXDR (0x0028) | |
222 | ||
223 | #endif /* _ROCKCHIP_IIS_H */ |