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f874b80e SS |
1 | /* |
2 | * ALSA SoC Audio Layer - Rockchip SPDIF transceiver driver | |
3 | * | |
4 | * Copyright (c) 2015 Collabora Ltd. | |
5 | * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #ifndef _ROCKCHIP_SPDIF_H | |
13 | #define _ROCKCHIP_SPDIF_H | |
14 | ||
15 | /* | |
16 | * CFGR | |
17 | * transfer configuration register | |
18 | */ | |
19 | #define SPDIF_CFGR_CLK_DIV_SHIFT (16) | |
20 | #define SPDIF_CFGR_CLK_DIV_MASK (0xff << SPDIF_CFGR_CLK_DIV_SHIFT) | |
21 | #define SPDIF_CFGR_CLK_DIV(x) (x << SPDIF_CFGR_CLK_DIV_SHIFT) | |
22 | ||
23 | #define SPDIF_CFGR_HALFWORD_SHIFT 2 | |
24 | #define SPDIF_CFGR_HALFWORD_DISABLE (0 << SPDIF_CFGR_HALFWORD_SHIFT) | |
25 | #define SPDIF_CFGR_HALFWORD_ENABLE (1 << SPDIF_CFGR_HALFWORD_SHIFT) | |
26 | ||
27 | #define SPDIF_CFGR_VDW_SHIFT 0 | |
28 | #define SPDIF_CFGR_VDW(x) (x << SPDIF_CFGR_VDW_SHIFT) | |
29 | #define SDPIF_CFGR_VDW_MASK (0xf << SPDIF_CFGR_VDW_SHIFT) | |
30 | ||
18a9d748 SS |
31 | #define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x0) |
32 | #define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x1) | |
33 | #define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x2) | |
f874b80e SS |
34 | |
35 | /* | |
36 | * DMACR | |
37 | * DMA control register | |
38 | */ | |
39 | #define SPDIF_DMACR_TDE_SHIFT 5 | |
40 | #define SPDIF_DMACR_TDE_DISABLE (0 << SPDIF_DMACR_TDE_SHIFT) | |
41 | #define SPDIF_DMACR_TDE_ENABLE (1 << SPDIF_DMACR_TDE_SHIFT) | |
42 | ||
43 | #define SPDIF_DMACR_TDL_SHIFT 0 | |
44 | #define SPDIF_DMACR_TDL(x) ((x) << SPDIF_DMACR_TDL_SHIFT) | |
5042f936 | 45 | #define SPDIF_DMACR_TDL_MASK (0x1f << SPDIF_DMACR_TDL_SHIFT) |
f874b80e SS |
46 | |
47 | /* | |
48 | * XFER | |
49 | * Transfer control register | |
50 | */ | |
51 | #define SPDIF_XFER_TXS_SHIFT 0 | |
52 | #define SPDIF_XFER_TXS_STOP (0 << SPDIF_XFER_TXS_SHIFT) | |
53 | #define SPDIF_XFER_TXS_START (1 << SPDIF_XFER_TXS_SHIFT) | |
54 | ||
55 | #define SPDIF_CFGR (0x0000) | |
56 | #define SPDIF_SDBLR (0x0004) | |
57 | #define SPDIF_DMACR (0x0008) | |
58 | #define SPDIF_INTCR (0x000c) | |
59 | #define SPDIF_INTSR (0x0010) | |
60 | #define SPDIF_XFER (0x0018) | |
61 | #define SPDIF_SMPDR (0x0020) | |
62 | ||
63 | #endif /* _ROCKCHIP_SPDIF_H */ |