[deliverable/linux.git] / sound / soc / s3c24xx / s3c-ac97.c

/* sound/soc/s3c24xx/s3c-ac97.c
 *
 * ALSA SoC Audio Layer - S3C AC97 Controller driver
 * 	Evolved from s3c2443-ac97.c
 *
 * Copyright (c) 2010 Samsung Electronics Co. Ltd
 * 	Author: Jaswinder Singh <jassi.brar@samsung.com>
 * 	Credits: Graeme Gregory, Sean Choi
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/clk.h>

#include <sound/soc.h>

#include <plat/regs-ac97.h>
#include <mach/dma.h>
#include <plat/audio.h>

#include "s3c-dma.h"
#include "s3c-ac97.h"

#define AC_CMD_ADDR(x) (x << 16)
#define AC_CMD_DATA(x) (x & 0xffff)

struct s3c_ac97_info {
	unsigned           state;
	struct clk         *ac97_clk;
	void __iomem	   *regs;
	struct mutex       lock;
	struct completion  done;
};
static struct s3c_ac97_info s3c_ac97;

static struct s3c2410_dma_client s3c_dma_client_out = {
	.name = "AC97 PCMOut"
};

static struct s3c2410_dma_client s3c_dma_client_in = {
	.name = "AC97 PCMIn"
};

static struct s3c2410_dma_client s3c_dma_client_micin = {
	.name = "AC97 MicIn"
};

static struct s3c_dma_params s3c_ac97_pcm_out = {
	.client		= &s3c_dma_client_out,
	.dma_size	= 4,
};

static struct s3c_dma_params s3c_ac97_pcm_in = {
	.client		= &s3c_dma_client_in,
	.dma_size	= 4,
};

static struct s3c_dma_params s3c_ac97_mic_in = {
	.client		= &s3c_dma_client_micin,
	.dma_size	= 4,
};

static void s3c_ac97_activate(struct snd_ac97 *ac97)
{
	u32 ac_glbctrl, stat;

	stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
	if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
		return; /* Return if already active */

	INIT_COMPLETION(s3c_ac97.done);

	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
	ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
	msleep(1);

	ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
	msleep(1);

	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
	ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);

	if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
		printk(KERN_ERR "AC97: Unable to activate!");
}

static unsigned short s3c_ac97_read(struct snd_ac97 *ac97,
	unsigned short reg)
{
	u32 ac_glbctrl, ac_codec_cmd;
	u32 stat, addr, data;

	mutex_lock(&s3c_ac97.lock);

	s3c_ac97_activate(ac97);

	INIT_COMPLETION(s3c_ac97.done);

	ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
	ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
	writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);

	udelay(50);

	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
	ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);

	if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
		printk(KERN_ERR "AC97: Unable to read!");

	stat = readl(s3c_ac97.regs + S3C_AC97_STAT);
	addr = (stat >> 16) & 0x7f;
	data = (stat & 0xffff);

	if (addr != reg)
		printk(KERN_ERR "s3c-ac97: req addr = %02x, rep addr = %02x\n", reg, addr);

	mutex_unlock(&s3c_ac97.lock);

	return (unsigned short)data;
}

static void s3c_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
	unsigned short val)
{
	u32 ac_glbctrl, ac_codec_cmd;

	mutex_lock(&s3c_ac97.lock);

	s3c_ac97_activate(ac97);

	INIT_COMPLETION(s3c_ac97.done);

	ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
	ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
	writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);

	udelay(50);

	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
	ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);

	if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
		printk(KERN_ERR "AC97: Unable to write!");

	ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
	ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
	writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);

	mutex_unlock(&s3c_ac97.lock);
}

static void s3c_ac97_cold_reset(struct snd_ac97 *ac97)
{
	writel(S3C_AC97_GLBCTRL_COLDRESET,
			s3c_ac97.regs + S3C_AC97_GLBCTRL);
	msleep(1);

	writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
	msleep(1);
}

static void s3c_ac97_warm_reset(struct snd_ac97 *ac97)
{
	u32 stat;

	stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
	if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
		return; /* Return if already active */

	writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL);
	msleep(1);

	writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
	msleep(1);

	s3c_ac97_activate(ac97);
}

static irqreturn_t s3c_ac97_irq(int irq, void *dev_id)
{
	u32 ac_glbctrl, ac_glbstat;

	ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT);

	if (ac_glbstat & S3C_AC97_GLBSTAT_CODECREADY) {

		ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
		ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
		writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);

		complete(&s3c_ac97.done);
	}

	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
	ac_glbctrl |= (1<<30); /* Clear interrupt */
	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);

	return IRQ_HANDLED;
}

struct snd_ac97_bus_ops soc_ac97_ops = {
	.read       = s3c_ac97_read,
	.write      = s3c_ac97_write,
	.warm_reset = s3c_ac97_warm_reset,
	.reset      = s3c_ac97_cold_reset,
};
EXPORT_SYMBOL_GPL(soc_ac97_ops);

static int s3c_ac97_hw_params(struct snd_pcm_substream *substream,
				  struct snd_pcm_hw_params *params,
				  struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct s3c_dma_params *dma_data;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		dma_data = &s3c_ac97_pcm_out;
	else
		dma_data = &s3c_ac97_pcm_in;

	snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);

	return 0;
}

static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
				struct snd_soc_dai *dai)
{
	u32 ac_glbctrl;
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct s3c_dma_params *dma_data =
		snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream);

	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
		ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
	else
		ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
		else
			ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		break;
	}

	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);

	s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);

	return 0;
}

static int s3c_ac97_hw_mic_params(struct snd_pcm_substream *substream,
				      struct snd_pcm_hw_params *params,
				      struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		return -ENODEV;
	else
		snd_soc_dai_set_dma_data(cpu_dai, substream, &s3c_ac97_mic_in);

	return 0;
}

static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
				    int cmd, struct snd_soc_dai *dai)
{
	u32 ac_glbctrl;
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct s3c_dma_params *dma_data =
		snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream);

	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
	ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		ac_glbctrl |= S3C_AC97_GLBCTRL_MICINTM_DMA;
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		break;
	}

	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);

	s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);

	return 0;
}

static struct snd_soc_dai_ops s3c_ac97_dai_ops = {
	.hw_params	= s3c_ac97_hw_params,
	.trigger	= s3c_ac97_trigger,
};

static struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = {
	.hw_params	= s3c_ac97_hw_mic_params,
	.trigger	= s3c_ac97_mic_trigger,
};

struct snd_soc_dai s3c_ac97_dai[] = {
	[S3C_AC97_DAI_PCM] = {
		.name =	"s3c-ac97",
		.id = S3C_AC97_DAI_PCM,
		.ac97_control = 1,
		.playback = {
			.stream_name = "AC97 Playback",
			.channels_min = 2,
			.channels_max = 2,
			.rates = SNDRV_PCM_RATE_8000_48000,
			.formats = SNDRV_PCM_FMTBIT_S16_LE,},
		.capture = {
			.stream_name = "AC97 Capture",
			.channels_min = 2,
			.channels_max = 2,
			.rates = SNDRV_PCM_RATE_8000_48000,
			.formats = SNDRV_PCM_FMTBIT_S16_LE,},
		.ops = &s3c_ac97_dai_ops,
	},
	[S3C_AC97_DAI_MIC] = {
		.name = "s3c-ac97-mic",
		.id = S3C_AC97_DAI_MIC,
		.ac97_control = 1,
		.capture = {
			.stream_name = "AC97 Mic Capture",
			.channels_min = 1,
			.channels_max = 1,
			.rates = SNDRV_PCM_RATE_8000_48000,
			.formats = SNDRV_PCM_FMTBIT_S16_LE,},
		.ops = &s3c_ac97_mic_dai_ops,
	},
};
EXPORT_SYMBOL_GPL(s3c_ac97_dai);

static __devinit int s3c_ac97_probe(struct platform_device *pdev)
{
	struct resource *mem_res, *dmatx_res, *dmarx_res, *dmamic_res, *irq_res;
	struct s3c_audio_pdata *ac97_pdata;
	int ret;

	ac97_pdata = pdev->dev.platform_data;
	if (!ac97_pdata || !ac97_pdata->cfg_gpio) {
		dev_err(&pdev->dev, "cfg_gpio callback not provided!\n");
		return -EINVAL;
	}

	/* Check for availability of necessary resource */
	dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	if (!dmatx_res) {
		dev_err(&pdev->dev, "Unable to get AC97-TX dma resource\n");
		return -ENXIO;
	}

	dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
	if (!dmarx_res) {
		dev_err(&pdev->dev, "Unable to get AC97-RX dma resource\n");
		return -ENXIO;
	}

	dmamic_res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
	if (!dmamic_res) {
		dev_err(&pdev->dev, "Unable to get AC97-MIC dma resource\n");
		return -ENXIO;
	}

	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem_res) {
		dev_err(&pdev->dev, "Unable to get register resource\n");
		return -ENXIO;
	}

	irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!irq_res) {
		dev_err(&pdev->dev, "AC97 IRQ not provided!\n");
		return -ENXIO;
	}

	if (!request_mem_region(mem_res->start,
				resource_size(mem_res), "s3c-ac97")) {
		dev_err(&pdev->dev, "Unable to request register region\n");
		return -EBUSY;
	}

	s3c_ac97_pcm_out.channel = dmatx_res->start;
	s3c_ac97_pcm_out.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
	s3c_ac97_pcm_in.channel = dmarx_res->start;
	s3c_ac97_pcm_in.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
	s3c_ac97_mic_in.channel = dmamic_res->start;
	s3c_ac97_mic_in.dma_addr = mem_res->start + S3C_AC97_MIC_DATA;

	init_completion(&s3c_ac97.done);
	mutex_init(&s3c_ac97.lock);

	s3c_ac97.regs = ioremap(mem_res->start, resource_size(mem_res));
	if (s3c_ac97.regs == NULL) {
		dev_err(&pdev->dev, "Unable to ioremap register region\n");
		ret = -ENXIO;
		goto err1;
	}

	s3c_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
	if (IS_ERR(s3c_ac97.ac97_clk)) {
		dev_err(&pdev->dev, "s3c-ac97 failed to get ac97_clock\n");
		ret = -ENODEV;
		goto err2;
	}
	clk_enable(s3c_ac97.ac97_clk);

	if (ac97_pdata->cfg_gpio(pdev)) {
		dev_err(&pdev->dev, "Unable to configure gpio\n");
		ret = -EINVAL;
		goto err3;
	}

	ret = request_irq(irq_res->start, s3c_ac97_irq,
					IRQF_DISABLED, "AC97", NULL);
	if (ret < 0) {
		printk(KERN_ERR "s3c-ac97: interrupt request failed.\n");
		goto err4;
	}

	s3c_ac97_dai[S3C_AC97_DAI_PCM].dev = &pdev->dev;
	s3c_ac97_dai[S3C_AC97_DAI_MIC].dev = &pdev->dev;

	ret = snd_soc_register_dais(s3c_ac97_dai, ARRAY_SIZE(s3c_ac97_dai));
	if (ret)
		goto err5;

	return 0;

err5:
	free_irq(irq_res->start, NULL);
err4:
err3:
	clk_disable(s3c_ac97.ac97_clk);
	clk_put(s3c_ac97.ac97_clk);
err2:
	iounmap(s3c_ac97.regs);
err1:
	release_mem_region(mem_res->start, resource_size(mem_res));

	return ret;
}

static __devexit int s3c_ac97_remove(struct platform_device *pdev)
{
	struct resource *mem_res, *irq_res;

	snd_soc_unregister_dais(s3c_ac97_dai, ARRAY_SIZE(s3c_ac97_dai));

	irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (irq_res)
		free_irq(irq_res->start, NULL);

	clk_disable(s3c_ac97.ac97_clk);
	clk_put(s3c_ac97.ac97_clk);

	iounmap(s3c_ac97.regs);

	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (mem_res)
		release_mem_region(mem_res->start, resource_size(mem_res));

	return 0;
}

static struct platform_driver s3c_ac97_driver = {
	.probe  = s3c_ac97_probe,
	.remove = s3c_ac97_remove,
	.driver = {
		.name = "s3c-ac97",
		.owner = THIS_MODULE,
	},
};

static int __init s3c_ac97_init(void)
{
	return platform_driver_register(&s3c_ac97_driver);
}
module_init(s3c_ac97_init);

static void __exit s3c_ac97_exit(void)
{
	platform_driver_unregister(&s3c_ac97_driver);
}
module_exit(s3c_ac97_exit);

MODULE_AUTHOR("Jaswinder Singh, <jassi.brar@samsung.com>");
MODULE_DESCRIPTION("AC97 driver for the Samsung SoC");
MODULE_LICENSE("GPL");
Commit	Line	Data
fc93ea2f JB	1	/* sound/soc/s3c24xx/s3c-ac97.c
	2	*
	3	* ALSA SoC Audio Layer - S3C AC97 Controller driver
	4	* Evolved from s3c2443-ac97.c
	5	*
	6	* Copyright (c) 2010 Samsung Electronics Co. Ltd
	7	* Author: Jaswinder Singh <jassi.brar@samsung.com>
	8	* Credits: Graeme Gregory, Sean Choi
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/module.h>
	17	#include <linux/io.h>
	18	#include <linux/delay.h>
	19	#include <linux/clk.h>
	20
	21	#include <sound/soc.h>
	22
	23	#include <plat/regs-ac97.h>
	24	#include <mach/dma.h>
	25	#include <plat/audio.h>
	26
	27	#include "s3c-dma.h"
	28	#include "s3c-ac97.h"
	29
	30	#define AC_CMD_ADDR(x) (x << 16)
	31	#define AC_CMD_DATA(x) (x & 0xffff)
	32
	33	struct s3c_ac97_info {
	34	unsigned state;
	35	struct clk *ac97_clk;
	36	void __iomem *regs;
	37	struct mutex lock;
	38	struct completion done;
	39	};
	40	static struct s3c_ac97_info s3c_ac97;
	41
	42	static struct s3c2410_dma_client s3c_dma_client_out = {
	43	.name = "AC97 PCMOut"
	44	};
	45
	46	static struct s3c2410_dma_client s3c_dma_client_in = {
	47	.name = "AC97 PCMIn"
	48	};
	49
	50	static struct s3c2410_dma_client s3c_dma_client_micin = {
	51	.name = "AC97 MicIn"
	52	};
	53
	54	static struct s3c_dma_params s3c_ac97_pcm_out = {
	55	.client = &s3c_dma_client_out,
	56	.dma_size = 4,
	57	};
	58
	59	static struct s3c_dma_params s3c_ac97_pcm_in = {
	60	.client = &s3c_dma_client_in,
	61	.dma_size = 4,
	62	};
	63
	64	static struct s3c_dma_params s3c_ac97_mic_in = {
65	.client = &s3c_dma_client_micin,
66	.dma_size = 4,
67	};
68
69	static void s3c_ac97_activate(struct snd_ac97 *ac97)
70	{
71	u32 ac_glbctrl, stat;
72
73	stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
74	if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
75	return; /* Return if already active */
76
77	INIT_COMPLETION(s3c_ac97.done);
78
79	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
80	ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
81	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
82	msleep(1);
83
84	ac_glbctrl \|= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
85	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
86	msleep(1);
87
88	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
89	ac_glbctrl \|= S3C_AC97_GLBCTRL_CODECREADYIE;
90	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
91
92	if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
93	printk(KERN_ERR "AC97: Unable to activate!");
94	}
95
96	static unsigned short s3c_ac97_read(struct snd_ac97 *ac97,
97	unsigned short reg)
98	{
99	u32 ac_glbctrl, ac_codec_cmd;
100	u32 stat, addr, data;
101
102	mutex_lock(&s3c_ac97.lock);
103
104	s3c_ac97_activate(ac97);
105
106	INIT_COMPLETION(s3c_ac97.done);
107
108	ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
109	ac_codec_cmd = S3C_AC97_CODEC_CMD_READ \| AC_CMD_ADDR(reg);
110	writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
111
112	udelay(50);
113
114	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
115	ac_glbctrl \|= S3C_AC97_GLBCTRL_CODECREADYIE;
116	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
117
118	if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
119	printk(KERN_ERR "AC97: Unable to read!");
120
121	stat = readl(s3c_ac97.regs + S3C_AC97_STAT);
122	addr = (stat >> 16) & 0x7f;
123	data = (stat & 0xffff);
124
125	if (addr != reg)
126	printk(KERN_ERR "s3c-ac97: req addr = %02x, rep addr = %02x\n", reg, addr);
127
128	mutex_unlock(&s3c_ac97.lock);
129
130	return (unsigned short)data;
131	}
132
133	static void s3c_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
134	unsigned short val)
135	{
136	u32 ac_glbctrl, ac_codec_cmd;
137
138	mutex_lock(&s3c_ac97.lock);
139
140	s3c_ac97_activate(ac97);
141
142	INIT_COMPLETION(s3c_ac97.done);
143
144	ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
145	ac_codec_cmd = AC_CMD_ADDR(reg) \| AC_CMD_DATA(val);
146	writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
147
148	udelay(50);
149
150	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
151	ac_glbctrl \|= S3C_AC97_GLBCTRL_CODECREADYIE;
152	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
153
154	if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
155	printk(KERN_ERR "AC97: Unable to write!");
156
157	ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
158	ac_codec_cmd \|= S3C_AC97_CODEC_CMD_READ;
159	writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
160
161	mutex_unlock(&s3c_ac97.lock);
162	}
163
164	static void s3c_ac97_cold_reset(struct snd_ac97 *ac97)
165	{
166	writel(S3C_AC97_GLBCTRL_COLDRESET,
167	s3c_ac97.regs + S3C_AC97_GLBCTRL);
168	msleep(1);
169
170	writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
171	msleep(1);
172	}
173
174	static void s3c_ac97_warm_reset(struct snd_ac97 *ac97)
175	{
176	u32 stat;
177
178	stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
179	if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
180	return; /* Return if already active */
181
182	writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL);
183	msleep(1);
184
185	writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
186	msleep(1);
187
188	s3c_ac97_activate(ac97);
189	}
190
191	static irqreturn_t s3c_ac97_irq(int irq, void *dev_id)
192	{
193	u32 ac_glbctrl, ac_glbstat;
194
195	ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT);
196
197	if (ac_glbstat & S3C_AC97_GLBSTAT_CODECREADY) {
198
199	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
200	ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
201	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
202
203	complete(&s3c_ac97.done);
204	}
205
206	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
207	ac_glbctrl \|= (1<<30); /* Clear interrupt */
208	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
209
210	return IRQ_HANDLED;
211	}
212
213	struct snd_ac97_bus_ops soc_ac97_ops = {
214	.read = s3c_ac97_read,
215	.write = s3c_ac97_write,
216	.warm_reset = s3c_ac97_warm_reset,
217	.reset = s3c_ac97_cold_reset,
218	};
219	EXPORT_SYMBOL_GPL(soc_ac97_ops);
220
221	static int s3c_ac97_hw_params(struct snd_pcm_substream *substream,
222	struct snd_pcm_hw_params *params,
223	struct snd_soc_dai *dai)
224	{
225	struct snd_soc_pcm_runtime *rtd = substream->private_data;
226	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
5f712b2b	227	struct s3c_dma_params *dma_data;
fc93ea2f JB	228
fc93ea2f JB	229	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5f712b2b	230	dma_data = &s3c_ac97_pcm_out;
fc93ea2f	231	else
5f712b2b DM	232	dma_data = &s3c_ac97_pcm_in;
	233
	234	snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
fc93ea2f JB	235
	236	return 0;
	237	}
	238
	239	static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
	240	struct snd_soc_dai *dai)
	241	{
	242	u32 ac_glbctrl;
	243	struct snd_soc_pcm_runtime *rtd = substream->private_data;
5f712b2b DM	244	struct s3c_dma_params *dma_data =
5f712b2b DM	245	snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream);
fc93ea2f JB	246
	247	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
	248	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	249	ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
	250	else
	251	ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
	252
	253	switch (cmd) {
	254	case SNDRV_PCM_TRIGGER_START:
	255	case SNDRV_PCM_TRIGGER_RESUME:
	256	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	257	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	258	ac_glbctrl \|= S3C_AC97_GLBCTRL_PCMINTM_DMA;
	259	else
	260	ac_glbctrl \|= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
	261	break;
	262
	263	case SNDRV_PCM_TRIGGER_STOP:
	264	case SNDRV_PCM_TRIGGER_SUSPEND:
	265	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	266	break;
	267	}
	268
	269	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
	270
5f712b2b	271	s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
fc93ea2f JB	272
	273	return 0;
	274	}
	275
	276	static int s3c_ac97_hw_mic_params(struct snd_pcm_substream *substream,
	277	struct snd_pcm_hw_params *params,
	278	struct snd_soc_dai *dai)
	279	{
	280	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	281	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	282
	283	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	284	return -ENODEV;
	285	else
5f712b2b	286	snd_soc_dai_set_dma_data(cpu_dai, substream, &s3c_ac97_mic_in);
fc93ea2f JB	287
	288	return 0;
	289	}
	290
	291	static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
	292	int cmd, struct snd_soc_dai *dai)
	293	{
	294	u32 ac_glbctrl;
	295	struct snd_soc_pcm_runtime *rtd = substream->private_data;
5f712b2b DM	296	struct s3c_dma_params *dma_data =
5f712b2b DM	297	snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream);
fc93ea2f JB	298
	299	ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
	300	ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK;
	301
	302	switch (cmd) {
	303	case SNDRV_PCM_TRIGGER_START:
	304	case SNDRV_PCM_TRIGGER_RESUME:
	305	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	306	ac_glbctrl \|= S3C_AC97_GLBCTRL_MICINTM_DMA;
	307	break;
	308
	309	case SNDRV_PCM_TRIGGER_STOP:
	310	case SNDRV_PCM_TRIGGER_SUSPEND:
	311	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	312	break;
	313	}
	314
	315	writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
	316
5f712b2b	317	s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
fc93ea2f JB	318
	319	return 0;
	320	}
	321
	322	static struct snd_soc_dai_ops s3c_ac97_dai_ops = {
	323	.hw_params = s3c_ac97_hw_params,
	324	.trigger = s3c_ac97_trigger,
	325	};
	326
	327	static struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = {
	328	.hw_params = s3c_ac97_hw_mic_params,
	329	.trigger = s3c_ac97_mic_trigger,
	330	};
	331
	332	struct snd_soc_dai s3c_ac97_dai[] = {
	333	[S3C_AC97_DAI_PCM] = {
	334	.name = "s3c-ac97",
	335	.id = S3C_AC97_DAI_PCM,
	336	.ac97_control = 1,
	337	.playback = {
	338	.stream_name = "AC97 Playback",
	339	.channels_min = 2,
	340	.channels_max = 2,
	341	.rates = SNDRV_PCM_RATE_8000_48000,
	342	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	343	.capture = {
	344	.stream_name = "AC97 Capture",
	345	.channels_min = 2,
	346	.channels_max = 2,
	347	.rates = SNDRV_PCM_RATE_8000_48000,
	348	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	349	.ops = &s3c_ac97_dai_ops,
	350	},
	351	[S3C_AC97_DAI_MIC] = {
	352	.name = "s3c-ac97-mic",
	353	.id = S3C_AC97_DAI_MIC,
	354	.ac97_control = 1,
	355	.capture = {
	356	.stream_name = "AC97 Mic Capture",
	357	.channels_min = 1,
	358	.channels_max = 1,
	359	.rates = SNDRV_PCM_RATE_8000_48000,
	360	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	361	.ops = &s3c_ac97_mic_dai_ops,
	362	},
	363	};
	364	EXPORT_SYMBOL_GPL(s3c_ac97_dai);
	365
	366	static __devinit int s3c_ac97_probe(struct platform_device *pdev)
	367	{
	368	struct resource mem_res, dmatx_res, dmarx_res, dmamic_res, *irq_res;
	369	struct s3c_audio_pdata *ac97_pdata;
	370	int ret;
	371
	372	ac97_pdata = pdev->dev.platform_data;
	373	if (!ac97_pdata \|\| !ac97_pdata->cfg_gpio) {
	374	dev_err(&pdev->dev, "cfg_gpio callback not provided!\n");
	375	return -EINVAL;
	376	}
	377
	378	/* Check for availability of necessary resource */
	379	dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	380	if (!dmatx_res) {
	381	dev_err(&pdev->dev, "Unable to get AC97-TX dma resource\n");
382	return -ENXIO;
383	}
384
385	dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
386	if (!dmarx_res) {
387	dev_err(&pdev->dev, "Unable to get AC97-RX dma resource\n");
388	return -ENXIO;
389	}
390
391	dmamic_res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
392	if (!dmamic_res) {
393	dev_err(&pdev->dev, "Unable to get AC97-MIC dma resource\n");
394	return -ENXIO;
395	}
396
397	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
398	if (!mem_res) {
399	dev_err(&pdev->dev, "Unable to get register resource\n");
400	return -ENXIO;
401	}
402
403	irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
404	if (!irq_res) {
405	dev_err(&pdev->dev, "AC97 IRQ not provided!\n");
406	return -ENXIO;
407	}
408
409	if (!request_mem_region(mem_res->start,
410	resource_size(mem_res), "s3c-ac97")) {
411	dev_err(&pdev->dev, "Unable to request register region\n");
412	return -EBUSY;
413	}
414
415	s3c_ac97_pcm_out.channel = dmatx_res->start;
416	s3c_ac97_pcm_out.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
417	s3c_ac97_pcm_in.channel = dmarx_res->start;
418	s3c_ac97_pcm_in.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
419	s3c_ac97_mic_in.channel = dmamic_res->start;
420	s3c_ac97_mic_in.dma_addr = mem_res->start + S3C_AC97_MIC_DATA;
421
422	init_completion(&s3c_ac97.done);
423	mutex_init(&s3c_ac97.lock);
424
425	s3c_ac97.regs = ioremap(mem_res->start, resource_size(mem_res));
426	if (s3c_ac97.regs == NULL) {
427	dev_err(&pdev->dev, "Unable to ioremap register region\n");
428	ret = -ENXIO;
429	goto err1;
430	}
431
432	s3c_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
433	if (IS_ERR(s3c_ac97.ac97_clk)) {
434	dev_err(&pdev->dev, "s3c-ac97 failed to get ac97_clock\n");
435	ret = -ENODEV;
436	goto err2;
437	}
438	clk_enable(s3c_ac97.ac97_clk);
439
440	if (ac97_pdata->cfg_gpio(pdev)) {
441	dev_err(&pdev->dev, "Unable to configure gpio\n");
442	ret = -EINVAL;
443	goto err3;
444	}
445
446	ret = request_irq(irq_res->start, s3c_ac97_irq,
447	IRQF_DISABLED, "AC97", NULL);
448	if (ret < 0) {
449	printk(KERN_ERR "s3c-ac97: interrupt request failed.\n");
450	goto err4;
451	}
452
453	s3c_ac97_dai[S3C_AC97_DAI_PCM].dev = &pdev->dev;
454	s3c_ac97_dai[S3C_AC97_DAI_MIC].dev = &pdev->dev;
455
456	ret = snd_soc_register_dais(s3c_ac97_dai, ARRAY_SIZE(s3c_ac97_dai));
457	if (ret)
458	goto err5;
459
460	return 0;
461
462	err5:
463	free_irq(irq_res->start, NULL);
464	err4:
465	err3:
466	clk_disable(s3c_ac97.ac97_clk);
467	clk_put(s3c_ac97.ac97_clk);
468	err2:
469	iounmap(s3c_ac97.regs);
470	err1:
471	release_mem_region(mem_res->start, resource_size(mem_res));
472
473	return ret;
474	}
475
476	static __devexit int s3c_ac97_remove(struct platform_device *pdev)
477	{
478	struct resource mem_res, irq_res;
479
480	snd_soc_unregister_dais(s3c_ac97_dai, ARRAY_SIZE(s3c_ac97_dai));
481
482	irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
483	if (irq_res)
484	free_irq(irq_res->start, NULL);
485
486	clk_disable(s3c_ac97.ac97_clk);
487	clk_put(s3c_ac97.ac97_clk);
488
489	iounmap(s3c_ac97.regs);
490
491	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
492	if (mem_res)
493	release_mem_region(mem_res->start, resource_size(mem_res));
494
495	return 0;
496	}
497
498	static struct platform_driver s3c_ac97_driver = {
499	.probe = s3c_ac97_probe,
500	.remove = s3c_ac97_remove,
501	.driver = {
502	.name = "s3c-ac97",
503	.owner = THIS_MODULE,
504	},
505	};
506
507	static int __init s3c_ac97_init(void)
508	{
509	return platform_driver_register(&s3c_ac97_driver);
510	}
511	module_init(s3c_ac97_init);
512
513	static void __exit s3c_ac97_exit(void)
514	{
515	platform_driver_unregister(&s3c_ac97_driver);
516	}
517	module_exit(s3c_ac97_exit);
518
519	MODULE_AUTHOR("Jaswinder Singh, <jassi.brar@samsung.com>");
520	MODULE_DESCRIPTION("AC97 driver for the Samsung SoC");
521	MODULE_LICENSE("GPL");