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dc85447b BD |
1 | /* sound/soc/s3c24xx/s3c-i2c-v2.c |
2 | * | |
3 | * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs. | |
4 | * | |
5 | * Copyright (c) 2006 Wolfson Microelectronics PLC. | |
6 | * Graeme Gregory graeme.gregory@wolfsonmicro.com | |
7 | * linux@wolfsonmicro.com | |
8 | * | |
9 | * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics | |
10 | * http://armlinux.simtec.co.uk/ | |
11 | * Ben Dooks <ben@simtec.co.uk> | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | ||
dc85447b BD |
19 | #include <linux/delay.h> |
20 | #include <linux/clk.h> | |
dc85447b BD |
21 | #include <linux/io.h> |
22 | ||
dc85447b BD |
23 | #include <sound/pcm.h> |
24 | #include <sound/pcm_params.h> | |
dc85447b BD |
25 | #include <sound/soc.h> |
26 | ||
27 | #include <plat/regs-s3c2412-iis.h> | |
28 | ||
dc85447b BD |
29 | #include <mach/dma.h> |
30 | ||
31 | #include "s3c-i2s-v2.h" | |
d3ff5a3e | 32 | #include "s3c-dma.h" |
dc85447b | 33 | |
8a0f62b8 MB |
34 | #undef S3C_IIS_V2_SUPPORTED |
35 | ||
36 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) | |
37 | #define S3C_IIS_V2_SUPPORTED | |
38 | #endif | |
39 | ||
40 | #ifdef CONFIG_PLAT_S3C64XX | |
41 | #define S3C_IIS_V2_SUPPORTED | |
42 | #endif | |
43 | ||
44 | #ifndef S3C_IIS_V2_SUPPORTED | |
45 | #error Unsupported CPU model | |
46 | #endif | |
47 | ||
dc85447b | 48 | #define S3C2412_I2S_DEBUG_CON 0 |
dc85447b BD |
49 | |
50 | static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai) | |
51 | { | |
52 | return cpu_dai->private_data; | |
53 | } | |
54 | ||
55 | #define bit_set(v, b) (((v) & (b)) ? 1 : 0) | |
56 | ||
57 | #if S3C2412_I2S_DEBUG_CON | |
58 | static void dbg_showcon(const char *fn, u32 con) | |
59 | { | |
60 | printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn, | |
61 | bit_set(con, S3C2412_IISCON_LRINDEX), | |
62 | bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY), | |
63 | bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY), | |
64 | bit_set(con, S3C2412_IISCON_TXFIFO_FULL), | |
65 | bit_set(con, S3C2412_IISCON_RXFIFO_FULL)); | |
66 | ||
67 | printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n", | |
68 | fn, | |
69 | bit_set(con, S3C2412_IISCON_TXDMA_PAUSE), | |
70 | bit_set(con, S3C2412_IISCON_RXDMA_PAUSE), | |
71 | bit_set(con, S3C2412_IISCON_TXCH_PAUSE), | |
72 | bit_set(con, S3C2412_IISCON_RXCH_PAUSE)); | |
73 | printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn, | |
74 | bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE), | |
75 | bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE), | |
76 | bit_set(con, S3C2412_IISCON_IIS_ACTIVE)); | |
77 | } | |
78 | #else | |
79 | static inline void dbg_showcon(const char *fn, u32 con) | |
80 | { | |
81 | } | |
82 | #endif | |
83 | ||
84 | ||
85 | /* Turn on or off the transmission path. */ | |
abbc8246 | 86 | static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on) |
dc85447b BD |
87 | { |
88 | void __iomem *regs = i2s->regs; | |
89 | u32 fic, con, mod; | |
90 | ||
ee7d4767 | 91 | pr_debug("%s(%d)\n", __func__, on); |
dc85447b BD |
92 | |
93 | fic = readl(regs + S3C2412_IISFIC); | |
94 | con = readl(regs + S3C2412_IISCON); | |
95 | mod = readl(regs + S3C2412_IISMOD); | |
96 | ||
ee7d4767 | 97 | pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic); |
dc85447b BD |
98 | |
99 | if (on) { | |
100 | con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE; | |
101 | con &= ~S3C2412_IISCON_TXDMA_PAUSE; | |
102 | con &= ~S3C2412_IISCON_TXCH_PAUSE; | |
103 | ||
104 | switch (mod & S3C2412_IISMOD_MODE_MASK) { | |
105 | case S3C2412_IISMOD_MODE_TXONLY: | |
106 | case S3C2412_IISMOD_MODE_TXRX: | |
107 | /* do nothing, we are in the right mode */ | |
108 | break; | |
109 | ||
110 | case S3C2412_IISMOD_MODE_RXONLY: | |
111 | mod &= ~S3C2412_IISMOD_MODE_MASK; | |
112 | mod |= S3C2412_IISMOD_MODE_TXRX; | |
113 | break; | |
114 | ||
115 | default: | |
abbc8246 MB |
116 | dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n", |
117 | mod & S3C2412_IISMOD_MODE_MASK); | |
118 | break; | |
dc85447b BD |
119 | } |
120 | ||
121 | writel(con, regs + S3C2412_IISCON); | |
122 | writel(mod, regs + S3C2412_IISMOD); | |
123 | } else { | |
124 | /* Note, we do not have any indication that the FIFO problems | |
125 | * tha the S3C2410/2440 had apply here, so we should be able | |
126 | * to disable the DMA and TX without resetting the FIFOS. | |
127 | */ | |
128 | ||
129 | con |= S3C2412_IISCON_TXDMA_PAUSE; | |
130 | con |= S3C2412_IISCON_TXCH_PAUSE; | |
131 | con &= ~S3C2412_IISCON_TXDMA_ACTIVE; | |
132 | ||
133 | switch (mod & S3C2412_IISMOD_MODE_MASK) { | |
134 | case S3C2412_IISMOD_MODE_TXRX: | |
135 | mod &= ~S3C2412_IISMOD_MODE_MASK; | |
136 | mod |= S3C2412_IISMOD_MODE_RXONLY; | |
137 | break; | |
138 | ||
139 | case S3C2412_IISMOD_MODE_TXONLY: | |
140 | mod &= ~S3C2412_IISMOD_MODE_MASK; | |
141 | con &= ~S3C2412_IISCON_IIS_ACTIVE; | |
142 | break; | |
143 | ||
144 | default: | |
abbc8246 MB |
145 | dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n", |
146 | mod & S3C2412_IISMOD_MODE_MASK); | |
147 | break; | |
dc85447b BD |
148 | } |
149 | ||
150 | writel(mod, regs + S3C2412_IISMOD); | |
151 | writel(con, regs + S3C2412_IISCON); | |
152 | } | |
153 | ||
154 | fic = readl(regs + S3C2412_IISFIC); | |
155 | dbg_showcon(__func__, con); | |
ee7d4767 | 156 | pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic); |
dc85447b | 157 | } |
dc85447b | 158 | |
abbc8246 | 159 | static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on) |
dc85447b BD |
160 | { |
161 | void __iomem *regs = i2s->regs; | |
162 | u32 fic, con, mod; | |
163 | ||
ee7d4767 | 164 | pr_debug("%s(%d)\n", __func__, on); |
dc85447b BD |
165 | |
166 | fic = readl(regs + S3C2412_IISFIC); | |
167 | con = readl(regs + S3C2412_IISCON); | |
168 | mod = readl(regs + S3C2412_IISMOD); | |
169 | ||
ee7d4767 | 170 | pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic); |
dc85447b BD |
171 | |
172 | if (on) { | |
173 | con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE; | |
174 | con &= ~S3C2412_IISCON_RXDMA_PAUSE; | |
175 | con &= ~S3C2412_IISCON_RXCH_PAUSE; | |
176 | ||
177 | switch (mod & S3C2412_IISMOD_MODE_MASK) { | |
178 | case S3C2412_IISMOD_MODE_TXRX: | |
179 | case S3C2412_IISMOD_MODE_RXONLY: | |
180 | /* do nothing, we are in the right mode */ | |
181 | break; | |
182 | ||
183 | case S3C2412_IISMOD_MODE_TXONLY: | |
184 | mod &= ~S3C2412_IISMOD_MODE_MASK; | |
185 | mod |= S3C2412_IISMOD_MODE_TXRX; | |
186 | break; | |
187 | ||
188 | default: | |
abbc8246 MB |
189 | dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n", |
190 | mod & S3C2412_IISMOD_MODE_MASK); | |
dc85447b BD |
191 | } |
192 | ||
193 | writel(mod, regs + S3C2412_IISMOD); | |
194 | writel(con, regs + S3C2412_IISCON); | |
195 | } else { | |
196 | /* See txctrl notes on FIFOs. */ | |
197 | ||
198 | con &= ~S3C2412_IISCON_RXDMA_ACTIVE; | |
199 | con |= S3C2412_IISCON_RXDMA_PAUSE; | |
200 | con |= S3C2412_IISCON_RXCH_PAUSE; | |
201 | ||
202 | switch (mod & S3C2412_IISMOD_MODE_MASK) { | |
203 | case S3C2412_IISMOD_MODE_RXONLY: | |
204 | con &= ~S3C2412_IISCON_IIS_ACTIVE; | |
205 | mod &= ~S3C2412_IISMOD_MODE_MASK; | |
206 | break; | |
207 | ||
208 | case S3C2412_IISMOD_MODE_TXRX: | |
209 | mod &= ~S3C2412_IISMOD_MODE_MASK; | |
210 | mod |= S3C2412_IISMOD_MODE_TXONLY; | |
211 | break; | |
212 | ||
213 | default: | |
abbc8246 MB |
214 | dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n", |
215 | mod & S3C2412_IISMOD_MODE_MASK); | |
dc85447b BD |
216 | } |
217 | ||
218 | writel(con, regs + S3C2412_IISCON); | |
219 | writel(mod, regs + S3C2412_IISMOD); | |
220 | } | |
221 | ||
222 | fic = readl(regs + S3C2412_IISFIC); | |
ee7d4767 | 223 | pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic); |
dc85447b | 224 | } |
dc85447b | 225 | |
fa68e002 J |
226 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) |
227 | ||
dc85447b BD |
228 | /* |
229 | * Wait for the LR signal to allow synchronisation to the L/R clock | |
230 | * from the codec. May only be needed for slave mode. | |
231 | */ | |
232 | static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s) | |
233 | { | |
234 | u32 iiscon; | |
fa68e002 | 235 | unsigned long loops = msecs_to_loops(5); |
dc85447b | 236 | |
ee7d4767 | 237 | pr_debug("Entered %s\n", __func__); |
dc85447b | 238 | |
fa68e002 | 239 | while (--loops) { |
dc85447b BD |
240 | iiscon = readl(i2s->regs + S3C2412_IISCON); |
241 | if (iiscon & S3C2412_IISCON_LRINDEX) | |
242 | break; | |
243 | ||
fa68e002 J |
244 | cpu_relax(); |
245 | } | |
246 | ||
247 | if (!loops) { | |
248 | printk(KERN_ERR "%s: timeout\n", __func__); | |
249 | return -ETIMEDOUT; | |
dc85447b BD |
250 | } |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
255 | /* | |
256 | * Set S3C2412 I2S DAI format | |
257 | */ | |
258 | static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai, | |
259 | unsigned int fmt) | |
260 | { | |
261 | struct s3c_i2sv2_info *i2s = to_info(cpu_dai); | |
262 | u32 iismod; | |
263 | ||
ee7d4767 | 264 | pr_debug("Entered %s\n", __func__); |
dc85447b BD |
265 | |
266 | iismod = readl(i2s->regs + S3C2412_IISMOD); | |
ee7d4767 | 267 | pr_debug("hw_params r: IISMOD: %x \n", iismod); |
dc85447b BD |
268 | |
269 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) | |
270 | #define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK | |
271 | #define IISMOD_SLAVE S3C2412_IISMOD_SLAVE | |
272 | #define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL | |
273 | #endif | |
274 | ||
275 | #if defined(CONFIG_PLAT_S3C64XX) | |
276 | /* From Rev1.1 datasheet, we have two master and two slave modes: | |
277 | * IMS[11:10]: | |
278 | * 00 = master mode, fed from PCLK | |
279 | * 01 = master mode, fed from CLKAUDIO | |
280 | * 10 = slave mode, using PCLK | |
281 | * 11 = slave mode, using I2SCLK | |
282 | */ | |
283 | #define IISMOD_MASTER_MASK (1 << 11) | |
284 | #define IISMOD_SLAVE (1 << 11) | |
553b1dd5 | 285 | #define IISMOD_MASTER (0 << 11) |
dc85447b BD |
286 | #endif |
287 | ||
288 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
289 | case SND_SOC_DAIFMT_CBM_CFM: | |
290 | i2s->master = 0; | |
291 | iismod &= ~IISMOD_MASTER_MASK; | |
292 | iismod |= IISMOD_SLAVE; | |
293 | break; | |
294 | case SND_SOC_DAIFMT_CBS_CFS: | |
295 | i2s->master = 1; | |
296 | iismod &= ~IISMOD_MASTER_MASK; | |
297 | iismod |= IISMOD_MASTER; | |
298 | break; | |
299 | default: | |
38e43c81 | 300 | pr_err("unknwon master/slave format\n"); |
dc85447b BD |
301 | return -EINVAL; |
302 | } | |
303 | ||
304 | iismod &= ~S3C2412_IISMOD_SDF_MASK; | |
305 | ||
306 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
307 | case SND_SOC_DAIFMT_RIGHT_J: | |
fd5ad654 | 308 | iismod |= S3C2412_IISMOD_LR_RLOW; |
dc85447b BD |
309 | iismod |= S3C2412_IISMOD_SDF_MSB; |
310 | break; | |
311 | case SND_SOC_DAIFMT_LEFT_J: | |
fd5ad654 | 312 | iismod |= S3C2412_IISMOD_LR_RLOW; |
dc85447b BD |
313 | iismod |= S3C2412_IISMOD_SDF_LSB; |
314 | break; | |
315 | case SND_SOC_DAIFMT_I2S: | |
fd5ad654 | 316 | iismod &= ~S3C2412_IISMOD_LR_RLOW; |
dc85447b BD |
317 | iismod |= S3C2412_IISMOD_SDF_IIS; |
318 | break; | |
319 | default: | |
38e43c81 | 320 | pr_err("Unknown data format\n"); |
dc85447b BD |
321 | return -EINVAL; |
322 | } | |
323 | ||
324 | writel(iismod, i2s->regs + S3C2412_IISMOD); | |
ee7d4767 | 325 | pr_debug("hw_params w: IISMOD: %x \n", iismod); |
dc85447b BD |
326 | return 0; |
327 | } | |
328 | ||
9c9b1257 | 329 | static int s3c_i2sv2_hw_params(struct snd_pcm_substream *substream, |
dc85447b BD |
330 | struct snd_pcm_hw_params *params, |
331 | struct snd_soc_dai *socdai) | |
332 | { | |
333 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
334 | struct snd_soc_dai_link *dai = rtd->dai; | |
335 | struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai); | |
336 | u32 iismod; | |
337 | ||
ee7d4767 | 338 | pr_debug("Entered %s\n", __func__); |
dc85447b BD |
339 | |
340 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
341 | dai->cpu_dai->dma_data = i2s->dma_playback; | |
342 | else | |
343 | dai->cpu_dai->dma_data = i2s->dma_capture; | |
344 | ||
345 | /* Working copies of register */ | |
346 | iismod = readl(i2s->regs + S3C2412_IISMOD); | |
ee7d4767 | 347 | pr_debug("%s: r: IISMOD: %x\n", __func__, iismod); |
dc85447b | 348 | |
bf328826 | 349 | iismod &= ~S3C64XX_IISMOD_BLC_MASK; |
553b1dd5 MB |
350 | /* Sample size */ |
351 | switch (params_format(params)) { | |
352 | case SNDRV_PCM_FORMAT_S8: | |
bf328826 | 353 | iismod |= S3C64XX_IISMOD_BLC_8BIT; |
553b1dd5 MB |
354 | break; |
355 | case SNDRV_PCM_FORMAT_S16_LE: | |
553b1dd5 MB |
356 | break; |
357 | case SNDRV_PCM_FORMAT_S24_LE: | |
bf328826 | 358 | iismod |= S3C64XX_IISMOD_BLC_24BIT; |
553b1dd5 MB |
359 | break; |
360 | } | |
dc85447b BD |
361 | |
362 | writel(iismod, i2s->regs + S3C2412_IISMOD); | |
ee7d4767 | 363 | pr_debug("%s: w: IISMOD: %x\n", __func__, iismod); |
dc85447b BD |
364 | return 0; |
365 | } | |
366 | ||
367 | static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd, | |
368 | struct snd_soc_dai *dai) | |
369 | { | |
370 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
371 | struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai); | |
372 | int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE); | |
373 | unsigned long irqs; | |
374 | int ret = 0; | |
faa31776 | 375 | int channel = ((struct s3c_dma_params *) |
faf907c7 | 376 | rtd->dai->cpu_dai->dma_data)->channel; |
dc85447b | 377 | |
ee7d4767 | 378 | pr_debug("Entered %s\n", __func__); |
dc85447b BD |
379 | |
380 | switch (cmd) { | |
381 | case SNDRV_PCM_TRIGGER_START: | |
382 | /* On start, ensure that the FIFOs are cleared and reset. */ | |
383 | ||
384 | writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH, | |
385 | i2s->regs + S3C2412_IISFIC); | |
386 | ||
387 | /* clear again, just in case */ | |
388 | writel(0x0, i2s->regs + S3C2412_IISFIC); | |
389 | ||
390 | case SNDRV_PCM_TRIGGER_RESUME: | |
391 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
392 | if (!i2s->master) { | |
393 | ret = s3c2412_snd_lrsync(i2s); | |
394 | if (ret) | |
395 | goto exit_err; | |
396 | } | |
397 | ||
398 | local_irq_save(irqs); | |
399 | ||
400 | if (capture) | |
401 | s3c2412_snd_rxctrl(i2s, 1); | |
402 | else | |
403 | s3c2412_snd_txctrl(i2s, 1); | |
404 | ||
405 | local_irq_restore(irqs); | |
faf907c7 SL |
406 | |
407 | /* | |
408 | * Load the next buffer to DMA to meet the reqirement | |
409 | * of the auto reload mechanism of S3C24XX. | |
410 | * This call won't bother S3C64XX. | |
411 | */ | |
412 | s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED); | |
413 | ||
dc85447b BD |
414 | break; |
415 | ||
416 | case SNDRV_PCM_TRIGGER_STOP: | |
417 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
418 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
419 | local_irq_save(irqs); | |
420 | ||
421 | if (capture) | |
422 | s3c2412_snd_rxctrl(i2s, 0); | |
423 | else | |
424 | s3c2412_snd_txctrl(i2s, 0); | |
425 | ||
426 | local_irq_restore(irqs); | |
427 | break; | |
428 | default: | |
429 | ret = -EINVAL; | |
430 | break; | |
431 | } | |
432 | ||
433 | exit_err: | |
434 | return ret; | |
435 | } | |
436 | ||
437 | /* | |
438 | * Set S3C2412 Clock dividers | |
439 | */ | |
440 | static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai, | |
441 | int div_id, int div) | |
442 | { | |
443 | struct s3c_i2sv2_info *i2s = to_info(cpu_dai); | |
444 | u32 reg; | |
445 | ||
ee7d4767 | 446 | pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div); |
dc85447b BD |
447 | |
448 | switch (div_id) { | |
449 | case S3C_I2SV2_DIV_BCLK: | |
51c6ab13 JB |
450 | switch (div) { |
451 | case 16: | |
452 | div = S3C2412_IISMOD_BCLK_16FS; | |
453 | break; | |
fd5ad654 | 454 | |
51c6ab13 JB |
455 | case 32: |
456 | div = S3C2412_IISMOD_BCLK_32FS; | |
457 | break; | |
fd5ad654 | 458 | |
51c6ab13 JB |
459 | case 24: |
460 | div = S3C2412_IISMOD_BCLK_24FS; | |
461 | break; | |
fd5ad654 | 462 | |
51c6ab13 JB |
463 | case 48: |
464 | div = S3C2412_IISMOD_BCLK_48FS; | |
465 | break; | |
fd5ad654 | 466 | |
51c6ab13 JB |
467 | default: |
468 | return -EINVAL; | |
fd5ad654 J |
469 | } |
470 | ||
dc85447b BD |
471 | reg = readl(i2s->regs + S3C2412_IISMOD); |
472 | reg &= ~S3C2412_IISMOD_BCLK_MASK; | |
473 | writel(reg | div, i2s->regs + S3C2412_IISMOD); | |
474 | ||
ee7d4767 | 475 | pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD)); |
dc85447b BD |
476 | break; |
477 | ||
478 | case S3C_I2SV2_DIV_RCLK: | |
51c6ab13 JB |
479 | switch (div) { |
480 | case 256: | |
481 | div = S3C2412_IISMOD_RCLK_256FS; | |
482 | break; | |
dc85447b | 483 | |
51c6ab13 JB |
484 | case 384: |
485 | div = S3C2412_IISMOD_RCLK_384FS; | |
486 | break; | |
dc85447b | 487 | |
51c6ab13 JB |
488 | case 512: |
489 | div = S3C2412_IISMOD_RCLK_512FS; | |
490 | break; | |
dc85447b | 491 | |
51c6ab13 JB |
492 | case 768: |
493 | div = S3C2412_IISMOD_RCLK_768FS; | |
494 | break; | |
dc85447b | 495 | |
51c6ab13 JB |
496 | default: |
497 | return -EINVAL; | |
dc85447b BD |
498 | } |
499 | ||
500 | reg = readl(i2s->regs + S3C2412_IISMOD); | |
501 | reg &= ~S3C2412_IISMOD_RCLK_MASK; | |
502 | writel(reg | div, i2s->regs + S3C2412_IISMOD); | |
ee7d4767 | 503 | pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD)); |
dc85447b BD |
504 | break; |
505 | ||
506 | case S3C_I2SV2_DIV_PRESCALER: | |
507 | if (div >= 0) { | |
508 | writel((div << 8) | S3C2412_IISPSR_PSREN, | |
509 | i2s->regs + S3C2412_IISPSR); | |
510 | } else { | |
511 | writel(0x0, i2s->regs + S3C2412_IISPSR); | |
512 | } | |
ee7d4767 | 513 | pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR)); |
dc85447b BD |
514 | break; |
515 | ||
516 | default: | |
517 | return -EINVAL; | |
518 | } | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
1ca75780 MB |
523 | static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream, |
524 | struct snd_soc_dai *dai) | |
525 | { | |
526 | struct s3c_i2sv2_info *i2s = to_info(dai); | |
527 | u32 reg = readl(i2s->regs + S3C2412_IISFIC); | |
528 | snd_pcm_sframes_t delay; | |
529 | ||
530 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
531 | delay = S3C2412_IISFIC_TXCOUNT(reg); | |
532 | else | |
533 | delay = S3C2412_IISFIC_RXCOUNT(reg); | |
534 | ||
535 | return delay; | |
536 | } | |
537 | ||
dc85447b BD |
538 | /* default table of all avaialable root fs divisors */ |
539 | static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 }; | |
540 | ||
1d2b7ae9 BD |
541 | int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info, |
542 | unsigned int *fstab, | |
543 | unsigned int rate, struct clk *clk) | |
dc85447b BD |
544 | { |
545 | unsigned long clkrate = clk_get_rate(clk); | |
546 | unsigned int div; | |
547 | unsigned int fsclk; | |
548 | unsigned int actual; | |
549 | unsigned int fs; | |
550 | unsigned int fsdiv; | |
551 | signed int deviation = 0; | |
552 | unsigned int best_fs = 0; | |
553 | unsigned int best_div = 0; | |
554 | unsigned int best_rate = 0; | |
555 | unsigned int best_deviation = INT_MAX; | |
556 | ||
af3ea7bd MB |
557 | pr_debug("Input clock rate %ldHz\n", clkrate); |
558 | ||
dc85447b BD |
559 | if (fstab == NULL) |
560 | fstab = iis_fs_tab; | |
561 | ||
562 | for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) { | |
563 | fsdiv = iis_fs_tab[fs]; | |
564 | ||
565 | fsclk = clkrate / fsdiv; | |
566 | div = fsclk / rate; | |
567 | ||
568 | if ((fsclk % rate) > (rate / 2)) | |
569 | div++; | |
570 | ||
571 | if (div <= 1) | |
572 | continue; | |
573 | ||
574 | actual = clkrate / (fsdiv * div); | |
575 | deviation = actual - rate; | |
576 | ||
449bd54d | 577 | printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n", |
dc85447b BD |
578 | fsdiv, div, actual, deviation); |
579 | ||
580 | deviation = abs(deviation); | |
581 | ||
582 | if (deviation < best_deviation) { | |
583 | best_fs = fsdiv; | |
584 | best_div = div; | |
585 | best_rate = actual; | |
586 | best_deviation = deviation; | |
587 | } | |
588 | ||
589 | if (deviation == 0) | |
590 | break; | |
591 | } | |
592 | ||
449bd54d | 593 | printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n", |
dc85447b BD |
594 | best_fs, best_div, best_rate); |
595 | ||
596 | info->fs_div = best_fs; | |
597 | info->clk_div = best_div; | |
598 | ||
599 | return 0; | |
600 | } | |
1d2b7ae9 | 601 | EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate); |
dc85447b BD |
602 | |
603 | int s3c_i2sv2_probe(struct platform_device *pdev, | |
604 | struct snd_soc_dai *dai, | |
605 | struct s3c_i2sv2_info *i2s, | |
606 | unsigned long base) | |
607 | { | |
608 | struct device *dev = &pdev->dev; | |
07736d48 | 609 | unsigned int iismod; |
dc85447b BD |
610 | |
611 | i2s->dev = dev; | |
612 | ||
613 | /* record our i2s structure for later use in the callbacks */ | |
614 | dai->private_data = i2s; | |
615 | ||
c86bde54 MB |
616 | if (!base) { |
617 | struct resource *res = platform_get_resource(pdev, | |
618 | IORESOURCE_MEM, | |
619 | 0); | |
620 | if (!res) { | |
621 | dev_err(dev, "Unable to get register resource\n"); | |
622 | return -ENXIO; | |
623 | } | |
624 | ||
625 | if (!request_mem_region(res->start, resource_size(res), | |
626 | "s3c64xx-i2s-v4")) { | |
627 | dev_err(dev, "Unable to request register region\n"); | |
628 | return -EBUSY; | |
629 | } | |
630 | ||
631 | base = res->start; | |
632 | } | |
633 | ||
dc85447b BD |
634 | i2s->regs = ioremap(base, 0x100); |
635 | if (i2s->regs == NULL) { | |
636 | dev_err(dev, "cannot ioremap registers\n"); | |
637 | return -ENXIO; | |
638 | } | |
639 | ||
640 | i2s->iis_pclk = clk_get(dev, "iis"); | |
fd5ad654 | 641 | if (IS_ERR(i2s->iis_pclk)) { |
b52a5195 | 642 | dev_err(dev, "failed to get iis_clock\n"); |
dc85447b BD |
643 | iounmap(i2s->regs); |
644 | return -ENOENT; | |
645 | } | |
646 | ||
647 | clk_enable(i2s->iis_pclk); | |
648 | ||
07736d48 MB |
649 | /* Mark ourselves as in TXRX mode so we can run through our cleanup |
650 | * process without warnings. */ | |
651 | iismod = readl(i2s->regs + S3C2412_IISMOD); | |
652 | iismod |= S3C2412_IISMOD_MODE_TXRX; | |
653 | writel(iismod, i2s->regs + S3C2412_IISMOD); | |
dc85447b BD |
654 | s3c2412_snd_txctrl(i2s, 0); |
655 | s3c2412_snd_rxctrl(i2s, 0); | |
656 | ||
657 | return 0; | |
658 | } | |
dc85447b BD |
659 | EXPORT_SYMBOL_GPL(s3c_i2sv2_probe); |
660 | ||
661 | #ifdef CONFIG_PM | |
662 | static int s3c2412_i2s_suspend(struct snd_soc_dai *dai) | |
663 | { | |
664 | struct s3c_i2sv2_info *i2s = to_info(dai); | |
665 | u32 iismod; | |
666 | ||
667 | if (dai->active) { | |
668 | i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD); | |
669 | i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON); | |
670 | i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR); | |
671 | ||
672 | /* some basic suspend checks */ | |
673 | ||
674 | iismod = readl(i2s->regs + S3C2412_IISMOD); | |
675 | ||
676 | if (iismod & S3C2412_IISCON_RXDMA_ACTIVE) | |
677 | pr_warning("%s: RXDMA active?\n", __func__); | |
678 | ||
679 | if (iismod & S3C2412_IISCON_TXDMA_ACTIVE) | |
680 | pr_warning("%s: TXDMA active?\n", __func__); | |
681 | ||
682 | if (iismod & S3C2412_IISCON_IIS_ACTIVE) | |
683 | pr_warning("%s: IIS active\n", __func__); | |
684 | } | |
685 | ||
686 | return 0; | |
687 | } | |
688 | ||
689 | static int s3c2412_i2s_resume(struct snd_soc_dai *dai) | |
690 | { | |
691 | struct s3c_i2sv2_info *i2s = to_info(dai); | |
692 | ||
693 | pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n", | |
694 | dai->active, i2s->suspend_iismod, i2s->suspend_iiscon); | |
695 | ||
696 | if (dai->active) { | |
697 | writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON); | |
698 | writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD); | |
699 | writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR); | |
700 | ||
701 | writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH, | |
702 | i2s->regs + S3C2412_IISFIC); | |
703 | ||
704 | ndelay(250); | |
705 | writel(0x0, i2s->regs + S3C2412_IISFIC); | |
706 | } | |
707 | ||
708 | return 0; | |
709 | } | |
710 | #else | |
711 | #define s3c2412_i2s_suspend NULL | |
712 | #define s3c2412_i2s_resume NULL | |
713 | #endif | |
714 | ||
715 | int s3c_i2sv2_register_dai(struct snd_soc_dai *dai) | |
716 | { | |
3715c6aa BD |
717 | struct snd_soc_dai_ops *ops = dai->ops; |
718 | ||
719 | ops->trigger = s3c2412_i2s_trigger; | |
9c9b1257 JB |
720 | if (!ops->hw_params) |
721 | ops->hw_params = s3c_i2sv2_hw_params; | |
3715c6aa BD |
722 | ops->set_fmt = s3c2412_i2s_set_fmt; |
723 | ops->set_clkdiv = s3c2412_i2s_set_clkdiv; | |
dc85447b | 724 | |
1ca75780 MB |
725 | /* Allow overriding by (for example) IISv4 */ |
726 | if (!ops->delay) | |
08226614 | 727 | ops->delay = s3c2412_i2s_delay; |
1ca75780 | 728 | |
dc85447b BD |
729 | dai->suspend = s3c2412_i2s_suspend; |
730 | dai->resume = s3c2412_i2s_resume; | |
731 | ||
732 | return snd_soc_register_dai(dai); | |
733 | } | |
dc85447b | 734 | EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai); |
a396e32e MB |
735 | |
736 | MODULE_LICENSE("GPL"); |